EEE 335 Analog and Digital Circuits (4)

Instructor: Professor Trevor Thornton; e-mail: trevor.thornton@asu.edu

Class time: Tu / Th 9:00 am – 10:15 am SCOB 150 A118

Office Hours: Room ERC115 – Time: Tues: 3:30 – 4:30 pm; Weds: noon – 1:00 pm,
Thurs: 11am - noon and by prior arrangement.
Lab Hours: TBD – Lab TA: TBD
Credits: 4 Credits – 3 hours Classroom lecture, 1 hour Lab - Prerequisite: EEE334

Text Book: “Microelectronic Circuits,” 5th Edition, Sedra & Smith, OXFORD Press.

Class Objective: Analysis, design, and applications of digital and analog CMOS circuits
and systems. The class will use the CADENCE labs for simulations, and design of
integrated circuits. The class will cover:
– Digital CMOS circuits: Gate sizing, timing analysis, sequential digital circuits
o CMOS Logic
o Dynamic Logic
o Latch, Flip/Flop and Memory Circuits
o ROM/RAM Memory
– Analog Circuits
o Single stage and differential amplifiers
o Two stage op-amps
o Feedback Circuits
o Analog-to-digital and digital-to-analog converters (if time permits).

Lab: There is a weekly lab session. The labs will be using a CAD tool (CADENCE) for
simulations of integrated circuits. All lab work will occur in TBD under an open lab system. You
are required to attend the lab and meet the TA.

Course Topics:
1. Overview of MOSFET models for AC and DC operation.(1 Week)
2. Digital circuit design: digital gates, sizing, delay characterization, static and dynamic
operations (4 weeks)
3. Sequential digital circuits: latches, flip-flops, memory cells. (2 weeks)
4. Single Stage Amp, Biasing, Current Mirrors, Single stage Amp, Small Signal and High
Frequency Models, Cascode Amplifier (3 weeks)
5. Differential MOS Amplifiers & Biasing MOS Amplifiers, Two Stage Amplifiers, Feedback,
Compensation. (3 weeks)
6. Spice simulation of AC/TRANsient/Operating point for amps (1 week)
7. Mixed signal data converters (1.5 weeks)
8. Tests, quizzes, and examinations (1.5 weeks)

Tentative Grading:
Two Mid Terms (15% each) 30%
Final 25%
Lab 25%
HW 20%
Notes/ Policy

1- Exams and Finals: Except for a conflict with another examination (which must be
given at the time listed for it in the time schedule), or for students who have 3 or more
exams on the same day, no changes can be made to the final examination schedule
without prior approval of the Dean. I will not support such requests unless they involve
circumstances beyond a student’s control. Airline reservations and work schedules are
within the student’s control.
2- Exams: There are no make-up tests. If you miss a test, you will get a zero. If you miss
a test due to a medical reason, I will need to see a note from your doctor.
3- NO Late HW, No late lab report, no late assignments.
4- HW is due in class at the end of the Lecture.
5- DO NOT SEE the TA For correction or mistakes in HW/project/lab grading. For any
questions on graded HW/Quiz/Lab/Exam, you must submit a written request to me in
class.

Important Dates

August 24, 2008 First Day of Classes

August 24-28, 2009 Late Registration & Drop/Add Deadline - In Person
August 24-30, 2009 Late Registration & Drop/Add Deadline - Online
September 7, 2009 Labor Day Observed
November 6, 2009 Course Withdrawal Deadline - In Person
November 8, 2009 Course Withdrawal Deadline - Online
November 11, 2008 Veterans Day Observed
November 26-27, 2009 Thanksgiving Holiday Observed
December 8, 2009 Complete Withdrawal Deadline - Online & In Person
December 8, 2008 Last Day of Classes and Last Day to Process Transaction
December 9, 2008 Reading Day

December 10-16, 2009 Final Exams