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1. CMOS Inverter
AIM:
Design a CMOS Inverter with following specifications:
For PMOS Wp = 3m and Lp = 180nm.
For NMOS Wn = 1m and Ln = 180nm
Perform Transient and DC analysis on Designed inverter Schematic with given specifications.
Draw the layout of the inverter; Perform DRC, LVS and QRC on the layout. Simulate the inverter with
extracted parasitics.
Compare the results of Inverter schematic and layout.
SCHEMATIC DIAGRAM:
SYMBOL VIEW:
TEST ENVIRONMENT:
ADEL VIEW:
SIMULATION RESULTS:
Transient Analysis:
TpLH TpHL
DC Analysis:
SWITCHING THRESHOLD:
Vinv: 865.102mV
LAYOUT:
Layout Area:
8.225m x 7.16m = 58.891m2
RCX Extracted:
Transient Analysis:
TpLH TpHL
TpLH: 83.88 ps
(Measured using delay function in calculator)
TpHL: 42.54 ps
DC Analysis:
SWITCHING THRESHOLD:
Vinv: 865.322mV
SUMMARY COMPARISON:
2. CS Amplifier
AIM:
Design a CMOS CS Amplifier with following specifications:
For Active PMOS transistor Wp = 50m and Lp = 1m.
For Load NMOS transistor Wn = 10m and Ln = 1m
Perform Transient, DC and AC analysis on Designed C Amplifier Schematic with given specifications.
Draw the layout of the CS Amplifier; Perform DRC, LVS and RCX on the layout. Simulate the CS
Amplifier with extracted parasitics.
Compare the results of CS Amplifier schematic and layout.
SCHEMATIC DIAGRAM:
SYMBOL VIEW:
TEST ENVIRONMENT:
ADEL VIEW:
SIMULATION RESULTS:
Transient Analysis:
DC Analysis:
SWITCHING THRESHOLD:
Vinv: -60.8mV
AC Analysis:
You will get Phase Shift as 132.19o at cut off frequency of 1.3296 GHz.
LAYOUT:
Layout Area:
61.7m x 15.06m = 929.02m2
RCX Extracted:
Transient Analysis:
DC Analysis:
SWITCHING THRESHOLD:
Vinv: -103.8mV
AC Analysis:
SUMMARY COMPARISON:
3. CD Amplifier
AIM:
Design a CD Amplifier with following specifications:
For Active NMOS transistor Wp = 50m and Lp = 1m.
For Load NMOS transistor Wn = 10m and Ln = 1m
Perform Transient, DC and AC analysis on Designed CD Amplifier Schematic with given specifications.
Draw the layout of the CD Amplifier; Perform DRC, LVS and RCX on the layout. Simulate the CD
Amplifier with extracted parasitics.
Compare the results of CD Amplifier schematic and layout. Try to improve the gain of CD amplifier with
changing above mentioned specifications, such that gain is closer to that of a unity gain amplifier.
SCHEMATIC DIAGRAM:
SYMBOL VIEW:
TEST ENVIRONMENT:
ADEL VIEW:
SIMULATION RESULTS:
Transient Analysis:
AC Analysis:
LAYOUT:
Layout Area:
12.72m x 56.715m = 721.41m2
RCX Extracted:
av_extracted View:
Transient Analysis:
AC Analysis:
SUMMARY COMPARISON:
4. Differential Amplifier
AIM:
Design a Differential Amplifier with following specifications:
For Active NMOS transistors Wp = 3m and Lp = 1m.
For Load PMOS transistors Wn = 15m and Ln = 1m.
For Current Source NMOS transistors Wn = 4.5m and Ln = 1m.
Idc: 30A, Vdd: 2.5V Vss: -2.5V.
Perform Transient, DC and AC analysis on Designed Differential Amplifier Schematic with given
specifications.
Draw the layout of the Differential Amplifier; Perform DRC, LVS and RCX on the layout. Simulate the
Differential Amplifier with extracted parasitics.
Compare the results of Differential Amplifier schematic and layout.
SCHEMATIC DIAGRAM:
SYMBOL VIEW:
TEST ENVIRONMENT:
ADEL VIEW:
SIMULATION RESULTS:
Transient Analysis:
DC Analysis:
SWITCHING THRESHOLD:
Vinv: -68.59mV
AC Analysis:
LAYOUT:
RCX Extracted:
Transient Analysis:
DC Analysis:
SWITCHING THRESHOLD:
Vinv: -68.59mV
AC Analysis:
SUMMARY COMPARISON:
5. Operational Amplifier
AIM:
Design an Operational Amplifier with following specifications:
Differential Amplifier:
For Active NMOS transistors Wp = 3m and Lp = 1m.
For Load PMOS transistors Wn = 15m and Ln = 1m.
For Current Source NMOS transistors Wn = 4.5m and Ln = 1m.
Common Source Amplifier:
For Active PMOS transistor Wp = 50m and Lp = 1m.
For Load NMOS transistor Wn = 10m and Ln = 1m
Idc: 30A, Vdd: 2.5V Vss: -2.5V.
Perform Transient, DC and AC analysis on Designed Operational Amplifier Schematic with given
specifications.
Draw the layout of the Operational Amplifier; Perform DRC, LVS and RCX on the layout. Simulate
the Operational Amplifier with extracted parasitics.
Compare the results of Operational Amplifier schematic and layout.
SCHEMATIC DIAGRAM:
SYMBOL VIEW:
TEST ENVIRONMENT:
ADEL VIEW:
SIMULATION RESULTS:
Transient Analysis:
DC Analysis:
SWITCHING THRESHOLD:
Vinv: -44.81mV
AC Analysis:
LAYOUT:
RCX Extracted:
Transient Analysis:
DC Analysis:
SWITCHING THRESHOLD:
Vinv: -45.23mV
AC Analysis:
SUMMARY COMPARISON:
Prepared by:
Keith R Fernandes.
Asst. Professor, Dept of ECE
SJEC, Mangaluru