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NETLIST 1- Ceva Block DRCs :

1. F8 Rules EDT Finder Rules

Verifies that all channel outputs are driven by a compactor. F8 traces all channel outputs to
verify that they are driven by a compactor, and verifies that the state elements in the channel
output pipelines are properly clocked during shift.
2. F9 rules - Verifies that all compressed scan chains are connected to a decompressor. F9
traces all channel outputs to verify they connect to a decompressor.

3.K5 EDT Rules


This rule check verifies the existence of all required EDT control and channel pins at the top
level of the design. The default handling for this rule violation is error.

4.P10 Procedure Rules

The shift procedure must contain a measure_sco statement. To correct this error condition, add
a measure_sco statement at the appropriate place in the shift procedure of the test procedure
file.

P12 -The pin name argument for a force or pulse statement must be a valid pin name of a
primary input or clock signal.
5. P34 - At the end of all test procedures (except test_setup procedure), all clocks must be at
their offstate. Correct this error condition by forcing the indicated clock to its off-state prior to
the
indicated line of the test procedure file.

6. P52 -A pulse statement was used with a pin name which is not a clock pin. This message can
also appear for either timeplates or procedures.
7. W12 Timing Rules
A timeplate was loaded that is missing a required statement. For example, a timeplate must have
a force_pi statement. If a required clock pulse statement is missing from the loaded timeplate,
you will receive a P53 rule message.

8. W32

A force_pi in a named capture procedure must not occur when a clock is in an on state.
W32 ensures the procedure file is valid.

9.W7 - No timing information has been specified for the named procedure. Either the procedure
needs to reference a timeplate, or time values must be associated with the event statements.

10.P30 - A procedure may not place a clock at its on-state at the same time it forces a non-clock
pin to a value or place another clock at its off-state.
11.Coverage Transition

12.Coverage Stuck At
NETLIST 2 - CORE CHIP
Core Chip Improved Coverage

Core Chip Simulations Result

1.Chain_serial -

2.Scan_Serial
3.Scan Parallel Mismatches

DRC Violations -
1. D7 Scan cell Data Rule
At the end of the shift procedure, the clock inputs of scan flip-flops must not be set to a one
state. The application performs this check using the simulated values of the last time period of
the shift procedure. The rule violation occurs if any clock input (not including set and reset lines)
of any scan flip-flop (except COPY) is set to 1. A possible cause of a rules violation is an
incorrect definition of the off-state of a clock.

2. K17 This rule check verifies the EDT clock is constrained to its inactive state. This is
required in order to avoid disturbing the EDT IP during the capture cycle.
NETLIST 3 ANUSANDESH

1.P34 -

2.P53,P30,W18

3.T3- The shift procedure must create a sensitizable path from the scan chain output back to the
scan chain input. An improperly sensitized gate in the scan path will cause an error condition.
Correct this error condition by accessing the simulated values of all time periods of the shift
procedure. To do this, set the gate reporting to trace, and use the report_gates command for the
gate ID number displayed in the error message. This can help you to identify where the blockage
occurs; tracing back from the inputs helps you identify how to correct the problem.
4.T5
During the shift procedure, you must never place an X value on a clock input or an active (X or
1) value on a set or reset input of a memory element in the scan path. Correct this error condition
by accessing the simulated values of all time periods of the shift procedure. You do this by
setting the gate reporting to trace and using the report_gates command for the gate ID number
displayed in the error message. This can help you identify where the problem occurred; tracing
back from the indicated input helps you identify how to correct the problem.

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