Documente Academic
Documente Profesional
Documente Cultură
DATA BOOK
1986
(408) 737-0204
CONTENTS
PRODUCT LINE-UP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .1
2 PACKAGING ...................................................... 3
OKI makes no warranty for the use of its products and assumes no responsibility for
any errors which may appear in this document nor does it make a commitment to
update the. information contained herein.
OKI retains the right to make changes to these specifications at any time, without
notice.
PRODUCT D
LINE-UP
PRODUCT LINE-UP
o APPLICATION TYPE NO FUNCTION
OUTPUT
DUTY PACKAGE REMARKS
COMMON SEGMENT
COMMON
MSM5238
DRIVER
32 - 1/32 - 1/128 44 FLT.
SEGMENT
MSM5839B - 40 1/8 - 1/128 56 FLT.
DRIVER
COMMON
MSM5278
DRIVER
64 - 1/8 - 1/128 80 FLT.
SEGMENT
MSM5279 - 80 1/8 - 1/128 100 FLT.
DRIVER
DRIVER/ with character
MSM6222B CON- 16 40 1/8 - 1/16 80 FLT. generator
-01 TROLLER ROM
CON-
DOT MATRIX
MSM6240
TROLLER
- - 1/32 - 1/144 60 FLT.
LCD
CONTROLLER CON-
MSM6255
TROLLER
- - 1/2 - 1/256 80 FLT. 512K dot
512K dot
software
CON-
MSM6265
TROLLER
- - 1/100 x 2 80 FLT. compatible
with CRT
Controller
Note: 1. MSM5259 and MSM5260 can be used as static display dot dri"es like MSM5219B and so forth.
2. The duty of LCD module is determined by the perform~mce of drivers and the material of LCD panel.
So, to select suitable LCD driver for superior display, it is necessary to study the material of the LCD
panel.
2
PACKAGING
H
PACKAGING
PLASTIC FLAT
PRODUCT PACKAGE GS-K GS-L GS-L2
(No. of Pins)
MSM58292 56 (small) 0
MSM5238 44 0 0
MSM5839S 56 (small) 0 0
MSM5278 80 0
MSM5279 100 0
MSM6222S-01 80 0
Note: Model names suffixed by GS denote plastic mold flat package, while -K, -L or -L2 denote
the direction of the lead bent.
Top
6
GS-K
..... GS-L/GS-L2 .
o
Bottom
4
- - - - - - - - - - - - - - - - - - - - - - - - - 1 1 . PACKAGING
121
~\'r
'"
o
33 fI
22
=
:...
12
'"
o
~-
1.5 2.0 10.5 2.0
MSM5238GS-K I--I~---------~-_l (Unit: mm)
12.1
42
o
I\,) in
" (J'1
I\,)
1.025 8.45
MSM58292GS-K 1.5 Index mark 2.0 10.5
MSM5839BGS-K
MSM5259GS-K
5
.PACKAGING.-----------------------------------------------
~II
Index mark
16
MSM5219BGS-K
MSM6240GS-K
2.10
64 45
MSM5221GS-K
MSM5278GS-K
MSM6255GS-K
MSM6265GS-K 0 ' 10
6
- - - - - - - - - - - - - - - - - - - - - - - -.... PACKAGING
fJ
0.15
MSM5265GSK
MSM5260GSK
MSM5279GSK
7
PACKAGING ----------------------------------------------
(Unit: mm)
12.1
23
....
It)
ci
0
N
22
;: ==*0
co
<Xi
Ln
en
ci
12
Ln
ci
0
N
11
Index mark
8.0 1.25
MSM5238GS-L2
(Unit: mm)
12.1
Index mark
MSM5839BGS-L2
MSM5259GS-L2
8
-------------------------------------------------PACKAGING-
(Unit: mm)
MSM6222B-01 GS-L
MSM5260GS-L
9
10
DATA SHEET
12
STATIC
LCD
DRIVER
OKI semiconductor
MSM58292GS
5-DIGIT STATIC LCD DRIVER
GENERAL DESCRIPTION
11 The OKI MSM58292GS is a 7-segment static LCD driver LSI which is fabricated by low power CMOS metal gate
technology. This LSI consists of 32-bit shift register, 32-bit latch, 5 sets of 7-segment decoder and LCD drivers.
It receives the serial display data from the microcomputer etc, converts it to a parallel data, then output to the
7-segment LCD panel.
The input code for each digit is a 4-bot binary code. The input codes are decoded into digits 0 ~ 9 and alphabetic
letters A - F, to display hexadecimal numbers. The expansion of display can be easily made by using another
MSM58292GS in cascade connection.
The MSM58292GS can directly drive the LCD panel, as the AC driving circuit is integrated on the chip.
FEATURES
5 digit 7-segment LCD display Supply voltage: 3 -7V
Serial input from the microcomputer etc. 56 pin plastic flat package
Expansion of display by cascade connection
PIN CONFIGURATION
n
o
;!:
VSS a1
OSC
SERIAL OUT
0 92
f2
SERIAL IN e2
CLOCK dl
LOAD DP.1
VDD C.I
BI/RBO VDD
a.1
f.l
9.1
e.1
d.l
14
OJ
r
o(")
"
o
(MSD) (LSD)
i>
C)
~
OSC SC a, b, c, d,e,',Q, F, F2 COM COM :0
JOOOOO(
s:
~-
OUTP
DISABLE
BLANKO~--------------~
en
~
::!
("')
In
~
- STATIC LCD DRIVER MSM58292GS - - - - - - - - - - - - - - - - -
11 OPERATING RANGE
DC CHARACTERISTICS
(Voo = 5V 5%, Ta ~ -30 - +85C)
l -0.2/
Output current 10H/IOL VO=OVIVO=VOO
0.2
- - mA
2 -0.2/
Output current 10H/IOL Vo = 2.5V1V0 = O.4V - - mA
1.6
-10/ -500/
BI/R-t30 short-circuit current 10H/IOL VO=OVIVO=VOO - I1A
10 500
Dynamic current consumption 100 f (OSC) = 360Hz no load - - 500 I1A
Note 1: Applied to the output pins excluding the SERIAL OUT, BI/RBO, COM and COM Pins.
Note 2: Applied to the SERIAL OUT pin.
Note 3: Applied to the COM pin.
Note 4: Applied to the COM pin.
Note 5: Applied to the input pins excluding the OSC pin.
16
- - - - - - - - - - - - - - - - STATIC LCD DRIVER MSM58292GS-
SWITCHING CHARACTERISTICS
(VDD = 5V. Ta = 25C. CL = 15pF)
tTHL
SERIAL OUT rise/fall time - - - 300 nS
tTLH
Maximum clock frequency ilCK) max - 1 - - MHz
Minimum clock pulse width tw(CK) - - - 500 nS
Minimum load pulse width twILl - - - 500 nS
1
Data setup time SERIAL IN ~CLOCK tsetup - - - 250 nS
2
Data setup time SERI AL OUT ~ LOAD tsetup - - - 500 nS
CLOCK
50% 50% 50%
- - "'""""\ r- -
SERIAL IN 50% _ _ _ _ _ _ ...J 50%
'-
90%
SERIAL OUT
- - - - ; - H - - t se tup2
LOAD 50%
17
STATIC LCD DRIVER MSM58292GS - - - - - - - - - - - - - -
FUNCTION TABLE
F * H H L L L H H H C
I
Note 1: The H indicates that the segment is displayed. and the L indicates that the segment is not displayed. The H
is an antiphase output of the COM output. and the L is an inphase output of the COM output.
Note 2: The RI/RBO pin goes to low level only when the RBI pin is at a low level and all the digit are 0 (the display
is blank).
If the BI/RBO pin is forcibly turned to high level. 0 at LSD is displayed.
Note 3: If the BI/RBO pin is forcibly turned to low level. the LSD is made blank.
Note 4: If the RBI pin is turned to low level, the display is placed in the leading zero blanking status, in which the
contiguous Os preceding the MSD are made blank.
18
- - - - - - - - - - - - - -...... STATIC LCD DRIVER MSM58292GS.
FUNCTIONAL DESCRIPTION
SERIAL IN
The SERIAL IN pin is a shift register data input in the order of blank data, flag data, decimal point
pin. The display data are input to this pin synchro- data, then numeric data (beginning with the LSB)
nized with the clock pulses. The data are input (positive logic).
< Data input procedure>
OSERIAL
OUT
CLOCK BIJRBO
The CLOCK pin is a synchronizing pulse input The BI/RBO pin is used for both input and output.
pin used for data input to the shift register or data As an input pin, the input level can forcibly be
output from the shift register. The data is shifted set to low regardless of the output level, since the
at the rising edge (low to high) of each clock pulse. output resistance is treat.
A Schmitt trigger circuit is employed as the CLOCK
input circuit (the hysteresis is approximately 0.5V). For use as an output pin RBO
When the RBI pin is turned to low level, if all
the digits are Os, the display is made blank
LOAD and the RBO pin is turned to low level. If the
The LOAD pin is an input pin for latching the shift RBI pin is at high level or a number including
register contents. When this pin is at high level, some significant digits is displayed, the RBO
the shift register contents' are transferred to the pin is turned to high level. If two MSM58292GS
decoders, and ,:",hen this pin is at ,low level, the chips are connected for extension of the digit
last data to be transferred from the shift register display capacity, the RBO pin of the first chip is
when this pin was at high level is held, so that the connected to the RBI pin of the second ch ip,
display contents are not changed with the change which connects to the MSD of the second chip,
of the shift register contents. so that all the continguous Os preceding the MSD
are made blank.
19
STATIC LCD DRIVER MSM58292GS ....- - - - - - - - - - - - - - - - . . , . -
2 For use as an input pin Bi decimal points (DPI-DPsl. and flags (FI and F z )
The Bi pin is connected to the decoder circuit on the display device.
for the LSD. Therefore, if this pin is turned The seven segment outputs (a - g) for each digit
to low level, only the LSD digit is made blank. are used to display a digit 0-9 or an alphabetic
Since this pin is also used as an output pin letter A-F.
ROB, some current indicated in the rating flows
when this pin is set to low level. level.
The Bi pin may be open when not used. e OSC
Note: The DPI through DP s are not made blank. The OSC pin is an input pin for a signal generator
circuit which outputs AC signals required for driving
VDD
R
OSC
C.L
T LSI I>--
20
- - - - - - - - - - - - - - - . STATIC LCD DRIVER MSM58292GS.
Output pins
21
STATIC LCD DRIVER MSM58292GS ....- - - - - - - - - - - - - -
Application circuit
I. 10 digit display (using two MSM58292GSs. cascade connection)
(32 - 64 Hz)
COM
LCD
Segment
outPr-u_t_---.:l'--_ _-I
"""' Segment
output
series
+5V
VDD
LCD
DO
OLMS-40
series VDD COM
22
- - - - - - - - - - - - - - - t l . STATIC LCD DRIVER MSM58292GS
8 4 2 , 8 4 2 , 8 4 2 , 8 4 2 , 8 4 2 ,
LOAD
'[2[3[4 5[6[71819[1O['~'2 '1'~ki'~'1'~'912o 21222124[2 261271281291301313~
j 1
SERIA 0 -
'~141'51'61'7 ~81l9120 2,12 2312412512~21~~2~3~3J32
SERIAL
IN
,12131415161718191101,,1,2 OOUl
CLOC~
Input
data
- ~~:~:~:~:O 0 1 0 110.Vla 0 0
I I I I I: 0O.
I / / : 1 " 8 lank datd
I Decimal MHz FM,I
POlllt
SERIALIN~ ____________ SL
I Dat.} setup lime is 250 Il~ or more
,M" "
CLOCK~ ______ _ _______ JL
500
t
os 01 more
LOAD
--------------------~7__ 500 ns 01 1l10re
- - - Shifting direction
23
f!
I\)
.eo m
><
CJ en
3 -I
"'0
-I
(1)
0
...... n
DP s DP 4 DP., DP 1 DP) r-
5" n
r
COM d4 e4 g4 f4 as bs Cs d4 e4 g4 f4 a4 b4 C4 d~ e~ 9.1 1.1 a.l b.1 c, d1 e1 g, I, a, b,C2 d)e)9)I)a)b)cl F)hCOM d e q 1 a b c DP
1 II II II II II 1111111111111,11111 1 II II II II 1 1 II II II II II II 1 1 II II II II Irlr lrlrn lr II 1 .... 0
..,en
WIll!
(") 0
0 :JJ
::l
::l
en <:m
~8 ....
(")
p8i7 P
I~ '~il 0 0
0 0 ..J
> ..J u
u
(/)
0>
(/)
(/)
OKI semiconductor
MSM5219BGS
48DOT STATIC LCD DRIVER
GENERAL DESCRIPTION
The OK I MSM5219BGS is a 48 dot static LCD driver which is fabricated by low power CMOS metal gate technology.
This LSI consists of 48bit shift register, 48bit latch and 48bit LCD driver. The display data, which was input to the
48bit shift register, is shifted to the 48bit latch by the LOAD signal. Then the data is output to the LCD panel
through the 48bit LCD driver.
FEATURES
48 dots static LCD driving capability LCD driving AC frequency is directly input exter-
Simple interface with microcomputer chip (con- nally
trolled by three input signals) Applicable as an output expanrler
Bit-tobit correspondence between the input and Supply voltage: 3 -7V
the output 60 pin plastic flat package (bent lead)
Cascade connection capability
PIN CONFIGURATION
(Top View) 80 Lead Plastic Flat Package
C/J en en C/J en en en en en Vl en Vl Vl Vl Vl
m m m m m m m m m m m m m m m
~ ~ *~ 3 ~ ~ ~
o ~ ~ ~ ~ ~
LOAD SEG32
SEG31
DATAIN SEG30
SEG29
SEG28
GND SEG27
VDD SEG26
SEG25
SEG24
ALL ON SEG23
BLANK SEG22
COM SEG21
SEGl SEG20
SEG2 SEG19
25
STATIC LCD DRIVER MSM5219BGS .
---------------
BLOCK DIAGRAM
LCD driving output
~~----------~'~------~----~"
BLANK
ALLON
F
I
SEG 1
LOAD ~~-------4-8-.-b-it-D-a?ta~La-t-c-h----------~
DATA IN 48bit Shift Register DATA OUT 48
COM
OPERATING RANGE
26
----------------11. STATIC LCD DRIVER MSM5219BGS-
DC CHARACTERISTICS
(Voo - VSS = SV. Ta = -40 -+8SoC)
*3 5 - -
Clock pulse width tw J1.S
*4 O.S - -
*3 0.1 - -
Max. clock pulse frequency fMAX MHz
*4 1 - -
Input signal rising/falling time t r. tf *5 - - 5 J1.S
Static current consumption 1001 - - - 100 Jl.A
No load when
Active current consumption 1002 ROSC = 150 kn. - - 2 rnA
COSC = 0.015 Jl.F
COM Frequency
(Self oscillation) fCOM No load when VOO = 5V 25 - 300 Hz
*1: Applicable to all terminals except OSC. This condition is applied to OSC in the external oscillation mode.
*2: Applicable to DATA OUT 32. DATA OUT 48.
*3: Applicable to OSC.
*4: Applicable to CLOCK.
*S: Applicable to all terminals except OSC terminal.
27
STATIC LCD DRIVER MSM5219BGS ....- - - - - - - - - - - - - -
FUNCTIONAL DESCRIPTION
Operational Description to the 48-bit latch by the LOAD signal and it is
The display data is input to the shift register by the output to the LCD panel through 48-bit LCD
DATA IN signal and CLOCK signal. It is transferred driver.
DATA IN
CLOCK
LOAD
o CLOCK 2 BLANK
The clock, which is used to generate the COM When this pin is set at high level, all segments display
signal and the LCD driving signal, is input to this turn off. The ALL SEG ON pin has the priority
pin. over this pin.
28
- - - - - - - - - - - - - - - t I . STATIC LCD DRIVER MSM5219BGS.
APPLICATION CIRCUIT
Single MSM5219BGS
>
- ---- --------- 1 >
<>
-"'. BLANK
SEG1 SEGN SEG48
" ALL ON
" LOAD COM -
"DATA IN MSM5219B
_,CLOCK,
CLOCK 2
I
*1: When this IC is used under a strong external noise or large-capacity LCD load, this resistor prevents latch-up to
be caused by a low output impedance of the COM pin.
The resistance is about lOOn.
Cascade connection
LCD (Static)
~
BLANK SEG1
t ~ 48 -
t
SEGl - 48
*1
*2
.---
.----
t
I
SEG1 - 48
*1
*2
ALL ON
LOAD Master r:o" 0
,---
- Siove
COM
- Sldve
COMU
l
DATA IN DATA (lIlT LID
CLOCKI CLOCK, CLOCK2
CLOT'
1 1 --
*1: The COM pin of the slave MSM5219BGS can be WI RED OR.
*2: When this IC is used under a strong external noise or large-capacity LCD load, this resistor prevents latch-up to
be caused by a low output impedance of the COM pin.
The resistance is about lOOn.
29
STATIC LCD DRIVER MSM5219BGS .....- - - - - - - - - - - - - -
Output Expander
As explained above, this I C can drive the static used as an output pin expander for a microcomputer
LCD with the COM pin. In addition, it can also be with the following connections:
r--------,
I I
r--------l r--- --- --..,
I I
: LED driv.!r
L ______ J
I :
IL _______
F L T driver
...J
I
: lL Relay driver
_______
:
oJ
l L
\,
,---
~~---IBLANK SEG1 - 48 - r-----
. ~ t--1rl>---i A L LON r---- -
f t--1H-.......-ILOAD r--
I-t-+-+--i
- :-- ---
~ 8 ~H--+---iDA TAl N OU T 48
______ t--1H--+-~~.C_L_O_C_K~I_~C~L~O~C~K.,~
+*1 + *1 +*1
*1: In this example, "H" is output by the positive logic, that is, when "H" is written from DATA IN, "H" is output
with a LOAD signal. If the OSC pin is connected to VDD, the output has the negative logic, that 1s, the logic
level input from the DATA I N pin is inverted and output.
30
OKI semiconductor
MSM5221GS
56-DOT STATIC LCD DRIVER
GENERAL DESCRIPTION
The OKI MSM5221GS is a 56 dot static LCD driver which is fabricated by low power CMOS metal gate technology.
This LSI consists of 56-bit shift register, 56-bit latch and 56-bit LCD driver. The display data, which was input to the
56-bit shift register by the DATA IN signal and CLOCK signal, is transferred to the 56-bit latch by the LOAD signal
and the data is output to the LCD through the 56-bit LCD driver.
FEATURES
56 dots static LCD driving capability Fully controlled by the software
Simple interface with microcomputer chip (control- LCD driving AC frequency is directly input exter-
led by three input signals) nally
Bit-to-bit correspondence between the input and Applicable as an output expander
output Supply voltage: 3 -7V
Cascade connection capability 80 pin plastic package (bent lead)
PIN CONFIGURATION
(Top View) 80 Lead Plastic Flat Package
(f) (f) (f) (f) (f) (f) (f) (f) (f) (f)
'"m m'" '"m
(f) (f) (f) (f)
m m m m m m m m m m m m m m '"
m
~ ~ ~ ~ ~ ~ ~ ~ z
()
z
()
z ()
n
z ()
z z
.() ~ t ~ ~ ~ ~
0 ~ 8 (Xl
SEG56 25 SEG37
LOAD
CLOCK SEG36
SEG35
.DATA IN SEG34
NC SEG33
DATA OUT 56 SEG32
COM IN SEG31
vDD SEG30
NC SEG29
VSS SEG28
ALL SEG ON SEG27
BLANK
SEG26
COM OUT SEG25
SEG 1 SEG24
SEG 2
SEG 3 0 SEG23
SEG22
(f)
m
(f)
m
en
m
(f)
m
(f)
m
(f)
m
(f)
m
(f)
m
(f)
m z z z z Z 2 (f)
m
(f)
m
(f)
m
(f)
m
(f)
m
(f)
m
(f)
m
(f)
m
(f)
m
() () () () () n
~ ~ g) 8 ~ f2 Cl ~ ~ ~ ~ ~ ~ ~
'"' ~
Cl
~ 8
0 tV W .... (Xl
'" C'>
(]1
31
STATIC LCD DRIVER MSM5221GS ...- - - - - - - - - - - - - -
BLOCK DIAGRAM
ALLS:::: i
I
CLOCK
VDD
VSS
t--
t::.-
OPERATING RANGE
32
- - - - - - - - - - - - - - - . STATIC LCD DRIVER MSM5221GS.
DC CHARACTERISTICS
(VDD-VSS=sv. T a =-40-+8SoCI
-400/
SEG Output current 2 IOHS2/ I OLS2 VOH = lV/VOL = 4V
400
- - J.lA
-SOO/
COM Output current 1 IOHC1/ I OLCl VOH = 4.SVIVOL = O.SV - - J.lA
SOO
COM 04tput current 2 IOHC2/ I OLC2 VOH = lVIVOL = 4V -2/2 - - mA
"H" Output voltage* 1 VOH 10 = -O.lmA 4.S - - V
"L" Output voltage* 1 VOL 10 = O.lmA - - O.S V
Clock pulse width * 2 tWcjJ - O.S - - J1S
Maximum clock pulse
frequency * 2 fcjJMAX - 1 - - MHz
33
STATIC LCD DRIVER MSM5221GS ....- - - - - - - - - - - - - - -
FUNCTIONAL DESCRIPTION
Operation Description
The display data is input to the shift register by the to the 56-bit latch by the LOAD signal and it is
DATA I N signal and CLOCK signal. It is transferred output to the LCD panel through 56-bit LCD driver.
CLOCK
LOAD
DATA LATCH output
(inside LSI)
COMIN BLANK
Input pin to generate the COM OUT signal. The When this pin is set at high level, all segments display
same phase signal as the COM IN pin is output turn off. The ALL SEG ON pin has the priority
from the COM OUT pin. over this pin.
34
- - - - - - - - - - - - - -..... STATIC LCD DRIVER MSM5221GS.
APPLICATION CIRCUIT
Single MSM5221GS to the LCD panel
t-
LCD panel (static)
>
- -- -- - - - --- ---- <-~
DATA IN
CLOCK
COM IN
COM IN --------------------------------~
Cascade connection
MSM5221GS
--
> MSM5221GS MSM5221GS
56 R, ~ 56 ~
RI > ,
56 R,
>
?
~
BLANK r-- ;--
-r- SEGI - 56
~r----- SEGl - 56
SEGI - 56
- -
ALL SEG ON
LOAD
DATA IN
-
- r-
~
~
COM OUTr----
0.0.56
COM OUT
0.0.56
-
r--- COM OUT 1--'
COMIN t t t ----
--
- ---
--
-
35
OKI semiconductor
MSM5265GS
l60-DOT LCD DRIVER
GENERAL DESCRIPTION
The OKI MSM5265GS is an LCD driver which can directly drive up to 80 segments in the static display mode, while
it can directly drive up to 160 segments in the 1/2 duty dynamic display mode.
The MSM5265GS is fabricated by low power CMOS metal gate technology, consisting of 160stage shift register,
160-bit latch, 80 sets of LCD driver and a common signal generator.
The display data is serially input from the DATA-IN terminal to the 160-stage shift register synchronized with the
CLOCK pulse. The data is shifted to the 160-bit latch by the LOAD signal. Then the latched data is directly output
to the LCD from the 80 sets of LCD driver as serial output.
The common signal can be generated by the on-chip generator, or can be externally input. The common synchroniza-
tion circuit which is used in the dynamic display mode is integrated on the chip.
FEATURES
80 segments display drive (in the static display mode) Can be synchronized with the external common
160 segments display drive (in the dynamic display signal
mode) Testing terminals for all-on (SEG-TEST) and all-off
Simple interface with microcomputer (BLANK)
Bit-to-bit correspondence between input data and Applicable as an output expander
output data LCD driving voltage can be adjusted by the com-
H : Display L : No display bination of VLCl and VLC2
Cascade connection capability Supply voltage: 3.0'" 6.0V
On-chip common signal generator 100 pin plastic flat package (bent lead)
PIN CONFIGURATION
(Top View)
36
- - - - - - - - - - - - - - - - 1 1 . STATIC LCD DRIVER MSM5265GS.
BLOCK DIAGRAM
To LCD panel
VDD
GND
LOAD
DATA-IN DATA-OUT2
34
DATA-OUT1
DIS
O"SC-ODT
OSC-OUT
48
OSC-IN COM-A
Oriver
49
EXTIINT COM-B
46
SYNC COM-OUT
37
STATIC LCD DRIVER MSM5265GS 11-.- - - - - - - - - - - - - -
OPERATING RANGE
Oscillator
capacitance
Co [ll] OSC-OUT Film capacitor 0.001 - 0.047 J.lF
Current limiter
resistance
RI 00 OSC-IN RI ~ 10 Ro 0.56 1 2.2 Mn
38
- - - - - - - - - - - - - - - . STATIC LCD DRIVER MSM5265GS.
[m OSC-OUT
~ OSC-OUT 10 = -200p.A 4.S - - V
"L" Output
~ DATA-OUTl
em OSC-OUT
10 = 200p,A - - O.S V
@ill OSC-OUT
Output Vo = SV - - S p,A
leakage ILO ffi] SYNC
when internal Tr is off
current
39
STATIC LCD DRIVER MSM5265GS - - - - - - - - - - - - - - -
11 SWITCHING CHARACTERISTICS
0
(VDD=3.0-6.0V Ta =-40-+85 C)
33 DATAI~,I
32 C'_OCK
31 LOAD
34 DA T A-OUT 1
35 DATA-OUT2
45 SYNC
40
- - - - - - - - - - - - - - - . STATIC LCD DRIVER MSM5265GS.
DATA-IN
CLOCK
LOAD -------------~H\r-_------In'---
r----
DATA L A T C f . i I I - - - - - - - - - - - - - - - - - - - f ( ( I f - - - - - - - - ,
fi~~?~~
the IC) X..____ )}
fOSC
41
STATIC LCD DRIVER MSM5265GS - - - - - - - - - - - - - - -
DIS DATA-OUT!
When this pin is set at high level, the MSM5265GS The 80th stage of the shift register contents is
operates in the dynamic display mode, while it output from this pin.
operates in the static display mode when this pin When more than two MSM5265GSs are connected
is set at low level. in a series (cascade connection) in the static display
mode, this pin should be connected to the next
EXT/INT MSM5265GS's DATA-IN terminal.
When the external common signal is used, this pin
should be set at high level and the external common
signal is to be input from the OSC-I N terminal. DATA-OUT2
42
- - - - - - - - - - - - - - - . STATIC LCD DRIVER MSM5265GS.
COM-A, COM-B
LCD driving common signal is output from these In the select mode the, same phase level as the
pins and these pins should be connected to the COM-OUT signal is output.
common side of the LCD panel. In this case, VOO or VLC2 is output at high
level or low level respectively_ In the non-select
In the static display mode
mode, VLCl is output at the middle level.
Same phase pulse as COM-OUT terminal is
In the select mode of COM-A (non-select mode
output from both of COM-A and COM-B. In
of COM-B), the 1st ,..., 80th latched data contents
this case high level is VOO level and low level
are output from the 80 sets of LCD driver to
is VLC2 level.
the LCD panel.
In the dynamic display mode In the select mode of COM-B (non-select mode
The COM-A and COM-B output signal are of COM-A), the 81st '" 160th latched data
alternately changed within each COM-OUT contents are output from the 80 sets of LCD
output cycle, resulting in alternately repetition driver to the LCD panel.
of select and non-select modes.
COM-OUT
- JlJlJl
---Jl-Jl-J
VOO
COM-A - VLCL
- - VLC2
rL rL n ~ _~::1 - n n n
uu
COM-B .
U=---VLC2~ U U I
43
i
/
STATIC LCD DRIVER MSM5265GS . - - - - - - - - - - - - - - -
IJ
mode. signal as the common signal is output, while
The inversed phase signal as the COMOUT the same phase signal as the common signal is
signal is output to the LCD, when the display output when the display turns off.
turns on, while the same phase signal is output
when the display turns off.
COMA COMA
COMB COMB
, I I
3UU1SI
SEG N
:J-+l1J-fL
Off On I Off On
SEG N
Off
~ On
fn 10n On
ISO+N N N
SEGTEST BLANK
This pin is used to test the segment output (SEG 1 '" This pin is also used to test the segment output
SEGSO)' All display turn on when this pin is set at (SEG1 '" SEGSO). All display turn off when this
high level, while the display becomes the same pin is set at high level, while the display becomes the
condition before this pin was set at high level, when same condition before this pin was set at high level,
this pin is set at low level. This pin has the priority when this pin is set at low level.
over BLANK terminal. When SEGTEST pin is set at high level, the input
on this pin is invalid.
44
- - - - - - - - - - - - - - - - - . - STATIC LCD DRIVER MSM5265GS-
APPLICATION CIRCUIT
LCD panel
COM ~
80 segments (static)
- - - - - - - - - RCOM
.
SEG 1 - -- - - - - - - - SEG 80
SEG-TEST
. BLANK COM-A f--
1
DATA-IN
CLOCK
SYNC
r--
DIS EXT/INT OSC-IN OSC-OUT OSC-OUT VLC 2
77" 7~
>RI
1Mn
lco .. Ro
100kn. TJ'r
To01/1F
COM-B I---
LCD panel
80 x 2 segments (dynamic)
COM-A I - - V DD
~7
>
- - - - - - - - - RCOM
x2 ')
>
>
- - - - - - - - - SEG 80
~
. SEG-TEST
SEG 1
VLC1
COM-A 1 -
BLANK
~
From
controller
LOAD MSM5265GS COM-B I---
DATA-IN VLC2
1
).
)-
22k
Voo T RI
1Mn
lco
TO.01/1F
Ro
100kn
45
~
.j:>o
en ~
en
Q ~
~
Cl
Q.
~
CD
n C")
0
::I
::I r-
CD C")
~
0' C
::I
C
2- :0
LCD panel (80 x n segments) static
3:
en
3:
U1
<
m
N :0
COM en
U1
G')
~
s:
en
r
VLC2
VLC2
80
RCOM
80
RCOM
80
RCOM
---- ..:j'
=r
CD
~
~
s:U1
N
m
U1
n' G)
Q. en
SEG-TEST COM-A COM-A
~'
iii'
VLC2 <
BLANK MSM5265GS VLC2 MSM5265GS
3
0
COM-OUT Q.
LOAD !II
DATA-IN DATA-OUT 1 DATA-IN DATA-OUT 1
:e
~
~
AI
C.
GI
n
0
:::I
:::I
GI
g.
(
0
:::I
.> RCO~
'1'80 RCOM
RCOM:> ~ RCOM RCOM } C.
VLC2 : c
<:::I
AI
3
SEG-TEST COM-A f- ..--- COM-A I - .--- COM-A I- 0"
c.
BLANK MSM5265GS CO~I-B I--- roo- MSM5265GS
COM-B I - - .---- MSM5265GS COM-B
~ ~"
Qj
LOAD COM-OUT '"-- r-- r-- <
3 en
DATA-IN DATA-OUT 2 DATA-IN DATA-OUT 2 DATA-IN DATA-OUT 2 :..-- -- 0
c. -i
!D
CLOCK SYNC I- r- SYNC ~ ..-- SYNC l -
:::!
OIS EXT/INT ~ DIS EXTIINT OSC-IN DIS EXTIINT OSC-IN (")
tJ lW~~c
22kn
rol I fool 1
-- --
r-
(")
C
C
:0
<:
m
- - :0
- -
- -
-- s:en
~
(.TI
N
en
(.TI
C)
:. en
....
~
STATIC LCD DRIVER MSM5265GS . - - - - - - - - - - - - - - -
5) Output-expander
SEG 1 - - - - - - - - - - SEG 80
SEG-TEST
BLANK
From
LOAD MSM5265GS
controller
DATA-IN
--11----1 CLOCK
*The output logic can be reversed in respect to the input data by setting OSC-I N to "H" level.
48
DOT
MATRIX
LCD
DRIVER
OKI semiconductor
MSM5238GS
DOT MATRIX LCD 32 DOT COMMON DRIVER
GENERAL DESCRIPTION
The OKI MSM5238GS is a dot matrix LCD's common driver LSI which is fabricated by low power CMOS metal gate
technology. The scanning signal in one matrix display frame can be divided into up to 1/32 duty. This LSI consists
of 32-bit shift register, 32-bit level shifter and 32-bit 4-level driver.
This LSI can drive a variety of LCD panel because the bias voltage, which determines the LCD driving voltage, can be
optionally supplied from external source.
FEATURES
PIN CONFIGURATION
(Top View)
1
O2
03
0 0.12
0.11
0.10
04 0 29
0 28
o~
0 6 027
0 7 026
0 25
as
0 9 0 24
023
0 22
all
0 0
..
0 0
'" 0
0 0 0
.,
0
c:-
5 0
o
o
~
*Pin 17 is an auxiliary pin. It shall be connected to the power supply or disconnected to any other terminal.
50
------------_i_ DOT MATRIX LCD DRIVER MSM5238GS-
BLOCK DIAGRAM
01
...-------0-- - - - - - - - - - - - - - - - - - - -0----....,
Voo
VI o---t---i
V 1 o----I-~ 32bit 4 Level OriVer
V 1 o---t----i
Voo
VEE(V 4 )cr~----Lr_------__::::;:::oo-==:__------..J
OFo-_ _ _...J
VSS
01
32bit Shift Register
CP
OPERATING RANGE
51
DOT MATRIX LCD DRIVER MSM5238GS - - - - - - - - - - - - -
Condition Limits
Item Symbol Unit
VOO VSS VEE
MIN TYP MAX
(V) (V) (V)
"H" *1 0- 3.6/
5 0
-9
-
4.2
- -
input VIH 1/
V
voltage VIH 2 0- 5.2/
7 0 - - -
-7 6.0
"L" *1 0- 0.8/
5 0
-9
- - - 0.4
input VILli V
voltage VIL2 0- 1.1/
7 0 -
-7 0.5
Input IIH 7 0 -7 VI = 7V - - 1
IlA
voltage IlL 7 0 -7 VI = OV - - -1
0-
"H" 5 0
-9
100 = -401lA 4.2 - -
*2
output V
voltage VOH 0-
7 0 10D = -561lA 5.8 - -
-7
0-
"L"
*2
5 0
-9
100 = 0.2mA - - 0.4
output V
VOL 0-
voltage 7 0 100 = 0.3mA - - 0.4
-7
0 0 Vo: ORV output - 500 2000
5 Vo - Vi = 0.25V
0 -5 - 250 1000
RON Vi = VEE - (VOO - 0.25V) n
(Vi. V4) 0 0 Vo - V 4 = 0.25V - 350 1400
7
ON 0 -7 V4(VEE): MAX OV - 200 800
Resistance
0 0
VN =V2 or V3
- 800 3200
5
RON 0 -5 V = ORV output - 450 1800
n
(V2. V3) Vo - VN = 0.25V
0 0 - 550 2200
7 VN = VEE'" (VOO - 0.25V)
0 -7 - 350 1400
OFF Lead 5 0 -9 - - - 5
current IOFF IlA
7 0 -7 - - - 5
Power supply 5 0 -9 - - - 0.5
mA
current 100
7 0 -7 - - - 1.0
Input
capacitance CI - - 5 - pF
* 1 VIHl and VI Ll are input pins for 01 and OF. while VI H2 and VI L2 are input pins for CPo
*2 VOH and VOL are output pins for Do.
52
- - - - - - - - - - - -.....- DOT MATRIX LCD DRIVER MSM5238GS-
SWITCHING CHARACTERISTICS
VDD
Item Symbol Condition MIN TYP MAX Unit
(V)
5 - 400 - -
Maximum clock frequency t (cp) KHz
7 - 550 - -
5 - 400 - -
Clock pulse width tw (cp) ns
7 - 300 - -
5 - 100 - -
Data setup time (DATAIN ~CP) tsetup ns
7 - 50 - -
5 - 800 - -
Data hold time (DATAIN ~CP) thold ns
7 - 500 - -
tr (cp) 5 - - - 0.5
Clock pulse Rising/Falling time ms
tr (cp) 7 - - - 0.1
tf (cp)
CP 50% 50%
10%
tw (cp)
53
- DOT MATRIX LCD DRIVER MSM5238GS - . . . - - - - - - - - - - - - -
VOO = 5V
VOO
VI C
V2
C
MSM5238GS C VLCO
VSS VSS
Fig. 1
-7 - -9V -7 - -9V
1/32 duty C = 0.1 pF or less 1/32 duty C = 0.1 pF or less
1/7 bias R = 0.5 KQ-6 1/7 bias R = 0.5 kQ- 5kQ
VR = 5kQ-10kQ
*Ttie value of R should be decided according to the power consumption and LCO panel size.
V 1,V 2,V3,V4 00
Bias supply voltage pin to drive the LCO. Bias Shift register contents output pin. The data which
voltage divided by the registance is usually used was input from 01 is output from 00 with 32 bits'
as supply voltage source. delay. synchronized with the clock pulse. By
Fig. 1 shows the case when the bias voltage, which connecting 00 with next MSM5238GS's 01. this
determines the LCO driving voltage. is supplied LSI is applicable to the LCO. the duty of which
from the external source. is 1/64. Refer to the Fig. 2 below.
X32
> 64 x n
\
LCO panel
Frame
X32
I V
signal"'-- Ol
0 1 0 32
00 - 01
0 1 0 3200
R R 5R R R VR
, ... ,
Fig.2
To SEGMENT Orivers
54
- - - - - - - - - - - -..... DOT MATRIX LCD DRIVER MSM5238GS.
TIME CHART
1/32 duty. 1/7 bias
01 ---Fl--------------- ~
(Frame signal) 32 : 1 ! 2 3 ----------- 32 1 2 3
CP
..JLJLJL..JL.JL-----------~
SR 0, ~------------~
a,
~__________ \1____
(InsIde the
circuIt)
VOO
Va
Vb --t--t---+---t--+-+--1r-- - - - - - -I-+---+---+--+-+-+-t-
0, -+-+--+--+-+-+--If-- - - - - - ---+--+--t--I--t-+--+--t-
Vc -+-+--+---+--+-+-t- - - - - - __I-t--+---+--+-+-+-t-
Vd _"--.......,....+-_-4..__1..---1.-""_ _ _ _ _ _ _"---'--.,....+-_-4..---I.---I.-""---l.....
Ve --_....1--"'------- - - - - - .---.......1---------
1 frame
VOD ------------,.......,------
Va - ......,..--.-..,..---+---'--r--r- - - - - - - -.....,..__ .........-__....--
....,.--,~-t--
Vb -+-+-+-+--+--+--1- - - - - - ---t--1-+--+---+---+--+-t-
0,
-+--+--+--+---+--t-I--- - - - - ----t-1-+--+---+---+--+-t-
Vc -+-+-+-I---+--t-I-- - - - - - --t--t-+-+---+---+-t--l-
Vd _ooI__-L-...............,..-+_--I_'__ - ---- -- - ...............---..........,...-t---.............--
Ve
0 . ,
Vc
Vd
Ve L L
VOO VOO
.-J R~
--
-01
V,
CP
OF
V, fo-
. Va
Vd VOO- l'7VLCO
--
~
0,
0,
CI)
t:)
~ 3R
R.
Vb
Vb VOO 2i7VLCD
Vc -VOO 517VLCO
I ~
CI)
Vc
Vd" VOO-6I7VLCO
:
V. ~ ~c-'"
~
VR
-5 --7V
55
DOT MATRIX LCD DRIVER MSM5238GS - .- - - -
Common
Voo I 1 I 2 I 3 I 4 1------- I 32 I 1 I
th IVoo----r........-----
I I I I I
-
0, ~
0, r: 11111I11 II III
VLCO _ _ _ __
Va "VOO--l17VLCO
Vb" VOO- -2I7VLCO
1I7V~:~ I
J II II I
Vc" VOO -517VLCO
Vd ~ VOO-.6I7VLCO 517VLCO ~==================
VLCO _ _ _ __
56
-i
-<
~
n
r-
LCD panel 32 X 200
J
WU HHlIHtI ~IIII !ttl! iUti \ ~
~
" fHtFfITtfl r-
ri DD
V, VSS V2
DF
V.l VEEIV4) r--
.-- CP MSM5839B
LOAD GS
0 40
D0 40
OC 20
DI21
DI,
CP
LOAD
0
'
MSM5839B
GS DI21
DI,
0,
::c
C")
c
=i
~
DF CK DF CK
VDDVSSV2V3VEEIV4) VDDVSSV 2 VJVEEIV~)
~~~Mf: D~~~ I
gE
) )'
CP OUT c
0
LOAD OUT -i
DF
s:
VDD
VSS
R
.(
\'
-i
> \\ ::c
R X
CONTROLLER
TIMING GEN
ROM IC.G.!
{ RAM 3R
~ \\ r-
C")
C
R ~ c
::c
R :>
<
m
~
::c
~ Brightness R = 0.5KD - 5KD
-') Adjustment
VR
VR=5KD-l0KD
s:
en
OV +5F -7 - -9V
~
U'1
N
W
00
G')
en
en
.....
~
OKI serniconauctor
MSM5839BGS
DOT MATRIX LCD 40 DOT SEGMENT DRIVER
GENERAL DESCRIPTION
The OKI MSM5839BGS is a dot matrix LC~'s segment driver LSI which is fabricated by low power CMOS metal
gate technology. This LSI consists of 40-bit shift register (two 20-bit shift registers), 40-bit latch (tVIO 20-bit latches),
40-bit level shifter and 40-bit 4-level driver.
It converts serial data, which is received from LCD controller LSI, to parallel data and outputs LCD driving waveform
to the LCD panel.
This LSI can drive a variety of LCD panel because the bias voltage, which determines the LCD driving voltage, can
be optionally supplied from the external source.
FEATURES
Supply voltage: 4.5 - 5.5V Bias voltage can be supplied externally
LCD driving voltage: 8 -18V 56 pin plastic flat package
Applicable LCD duty: 1/8 -1/128
PIN CONFIGURATION
(Top View)
NC
NC
NC
OF
LOAD
VDD
*This pin is internally connected with VOO, so it must not be connected to other signals. It is also prohibited to
use the 21 pin as a VOO independently. This pin may be used as a line reinforcing VOO.
58
- - - - - - - - - - - - . . - DOT MATRIX LCD DRIVER MSM5839BGS-
BLOCK DIAGRAM
-l I
r-L----------'-_-'--------\VEE I
-- I
OF
LOAOD----t
~------~~------~
01,
CP
I I
L- ----o-u---- -.---
OO~I
---1
MSM5839BGS
VOO-VEE 8+
-V
V
V EE _--~A"",-_
VSS RS~47n
59
DOT MATRIX LCD DRIVER MSM5839BGS - - - - - - - - - - - -
OPERATING RANGE
VOO
MSM5839BGS
VSS
V3
VEE I---'V'J'V----I
n -V
RS~47.l"
ti +V
D.C. CHARACTERISTICS
0
(Voo = 5V 10%, Ta = -20'" +85 C)
60
- - - - - - - - - - - - - - - DOT MATRIX LCD DRIVER MSM5839BGS-
SWITCHING CHARACTERISTICS
tr(ll
lOAD Rising/Falling time - - - 1 J.Is
tf(ll
CP
tsetup
O.BVDD
0.2VDD
D0
20
.D0
40
-----------------------+-----'
LOAD ___________________________0_.2_V_D_D-JL.~
61
DOT MATRIX LCD DRIVER MSM5839BGS - - - - - - - - - - - -
PIN DESCRIPTION
CP
Clock pulse input pin for the two 20-bit shift regis- LOAO
ter. The data is shifted to the two 20-bit latch at the The signal for latching the shift register contents
falling edge of the clock pulse. A data setup time is input from this pin.
(tsetupl and data hold time (tholdl are required When LOAD pin is set at "H", the shift register
each between 011. 0121 and CP. contents are transferred to 40-bit 4-level driver.
Schmit circuit is included in CP input circuit. When LOAD pin is set at "L", the last display
output data (0 1 - 0401, which was transferred
when LOAD pin was at "H", is held.
0020
The 20th bit of shift register contents is output
from 00 20 synchronized with the clock pulse. 0 1 -040
By connecting 0020 with 0121. two 20-bit shift Display data output pins which correspond to
registers are connected and becomes 40-bit shift each data bit in the latch.
register. One of VOO, V 2 , V3 or VEE is selected as a display
driving voltage source according to the combination
of latched data level and OF signal.
01 2 1
The 21st - 40th data from the LCD controller LSI These pins should be connected to the SEGMENT
is input to shift register from 0121' By connecting side of the LCD panel. Refer to the truth table
0020 with 0121. two 20-bit shift registers are below.
connected and becomes 40-bit shift register.
OF
Alternate signal input pin for LCD driving waveform.
VOO(V I I. VSS
Supply voltage pin. VOO should be 4.5 -5.5V.
VSS is a ground pin (VSS = OVI.
62
- - - - - - - - - - -___ DOT MATRIX LCD DRIVER MSM5839BGS-
TIME CHART
1/64 duty. 1/9 bias
1 - 6 4 + 1 + 2 .. -1-64-t-1 -+- 2.
LOAO
---1LJLJL JLJL1L
LATCH
DATA ~~
OF
LOAD
01,
OF CP
DOlO
~---~
Vu:.O
01, v,
I ---
CP ~ ___ --1L.JtSU 04 (,
LATCHOArA ~ ~
Vss
1-64 + 1 -I- 2. I- 64-t- 1 + 2 . /-64+ 1 ~
LOAO
--1L.JLJL JLJL1L --1LJL..JL -9 -llV
LATCH
DATA ~ ~ ~
(O,'s lewl)
OF ~ ~ ~
VOO
I
T
Va
t
Vb
0,
Vc
Vd
Ve
I
I 1
Va VOO 1.9VLCO
Vb VOO -2/9VLCO
Vc VOO-719VLCO
Vd VOO- 8 19VLCO
"P. VOO-VLCO
63
E!
al
.j::o
__ -t
al
.j::o
-<
""C
C
0
~
Q. -
(") -t
-:'
~ r- ~
f\
~
-t
LCD Qio ""C
x64 ) on
""C JJ
64 x 120 dots r- X
" (")
r-
(")
0}-064 0080 -t C
r-- DI.
COM/SEG OF
CP f--
"0~o, ~rN02 ~rN03 0
2:
(")
C
JJ
<:m
~ LOAD MSM5260GS
VOO Vl VJ Vs VSS
,....---
r - - CP
01.
O. - 0 40
MSM5839B
00 40
00 10
---
-
01.
CP
O. - 0 40
MSM5839B
GS
00 4 I - 01.
00 10 -
O. - 0 40
!;P MSM5839B
0040
0010
JJ
(")
C
JJ
- LOAD
GS r- LOAD ..- LOAD
GS
FRP
'---
OF
Oil.
VOO V l VJ VEE VSS
0 OF
Oil.
VOO V l VJ VEE VSS
0 OFVOO V l VJ VEE
Oil.
VSS
-t ~
en
~
00. I
CJ1
CO
, I
I W
VOO
I
I
1 J.
J cg
OJ
VSS C')
CP R l
OV +5V
en
LIP R
FRM
5R.
~
LCD
R
Controller
R
~ Brightness
) adjustment
VEE
OKI semiconductor
MSM5259GS
DOT MATRIX LCD 40 DOT SEGMENT DRIVER
GENERAL DISCRIPTION
The OKI MSM5259GS is a dot matrix LCD's segment driver which is fabricated by low power CMOS metal gate
technology. This LSI consists of 40-bit shift register (two 20bit shift registers), 40bit latch and 40bit 4-level driver.
It converts serial data, which is received from LCD controller LSI, to parallel data and output LCD driving waveform
to LCD.
Expansion of display can be easily made according to the number and structure of characters. Its 40bit shift register
consists of two 20bit shift registers and this make it possible to allot bits efficiently according to the numbers of
characters.
The MSM5259GS can drive a variety of LCD panel because the bias voltage, which determines the LCD driving
voltage, can be optionally supplied from the external source.
FEATURES
Supply voltage: 3.5 "'6.0V Interface with MSM6222GS (LCD controller LSI
LCD driving voltage: 3.0'" 6.0V with 16bit common driver and 40-bit segment
Applicable LCD duty: 1/8'" 1/16 driver)
56 pin plastic flat package (bent lead)
Bias voltage can be supplied externally
PIN CONFIGULATION
(Top View)
0" NC
0'0
o NC
NC
0,. OF
0,. LOAD
O~II 011
{Vaal CP
0l' Vaa
0H Vss
02.\ \to:!
0,. v,
*21 pin is used as a VDD supporting pin, however, 21 pin alone cannot be used as VDD pin.
65
- DOT MATRIX LCD DRIVER MSM5259GS - - - - - - - - - - - - - - - -
BLOCK DIAGRAM
-~~~:
. I
40-blt 4-Level Driver I
OF ...,....--.... I
LOA
VSS
CP Register
I I
L -- - -----0-0------ _ ~
OPERATING RANGE
66
- - - - - - - - - - - - - . DOT MATRIX LCD DRIVER MSM5259GS.
D.C. CHARACTERISTICS
(Voo = 5 10%, Ta = -20 _85C)
ON resistance RON*3
VOO-Vs =5V
I VN - Vo I = 0.25V*4 - - 5 kn.
Current consumption 100 CP = ~C, No load - - 0.5 mA
67
DOT MATRIX LCD DRIVER MSM5259GS. - - - - - - - - - - - - -
SWITCHING CHARACTERISTICS
0
(VDD = 5 10%, Ta = -20 _+85 C, CL = 15pF)
tpLH
"H", "L" propagation delay time
tpHL
- - - 250 ns
tr(CP)
Clock pulse Rising/Falling time
tf(CP)
- - - 50 ns
tr(L)
Load pulse Rising/Falling time - - - 1 J1s
tf(L)
tf(CP)
CP
0111
LOAD 0.2VDD
68
- - - - - - - - - - - - - . DOT MATRIX LCD DRIVER MSM5259GS.
PIN DESCRIPTION
01 1,01 21 LOAD
The date (1 st - 20th bit) from the LCD controller The signal for latching the shift register contents
LSI is input to 20-bit shift register from 011' The is input from this pin.
data (21st - 40th bit) is input to another 20-bit When LOAD pin is set at "H" level, the shift register
shift register from 01 21 , contents are transferred to the 40-bit 4-level driver.
(Positive logic) When LOAD pin is set at "L" level, the last display
output data (0 1 - 0 40 ), wh ich was transferred
CP when LOAD pin was at "H" level, is held.
Clock pulse input pin for the two 20-bit sh ift register.
The data is shifted to 40-bit latch at the falling VOO, VSS
edge of the clock pulse. A data set up time (tsetup) Supply voltage pins. VDO should be 3.0 -6.0V.
and data hold time (thold) are required between VSS is a ground pin (VSS = OV)
a Dl1 signal and a clock pulse.
Clock pulse rising time (t r ) and clock pulse falling VOD, V2, V3, Vs
time (tf) should be maximum 50ns respectively. Bias supply voltage pins to drive the LCD. Bias
voltage divided by the register is usually used as
0020 supply voltage source.
20th bit of the shift register contents is output from Refer to the application circuit.
0020' The data which was input from 011 is output
from this pin with 20 bits' delay, synchronized 0 1 -040
with the clock pulse. By connecting 00 20 to 0121, Display data output pin which corresponds to each
two 20-bit shift registers can be used as a 40-bit data bit in the latch_
shift register. One of VDD, V2, V3 and Vs is selected asa display
driving voltage source according to the combination
0040 of latched data level and OF signal.
40th bit of the shift register contents is output from (Refer to the truth table below)
0040' The data which was input from 01 21 is out-
put from this pin with 20 bits' delay, synchronized Latched data OF Display data output level
with the clock pulse. By connecting 0040 to the
next MSM5259GS's Oil, this LSI is applicable to "H" H Vs
a wide screen LCD. (Selected) L VDD
Refer to the application circuit.
"L" H V3
(Non-selected) L V2
OF
Alternate signal input pin for LCD driving.
Truth Table
69
DOT MATRIX LCD DRIVER MSM5259GS . - - - - - - - - - - - - -
TIME CHART
1/5 bias, 1/16 duty
Frame
signal
--......Jr:--l----_____ -- - - ~
I
LOAD
+16+ 1 +- 2+ 3~ T2+3 + -------- +16+ 1
~-------~
11 LATCH
DATA
=~----------==
~rL _______ JLIl..JL.SL.Jl.
OF
: I
--- ................
- ......
I ---
I ......................
OF
--; .....
1 _ _ _ _ _ _- ___
-- - -------..~1...._ _ _ __
LOAD --1l __ ___ nL...-_ _
01
CP
LATCH
=-----=
JULJLJl..JL ____ J1..JL..JL..flJ
_______ ___
~'-- -~== X\.... _ _ __
.....J
DATA
OF
VOO
1
Va ~
Ve - VOO-VLCO
Vss
70
- - - - - - - - - - - - - . DOT MATRIX LCD DRIVER . MSM5259GS.
--~. ..--.
OO
~ : ~= ~~:=;=
~- -r- : J= :- +L=~-4-+1 ===-= - :t :l ~=~'~,
o. V --L-----.--
Il
0,. -ffi-e-{f}-ffi-ffi- VOO -,-1--.-_ _ _ _ _ _ _ _ _----;'_ _- -
~:: O,~
t
OJ' ~~ ~~~---------3~~---
JII IE Ve
DOL
:
Segmcnt-. : :
,,
1
~VLCD I I r I I 1 I r1
Common at-Segment 0 1 a
1 ~ I I tJ L I I I I
(Select waveform) -"5 VLCD
VLeD
VLCD
3 0 I
"5 VLCD
l~
I
~VLCD
Common 02-Segment 0 1 I 13 1 R I
(Non-select waveform) -~ VLCD
-~ VLCD
! !
1
I
II
I
-VLCD
1 frame ,I
71
l!
'-I
N - -I
b> ~ c
5""D a
n
:ll
[
-I
s:
~
LCO or
s:
en""D
-I
JJ
S:""D _
~ ~ ~~ ~ N
0) r_ X
N n r
~ n
ren -I
_ C
n a c
SEG1-40 0 1 - 0 40 0 1 - 0 40 0 1 - 0 40 0:2
n JJ
_
COM1-16
00 011 MSM 0040 011 MSM 0040 011 MSM 00 40
g n <
.., JJ m
.--- CP
5259GS
0020 . . - - - CP 5259GS 00
20 .--- CP 5259GS 00 20 g, n JJ
- LOAO 01 21 tJ r--- LOAO 01 21 ] .--- LOAO 00 21 ] ! c
s:
MSM6222GS
.-- OF
VOOVSSV2 V3 Vs
- OF
VOOVSSV2 V3 Vs
- OF
VOO VSS V 2 V3 Vs
-I
en
s:
U1
CP N
U1
L (g
G)
OF en
VOO
GNO
VI
V2
V3
V4
'Is \
R R R R R
...... ...
..yyy .,1
TV"
=rc =r ;:c T
AlA AA A AA
YV' YY. VYT V T
c
C;:i OV
-i
The MSM5259GS is applicable to a static LCD by setting V 2 and Vs at ground level, connecting V3 to VOO and' -<
"'C
inputting COMMON SIGNAL to OF pin. n
This sample application circuit below is the case when the MSM5259GS is applied to a SObit LCD panel by connect r
ing two MSM5259GS in series.
"'C
"'C
r
n
-i
0
2
n
:JJ
80 Dot LCD PANEL n
__________________ Seg Seg. , SP.<J80 c
COM Seg, ----------------- =i
:OM
J----------------- ---f f---------------------4 "TI
0
:JJ
M
32 -1
:69f ;.
'tr r--
0, - - - - - - - - - - - - - - - - - - - - - 0 4
VDD
v,
[:
0,
VDD
V,
- - - - - - - - - - - - - - - - - - - 0
en
-i
C
0
-i
Duty l% I-- V 1 V1 -i s:
n
~
C ION
JAL
t 0.---- V,
OF
MSM5259GS
~ V,
OF
MSM5259GS
C
en
-i
:JJ
.---- J.- LOAD LOAD "'C
r
X
o
I
IN 01, DO 01, r
S
K CP ,-- '-- CP -< n
C
c
J1.... ~ VSS(GND) 00,0 01" ..- VSSIGND) 00'0 01" C
~ -..:-
- :JJ
L-...J L-J <:m
LOA ~
---JL
:c
s:en
S
C1I
N
C1I
(C
G)
..... en
Col
~
OKI semiconductor
MSM5260GS
DOT MATRIX LCD 80 DOT COMMON/SEGMENT DRIVER
GENERAL DESCRIPTION
11
The OKI MSM5260 is a dot matrix common/segment LCD driver LSI which is fabricated by low power CMOS. metal
gate technology. This LSI consists of 80bit shift register, 80-bit data latch, 80-bit level shifter and 80-bit 4-level
driver.
It converts serial data, which is received from LCD controller LSI, to parallel data and outputs LCD driving waveform
to LCD.
This LSI can drive a variety of LCD pannel because the bias voltage can be optionally provided from the external
source.
FEATURES
Supply voltage: 4.5 ....... 5.5V Can be used either as common driver or segment
LCD driving voltage: 8 ....... 18V driver
Duty 1/1 ....... 1/128 Interface with MSM6240GS LCD controller LSI
Bias voltage can be supplied externally 100 pin plastic flat package
PIN CONFIGURATION
(Top View)
999999999999PPPPPP22PP292?9PB9
- = .c. =-
:t -c
..J 'J' .. '_ 1.,1 - ::: '7 _l ':' 'J, .. W tJ - :::
0 1
NC
V.I
VDD"
ep
NC
011
NC
NC
NC
OOKO
NC
LOAD
OF
NC
COM/SEG
Vs
~~~~~illillW~~
2
V
74
- - - - - - - - - - - - - . DOT MATRIX LCD DRIVER MSM5260GS.
BLOCK DIAGRAM
O2 019 0 80
--O-O--VD~l
- - - - - - - - - - - - - - - - - - -
4 Level Oriver x 80 t I
Vs
Voo I
COM/SEG
LOAO 80 Bit Latches V!S I
~ VSS
01, ~------------~--~-------------~------<)OORO
I
CP .80 Bit Shift Register I I
I
L- ____ ---~
Voo
I 1
V2 r- Voo-Vs
~AA I ~t-I
MSM5260GS v 3 !-
Vs ~ v >V
Vss
RS;;>47rl
.J,.
75
DOT MATRIX LCD DRIVER MSM5260GS. - - - - - - - - - - - - -
OPERATING RANGE
*1 :VOO>V2>V3>VS
*2: When a series resistance of more than 47nis connected as shown below:
I r
VOO
V1r-
rh-
Value Unit
Parameter Symbol Condition
MIN TYP MAX
"H" Input Voltage VIH*l 0. 8V OO - - V
"L" Input Voltage VIL*l - - 0. 2V OO V
"H" Input Current IIH*l VIH = VOO - - 1 JiA
"L" I nput Current II L * 1 VIL = OV - - -1 JiA
"H" Output Voltage VOH*2 10 = -0.4 rnA VOO - 0.4 - - V
"L" Output Voltage VOL*2 10 = 0.4 mA - - 0.4 V
'(DO - Vs = 10V
ON Resistance RON*4
IVN -VOI=0.25*3
- - 2 kn
CP = DC
Power Consumption 100
VOO - Vs = 18V No load - - 100 JiA
76
- - - - - - - - - - - - - . DOT MATRIX LCD DRIVER MSM5260GS.
SWITCHING CHARACTERISTICS
(VOO = 5V 10%, Ta = 20"" 85C. CL = 15 p F)
Value
Parameter Symbol Condition Unit
MIN TYP MAX
tpLH
"H", "L" Propagation Delay Time - - - 250 ns
tpHL
Max. Clock Frequency fCp Duty = 50% 3.3 - - MHz
Clock Pulse Width tW(CP) - 125 - - ns
LOAD Pulse Width tWILl - 125 - - ns
Data Set-up Time 01 ~CP tsetup - 50 - - ns
CP ~ lOAD Time tCl - 250 - - ns
LOAD ~ CP Time tlC - a - - ns
Data Hold Time 01 ~ CP thold - 50 - - ns
tr(CP)
CP Rising/Falling Time - - - 50 ns
tf(CP)
trll) - -
lOAD Rising/Falling Time - 1 J,ls
tf(l)
CP
00 80
lOAD
PIN DESCRIPTION
011 0080
The date from the lCO controller lSI is input to 80th bit of the shift register contents is output
80-bit shift register from 011' (Positive logic) from 00 80 , The data which was input from 011
is output from this pin with 80 bits' delay,
CP synchronized with the clock pulse. By connecting
Clock pulse input pin for 80-bit shift register. The 00 80 with next MSM5260GS's Oil, this lSI is
data is shifted to 80-bit latch at the falling edge of applicable to a wide screen LCD. Refer to the
the clock pulse. A data set up time (tsetup) and a application circuit.
data hold time (thold) are required between a 011
signal and a clock pulse.
Clock pulse rising time (t r ) and clock pulse falling
time (tf) should be maximum 50 ns respectively.
77
DOT MATRIX LCD DRIVER MSM5260GS. - - - - - - - - - - - - -
LOAD COM/SEG
The signal for latching the shift register contents Selection signal input pin. MSM5260GS is used
is input from this pin. either as common driver or segment driver according
When LOAD pin is set at "H" level, the shift register to input signal level at COM/SEG pin.
contents are transferred to 80-bit 4-level driver When this pin is set at high level, MSM5260 is used
through 80-bit level shifter. as a common driver, while it is used as a row driver
When LOAD pin is set at low level, the last display at low level.
output data (0 1 - 0 8 0), which was transferred
when LOAD pin was at high level, is held. The display driving data 01 - 080, which are
determined according to the combination of latched
data and OF signal, are shown in the Table 1 below.
OF
Alternate signal input pin for LCD driving.
Table 1
When MSM5260GS is used as common driver, both side's non-selected level is to be supplied to V 2
LOAD pin and COM/SEG pin are to be connected and V3 pins.
to VDD. In this case, a bias voltage of common
VDD
VDD, Vss
Supply voltage pins. VDD should be 4.5 - 5.5V:
VDD t-----....--------tVDD
VSS is a ground pin (VSS = OV)
MSM
5260GS
VDD, V2, V3. Vs
Bias 'supply voltage pin to drive the LCD. Bias MSM
voltage divided .by the register is usually used as 5260GS
supply voltage source.
Figure 1 shows the case when bias voltage, which
is used to drive the LCD, is obtained by the
t - - - - - - - " - i V3
voltage disivion by external registers.
0 1 -080
Display data output pins which correspond to the
80bit latch contents.
One of VDD, V 2 , V3 and Vs is selected as a display VSS
VSS
driving voltage source according to the combination
of latched data level and OF signal. (Refer to the
time chart and Table 1.)
Contrast adjustment
1/64 duty 1/9 bias
Figure 1
78
- - - - - - - - - - - - - . DOT MATRIX LCD DRIVER MSM5260GS.
0, ~ __ ---1L-__ ~
InSide 0, ~ __ ----.JL_~_~
the IC
__ ~ ___ ..IlL-_ _
~
l COJSEG
LOADVDCf--
VOO
.... 01
"1
..... CP
V, I-- Va
a,
iI
VOO ~)
1-
I
Va I 5R
I
Vb >\l c
1
I VLCO
v.
~a
0,. f--
a,
VLCO
0 8
V. f - - Vr
1
Vss ~
Ve /' VR
Vd
Ve 9--11V
~1lrame --I
VOO
Va
Vb
0,
Vc
Vd
Ve
VOO
Va
I
Vb
Va~ VOO-1/9VLCO
0 Vb ~ VOO--2/9VLCO
Ve - VOO-7,'9VLCO
Vd 0 VOO-S/9VLCO
Ve Vc "VOO-VLCO
Vd
Ve VLCO LCD drivong voltage
79
DOT MATRIX LCD DRIVER MSM5260GS. - - - - - - - - - - - - -
.....
I
I
..... .......
I .....
.....
t
DF - -__. ._. . . . 1
.
LOAD
-.-ll ~
~---~
___ ----"------A--
CP ~ ___ JU1JLJ
LATCH DATA
~ ~
LOAD
r + +
64 1 2 - - + + +
64 1 2 -- - +- + -+- 64 1 2
1
I
I
I
I 1
Va = VDD - 1/9VLCD
Vb = VDD -- 2/9VLCD
Vc = VDD - 7/9VLCD
Vd=VDD - 8/9VLCD
Ve =VDD - VLCD
80
- - - - - - - - - - - - - . DOT MATRIX LCD DRIVER MSM5260GS.
APPLICATION CIRCUIT
STATIC display
Level Shifter
30 - l20Hl slgllal
.f1...I1.' 5V
o.---<I_--.
OV
D~~A .fUL
CLOCK Jl..IUUL
The MSM5260GS can make a static drive of a LCD by controlling the supply voltage. So it can be used to drive a
color LCD which requires high driving voltage. The value VDD - V S must be l8V > VD D - V s i:; 5V.
OV +5V
LIP
R
FRM
5R
MSM6240GS
R
VEE
81
OKI semiconductor
MSM5278 GS
DOT MATRIX LCD 64 DOT COMMON DRIVER
GENERAL
The OKI MSM5278GS is a dot matrix LCD's common driver LSI which is fabricated by low power CMOS metal gate
technology. This LSI consists of 64-bit bidirectional shift register, 64-bit level shifter and 64-bit 4-level driver.
This LSI has 64 output pins to be connectec1 to the LCD. By connecting more than two MSM5278GSs in series, this
LSI is applicable to a wide LCD panel.
This LSI can drive a variety of LCD because the bias voltage, which determines the LCD driving voltage, can be
optionally supplied from the external source.
FEATURES
PIN CONFIGURATION
(Top View) 80 Lead Plastic Flat Package
p p
f' p
? ? ? ~ ? .? ? 9 ? 9 ? ? P p
? p
? ? .~ P
0 411
10'4
NC 0
vEE 0"
v, 0,
v, 0"
v, D.n
NC D.,.
VOO 0"
SHL 0-'2
VSS 0"
NC 0.,,,
OF
NC 0,.
CP 0"
NC 0"
10, 0,.
s:- .'? '? P fl P '? 9 P 5' 5' 5' 5' 5' 5' 5' 5' 5' 5' .'?
f :? 9 f?
82
- - - - - - - - - - - - - . DOT MATRIX LCD DRIVER MSM5278GS.
BLOCK DIAGRAM
v.
--l
0 63 0 64
t
VEE VEE
I
~~:h
ABSOLUTE IVIAXIMUM RATINGS
OPERATING RANGE
83
DOT MATRIX LCD DRIVER MSM5278GS. - - - - - - - - - - - - -
D.C. CHARACTERISTICS
(Voo = 5V 10%. Ta = -20 _+85C)
SWITCHING CHARACTERISTICS
(VOO = 5V 10%. Ta = -20-+85C CL = 15pF)
tpLH
"H" "L" propagation delay time - - - 250 ns
tpHL
Max. clock frequency fCp - 1 - - MHz
Clock pulse width tW(CP) - 125 - - ns
Oata set-up time 10 1 (l064)~CP tsetup - 100 - - ns
Oata hold time la, (1064)~CP thold - 100 - - ns
tr(CP)
Clock pulse Rising/Falling time - - - 50 ns
tf(CP)
CP
tsetup
0. 8V OO
0. 2V OO
84
- - - - - - - - - - - - - . DOT MATRIX LCD DRIVER MSM5278GS.
PIN DESCRIPTION
101,1064, SHL
10 I and 10 6 4 are 64-bit bidirectional shift register by the H/L condition of SHL pin. Refer to the table
input/output pins. The shifting direction is selected below.
Shifting
SEL 10 1/ 10 64 Input/output Pin description
direction
The scanning data from the LCD controller LSI
10 1 Input is input from 10 1 synchronized with the clock
pulse. * 1
L 0 1 -+064
Shift register c'ontents output pin. The data
which was input from 10lis output from 1064
10 64 Output
with 64 bits' delay. synchronized with the
clock pulse. Refer to the application circuit.
The scanning data from the LCD controller LSI
1064 Input is input from 1064synchronized with the clock
pulse. * 1
H 064 -+0 1
Shift register contents output pin. The data
which was input from 1064is output from 101
10 1 Output
with 64 bits' delay. synchronized with the
clock pulse. Refer to the application circuit.
*1 The combination of the scanning data.IO I or 1064.and theLCD driving output. 0 1 ....... 0 64. is shown in the table
below.
CP
Clock pulse input pin for 64-bit bidirectional shift
register. The data is shifted to 64-bit level shifter at
the falling edge of the clock pulse. VDD
VDD
...-.....- - - - - - -.....--1V\
OF
Alternate signal input pin for LCD driving. R
Normal frame inversion signal is input.
1-~_----------1V2
VOO, VSS
R
Supply voltage pins. VDD should be 4.5 ....... 5.5V.
VSS is a ground pin. (VSS = OV) MSM
7R 5278GS
VI, V2, Vs, VEE
Bias supply voltage pins to drive the LCD. Bias R
voltage divided by the resistance is usually used r-~~-------~Vs
85
DOT MATRIX LCD bRIVER . MSM5278GS. - - - - - - - - - - - - -
VDD
VDD
VI
J R
R
7R
MSM5278GS
Op-Amp voltage follower
R
1/11 Bias. 1/100 duty
VR
01 - 0 6 4
Display data output pins which correspond to source according to the combination of the latched
64-bit shift register contents. One of V 1. V 2. V 5 data level and OF signal. (Refer to the truth table
and VEE is selected as a display driving voltage below'!
Truth table
86
- - - - - - - - - - - - - . DOT MATRIX LCD DRIVER MSM5278GS.
TIMING CHART
1/100 duty,l111 bias
VOO
I
~--~-~
100 I' 2 3 100 1 2 3 100 1 2 3 4
CP -A.JU1.JL ____ ---1lJ1Jl.JL ____ ~
. ,
o, (O~--~---~ 0,
I , 0,
O,(O,~ __ ~ __ ~
Inside
, I
the
I.C. t
a"
~
(0,001 1 I
__ ---IL--___ Sl 0
1
Va --~r--
I Voo
Vb ---+--- v,
0,
VLCD
v, R
R
v~
Vb
}
0"
VLCD
Vc
Vd
---+--_.-
- - _ _-L._ _
..
7R
R
V1
Vd
Ve
Ve _ _ _ L - - - -- 1
I 1 frame -11 .~ -13V
VOl) (V, 1, _ _ _ __
Va
Vb
0,
Vc
Vd
Ve
VJ!0(V, I -.-.."r-----
I
Vb
0 100
Va ~ VOO--l/11 VLCO
Vb = VOO- 2/11 V LCD
Vc = VOO-- 9/11 VLCD
Vd = V0010/ll VLCO
Vc Ve = VOO-,VLCO,
Vd
Ve
, -
VLCO: LCD driving voltage
87
r!
co
co l>
." 0
."
r- 0
-i
n
l> ~
-i l>
-i
VDD+5V -
-- 0 :0
--
---
II Z
C')
X
r-
-~
:0 C')
- C') 0
Controlier C
}44 4 }4 4
0
14 -i :0
8
FRAME
MSM5278
LOA
ECLK
P D.-D, ,,-VEE
VSS i -
SHL >-- -
LOAtf Do-D, V,-VEE
ECLK
VSS I-
SHL r- -
CP Do-D, V, -VEE
LOAD
ECLK
VSS
SHL
-
-
<:m
LOAD CP 10.. MSM5279 VODr-- >-- VDD _ :0
~~~ ~ f ~D
DF
~
'-i~;c
4 ____
00'0 - 0 ' 0,
EL Shifting ER
~,~~,,"--
I----------i
0 .. E
nable
direction
EL MSM5279
~ 0' 0,_- ____ 0..
-----------1
-
x
---
8 -
- EL MSM5279
'0,_ - - - --D..
\--------i
ER
~
CJ)
ECLK
re~o'O.. SEGI SEGSO SEGSI SEGl60 SEG561 SEG640 ~
~r-- ~vss 36 ....., 01
~~ 640xlOO 1/100 Duty N
4 v, '-VE' 100 -...J
CP LCD PANEL (640 x 200) 00
CP 10,4 64 100 C)
Voo CJ)
f - - ~vss .10 1
SHL r'
D,,-D,(UP) ............ OF -,
SEG641 SEG720 SEG721 SEGSOO SEGI201 SEGl2S0
--
VI -VEE
4
4
D. -D3(DOWN) CP
6
t---------- t Ellable
direction 1--------4 xS
--- ------1
4
'--- ~;DO
Vss ... '0, DFu"o ... --:---- 0, 0. 0 0,
-
pFo,o _____ 0,
SHLL
OF
r-- :'hift,ng EL f r-- DF MsM5279 - EL ER MSM5279 EL
4 VI -VEE
r-- ER direction VDD ER VDD 1------ - VDC
-
~
-=- -
1- ECLK MSM5279 SHL r-- ECLK SHL ECLK SHL
SS
MSM527S
1- LOAPo
_C
VSS
-D j V, -VEE
r- r-
LOAD VSS
r.F Do -D, V, -VEE r-- L0t'pttJo-D, V,_VEVE
VDD 0
V,
4 }4 4 14 4 J4
!~
V,
~
---
---
I~
V,
~
::=--
I~ ~ -
I~ :---"
V,
----
I~ ~
V
OKI semiconductor
MSM5279GS
DOT MATRIX LCD 80 DOT SEGMENT DRIVER
GENERAL
The OKI MSM5279GS is a dot matrix LC~'s segment driver LSI which is fabricated by CMOS low power metal gate
technology. This LSI consists of SO-bit bidirectional shift register, S(}'bit latch, S(}'bit level shifter and S().bit 4-level
driver.
It receives the display driving data, which consists of 4-bit parallel, from the LCD controller LSI, then output the
LCD driving waveform to the LC~'.
The MSM5279GS has the power down function which enables the MSM5279GS's power consumption low.
The MSM5279GS can drive a variety of LCD panel because the bias voltage, which determines the LCD driving
voltage, can be optionally supplied from the external source.
FEATURES
Supply voltage: 4.5 - 5.5V 4-bit parallel data processing
LCD driving voltage: S - 20V Can be interfaced with the MSM6255GS,
Applicable LCD duty: l/S -1/12S MSM6265GS, LCD controller LSI
Bias voltage can be supplied externally 100 pin plastic flat package
Power down function
PIN CONFIGURATION
(Top View)
ER
NC
VEE
v.
V.
V,
NC
OF
NC
VDD
SHL
VSS
D .
0,
0,
DC)
CP
ECLK
LOAD
EL
89
DOT MATRIX LCD DRIVER MSM5279GS. - - - - - - - - - - - - -
BLOCK DIAGRAM
Ic--"--'-------
----- ----- - -'- - '- --l
-,
11 SObit 4-Level Driver
VEE
VEE
t
OF
SObit Level Shifter
VDD
LOAD VSS
t
SO bit Latch (Edge trigger by DF/F)
SHL
4-bit x 20 Bidirectional Shift Register
I
......0 VDD
SHIFT CP
I
.Jl.J1.... CP r,VSS
EL
I
ER
ECLK
--~
JL!
I
*P.D; Power Down
90
- - - - - - - - - - - - - . DOT MATRIX LCD DRIVER MSM5279GS.
OPERATING RANGE
DC CHARACTERISTICS
0
(VDD = 5V 10%, Ta = -20 _+85 C)
CP = 1 MHz
Current consumption (1) IDDI - - 4 rnA
VDD - VEE = 18V, No load*6
CP = 1 MHz
Current consumption (2) IV
VDD - VEE = 18V, No load*7 - - 100 J.LA
Input capacitance CI f = 1 MHz - 5 - PF
91
DOT MATRIX LCD DRIVER MSM5279GS . - - - - - - - - - - - - -
SWITCHING CHARACTERISTICS
(Voo = 5V 10%. T a = -20""'-' +B5C CL = 15pF)
tpLH.
"H". "L" propagation delay time - - - 250 ns
tpHL
MAX. clock frequency fCp DUTY = 50% 3 - - MHz
CP ELCK pulse width tw - 125 - - ns
Load pulse width tW(L) - 125 - - ns
Data setup time tsetup - 100 - ... ns
CP -+ LOAD time tCL - 250 - - ns
LOAD -+CP time tLC - 0 - - ns
Data hold time CP -+ 0 0 ""'-' 03. ECLK -+ LOAD thold - 100 - - ns
tr
Clock pulse Rising/Falling time - - - 50 ns
tf
tr( L)
Load pulse Rising/Falling time
tf(L)
- - - 1 J1s
tf
tw tw i tf
I O.BVO~
~r-O.BVOD O.BVOO iit>:BVoo
CP
I\r 0.2VOO ,JrO. 2V oo ~ 0. 2V OO
tsetup thold tsetl!Q thold
On -03
>-
faB
k-Voo
0.2
Voo
O.B ~
VOO
1
:,.-- teE
K
tCL
~
O.B
rVOO Vo~
b.2
Voo
O.B ~
0.2
Voo
t
tr tw I
tLC
I)f"o.BV oo twILl ~~n-~
LOAD. ER(EL) Pt- 0 .2V OO
r 0. 2V OO
(Input) tpLH
tpHL
EL(ER) '}tc..
I- O.BVOO
0 . 2V ::m
(Output)
92
- - - - - - - - - - - - - . DOT MATRIX LCD DRIVER MSM5279GS.
-~
CP 4-bit x 20
SHIFT CP I
EL
>-...- ___-<1 ER
ECLK
SHL("")---.....- -
Internal circuit I
___ c_o_n_fi_9U~tion of MSM52~~
LOAD
(1st MSM5279GS's Ell
CP
ECLK
E F/F(ERI
1st
MSM5279GS
{ SHIFT CP
E F/F(ELl - - - - I J - - - - - . . ; . . J
2nd
E F/F(ER)
MSM5279GS
{
SHIFT CP
93
DOT MATRIX LCD DRIVER MSM5279GS . - - - - - - - - - - - - -
PIN DESCRIPTION
ER, EL
ELCK
Clock pulse input pin for ENABLE F/F. The active falling edge of the clock pulse. The clock pulse,
condition of ENABLE F/F is shifted to next which was input when the ENABLE F/F is not
MSM5279GS's ENABLE F/F at the falling edge active condition, is invalid.
of the clock pulse. ELCK is required every 20
CPo (Clock Pulse). SHL
ER and EL can be used as either input pin or output
pin according to the HI L condition of SH L. The
CP
Clock pulse input pin for the .4bit parallel shift shifting direction of each data, Do - D 3 , the Inputl
register. The data is shifted to 80-bit latch at the Output condition of ER and EL and the H/L
condition of SHL are described in the table below.
Do ~ 01 ~ Os - 0 7 7
Dl ~ 02 ~ 06 ~078
L Input Output
D2 ~ 03 ~ 0 7 ~079
D3 ~ 04 ~ Os ~080
Do ~ 080 ~ 0 76 ----+ 04
Dl ~ 0 79 ~ 075 ----+ 03
H Output Input
D2 ~ 078 ~ 0 74 ----+ O2
D3 ~ 0 77 ~ 073 ----+ 01
t t
end data start data
L L V3 OFF
H L VI ON
L H V4 OFF
H H VEE ON
94
- - - - - - - - - - - - - . DOT MATRIX LCD DRIVER MSM5279GS.
VDD
VDD
VI
MSM
V2 5279GS
V 3, V 4 - Nonselecting level
V4
Vs
-11 --13V
VDD
VI VDD
MSM
V2 5279GS
V3
Vs
--11 - -13V
0 1 - 0 80
Display data output pin which corresponds to the
OF Latched data Display data output level
respective .Iatch contents. One of VI, V3, V4
and VEE is selected as a display driving voltage L L V3
source according to the combination of the latched L H VI
data level and OF signal. (Refer to the truth table
on the right). H L V4
H H VEE
Truth table
95
DOT MATRIX LCD DRIVER MSM5279GS. - - - - - - - - - - - - -
TIME CHART
1/100 duty. 1/11 Bias
11 ~
LOAD
I
JL.Jl..---1L-
[
LATCH
DATA =cx=x=
I
~ VOO
OF ~ ~
II
OF ~L-~ _ _ __ vJ
LOAD V~ I VLCO
Ou -0 ..
CP
vel
Vd
LATCH DATA Ve
VR
[~:::HOATA ~
~
I I -11--13V
~~
~~"
Voo(Vd
1+ --.J---+I ~
I
I
I
I
l
Va I ! I
I
I I I va=vDD-lI11 VLCD
Vb
I
Vb'VOO-2111 VLCD
_1 VLCO
J
I I
VC=VOO-9111 VLCO
I
Vc Vd=VOO-l0Ill VLCO
Vd
Ve=VOO-VLCO
Ve
~
ER input I
SHL="L" (MSM5279GS's load signal)
ECLK
EL output
96
."
."
r
n
:::!
VOO + 5V o
VSS OV
JJ, 11 II ::----- :2
n
Controller
III, ,rl 1 I II ,11 1 I " -:~-- :c
n
c
MSM5278
=i
LOA1) O-OJ V,-VEE
FRAME
ECLK SHL ~
Vss
LOAD
EL MSM5279 VOO
OF ER
OF 0------0
x8
ECLK
C
CP
4100
LCD PANEL 1640 x 200)
o~
Do -03IUP) r:: s:
SEG641 SEG720 SEG721 SEG800 SEG1201
--------1
SEG1280
-i
61 x8
00-0) (DOWN) vOO
1 :c
~:8~-v
vss OF080MSM5:179 - 0,
j
t-_ _ _-+-I SHL
X
~
--- ER e~D f--
ECLK SHL r
MSM5278 LOAD VSS n
]p 0 0 -03 V,-VEE c
h f4 c
:c
II' ' I lj 1 I II III 1 I II ~~~_ <:
m
:c
II' 11 1l---~-======~----.J
s:
(I)
V s:
01
f\)
.....
e.g
G)
(I)
ID
.....
~
98
DOT
MATRIX
LCD
CONTROLLER
OKI semiconductor
MSM6222B-01GS
DOT MATRIX LCD CONTROLLER WITH 16 DOT COMMON DRIVER AND 40
DOT SEGMENT DR IVER
GENERAL DESCRIPTION
The OKI MSM62228-01 GS is a dot matrix LCD controller which is fabricated by low power CMOS silicon gate tech-
nology. In combination with 4-bit/8-bit microcontroller, character display on the dot matrix character type LCD can
be effected. This LSI consists of 16 dot COMMON driver, 40 dot SEGMENT driver, DISPLAY RAM, character
generator RAM, character generator ROM and control circuit.
Max. 80 characters' display can be controlled by MSM62228-01 GS by using together with the MSM5259GS.
The OKI MSM62228-01GS has the same. performance as HD44780. There is, however, slight differences between
these two devices as described in the table on page 101.
MSM62228 has ROM area for character code that can be programmed by custom mask. -01 GS is the standard version
with 160 characters, with small letter font 5 X 7, and 32 characters, with capital letter font 5 X 10, in this ROM area.
FEATURES
Easy interface with an 8-bit or 4-bit microcontroller. Character patterns can be programmable by CG
Dot matrix LCD controller/driver for small letter RAM. (Small letter font: 8 kinds, 5 X 8 dots, Capital
font (6 X 7 dots) or capital letter font (5 X 10 dots). letter font: 4 kinds, 5 X 11 dots).
Automatic power ON reset. Oscillation circuit for external register or ceramic
COMMON signal drivers (16) and SEGMENT signal resonator.
drivers (40). 1/8 duty (1 line; 5 X 7 dots + cursor), 1/11 duty
Control up to 80 characters when used in combina- (1 line; 5 X 10 dots + cursor), or 1/16 duty (2 lines;
tion with MSM5259GS. 5 X 7 dots + cursor), selectable.
Character generator ROM for 160 characters with Clear display even in case of 1/5 bias, 3.0V LCD
small letter font (5 X 7 dots) and 32 characters driving voltage.
with capital letter font (5 X 10 dots).
100
- - - - - - - - - - 1 1 . DOT MATRIX LCD CONTROLLER MSM6222B01GS
PIN CONFIGURATION
(Top View)
88g8888~~~
SEG 33 DB 1
SEG 37 UB 0
SEG 36
SEG 34 RS
SEG 33 DD
SEG 32
S~G 31 VDD
SEG 30 CP
SEG 29
SEG 28 V.
SEG 27 V,
SEG 26 V .
V,
SEG 25
SEG 24 V,
SEG 23 osc 2
N co .....
............ (,0
__ .n ~
.... COl
__ N
co - t.O .n
........ O'l 'Of M N
~ 0 u
~~~~~~~~~~~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ w
V)
Z
<.:l
V)
0
The increment and The address counter is incre- The address counter is incre-
decrement of the mented or decremented 6 p sec mented or decremented during
address counter in (when fosc = 250 KHZ) after the busy condition.
writing/reading the the busy condition i~ released. So, data can be written into/
data to/from the (Period of busy condition is read out from the RAM immedi-
CGRAM/DDRAM. 40ps) ately after the busy condition
So, the data cannot be written was over.
into/read out from the RAM
for 6 psec after the busy
condition was over.
101
~
o
N
tc
r-
C
0 0
(") -I
~
c s:
VOO r----------------------------------------------------------------------o L -I
GNO r---------------------------------------------------------------------~O CP
l>
G) :tI
~----------------------------------------------------------------------O OF jJ
X
s: r-
OSC 1 (")
OSC2
c
(")
Cursor blink
0
~
16-bit
control shift 2:
register -I
E
8 Iinstruction
c:J COMl-16
jJ
0
RS r-
decoder Parallell r-
R/W (101
Character
generator
M serial
c~Jnver-
sIan
m
jJ
OBo - DB"
RAM
(CGR~
s:
C/)
5 s:
0)
~ter
I\)
r
8 I\)
OB4 - OB 7
I\)
tc
:~~~~I.r ~40-~
it ~seg-
-
generator
ROM 140-bil
0 ment
signal SEG 1 _ 40
6
latc driver
(CG RAMI Q
C/)
VI 0--- ,
i
~ Display data
I ~n~~:~::
0---
F
V2
V.l 0--- RAM
V4 0--- (DO RAMI
V, 0---
L.--J L.--J
Y DO
- - - - - - - - - - - - - DOT MATRIX LCD CONTROLLER MSM6222B-01GS -
Applicable
Parameter Symbol Condition Value Unit terminal
Supply voltage Voo Ta = 25C -0.3 -+ 7.0 V VOO - GNO
Supply voltage for Vi. V2. V3 VOO - 9.0- Vi. V 2 V3
LCO displaying Ta = 25C V
V4. V S VOO + 0.3 V4. V S
R/W. RS. E.
Input voltage VIN Ta = 25C -0.3 -VOO + 0.3 V OBo -OB7
OSC1
Permissible loss Po - 500 mW -
Storage temperature T stg - -55 -+ 125 c -
Operating temperature Topr - -20 -+75 c -
OPERATING RANGE
Applicable
Parameter Symbol Condition Value Unit terminal
103
DOT MATRIX LCD CONTROLLER MSM6222B-01GS ....- - - - - - - - -
DC CHARACTERISTICS
(VDD=4.S-S.sv, T a =-20-+7SoCI
"H" input
voltage VIH2 - VDD - 1.0 - VDD V
OSC1
"L"input
voltage VIL2 - -0.3 - 1.0 V
"H" output
VOH1 10 = -0.20SmA 2.4 - V
voltage
DBo - DB 7
"L" output
VOL1 10 = O.4mA - - 0.4 V
voltage
"H" output
VOH2 10 = -40JlA 0.9VDD - V
voltage DO, CP, L,
"L" output DC,OSC2
VOL2 10 = 40JlA - - 0.1VDD V
voltage
COM voltage 10 = SOJlA
drop
Vc - - 2.9 V COMI -COM 16
Note 1
SEG voltage 10 = SOJlA
drop
Vs
Note 1 - - 3.8 V SEGI -SEG 40
104
- - - - - - - - - - - . . DOT MATRIX LCD CONTROLLER' MSM6222B01GS
(Note 1) Applied to the voltage drop (VC) occuring from terminals VDD, VI, V4, and Vs to each COMMON
terminal (COM1 to COM16) when 50 J-LA is flown in or out to and from all COM and SEG terminals,
and also to voltage drop (VS) occurring from terminals VDD, V2, V 3 , and Vs to each SEG terminal
(SEGl to SEG401.
When output level is at VDD, VI, or V 2 level, 50 p.A is flown out, while 50 p.A is flown in when the
output level is at V3, V4 or Vs level.
This occurs when 5V or -5V is input to VDD, VI, and V3 or to V2, V4, ann Vs, respectively.
(Note 2) Applied to the current value flown in terminal VDD when power is input as follows:
VDD =5V, GND = OV, VI = 3.4V, V2 = 1.8V, V3 = 0.2V, V 4 = -1.4V, and V2 = -3V.
105
DOT MATRIX LCD CONTROLLER MSM6222B-01GS ...- - - - - - - - -
(Note 31
Rf=91Kfb2%
OSC1P
Rf
OSC2
Minimum wiring is recommended between OSC 1 and Rf and
between OSC 2 and Rt.
(Note 41
(Note 51
Applied to pulse
input from OSC 1.
0.3VDD
ttr
tff
(Note 61
C1
OSC 1
/'v-t=l-4-~c"'m;' I.""
..-.-..R-'V'\f
OSC 2
Ad 2ti
Ceramic filter CSB250D (MURATA SEISAKUSHO Works I
At 1Mn 10%
C1 = C2 680pF 10%
Ad 3.3Kn 5%
106
- - - - - - - - - 1 1 . DOT MATRIX LCD CONTROLLER MSM6222B01GS.
~ Terminal
VI
number!
V
lline mode
VLCD V
2line mode
VLCD
DD- - 4 - DD- - 5 -
V VLCD V 2VLCD
V2 DD- - 2 - DD - --5-.
V VLCD V 3VLCD
V3 DD- - 2 - D D - --
5
V 3VLCD V 4VLCD
V4 D D - -- DD- - - 5 -
4
VLCD is the LCD driving voltage. (For UN (LCD line number!, refer to the initial set of the instruction code.)
INPUT/OUTPUT CIRCUIT
VDD
VDD VDD
VDD
VDD
~CONTROL
107
DOT MATRIX LCD CONTROLLER' MSM6222B01GS .11---------
PIN DESCRIPTION
10B
- - - - - - - - - - - DOT MATRIX LCD CONTROLLER MSM6222B01GS-
FUNCTIONAL DESCRIPTION
1. Instruction Register (I R) and
Data Register (DR)
These two registers are" selected by the register When an address code is written to IR, the data (of
selector (RS) terminal. the specified address) is automatically transferred
The DR is selected when the "H" level is input and from the DD RAM or CG RAM to the DR. By
I R when the "L" level is input. having the CPU subsequently read the DR (from
The I R is used to store the address code and the DR data), it is possible to verify DD RAM or
instruction code of the display data RAM (DD CG RAM data.
RAM) or character generator RM (CG RAM). After the writing of DR by the CPU, the DD RAM
The IR can be written into, but not be read out by or CG RAM of the next address is selected to be
the microcontroller (or CPU). ready for the next CPU writing.
The DR is used to write into/read out the data to/ Likewise, after the reading out of DR by the CPU,
from the DD RAM or CGRAM. DD RAM or CG RAM data is read out by the DR
The data written to DR by the CPU is automatically to be ready for the next CPU reading.
written to the DD RAM or CG RAM as an internal Write/read to and from both registers is carried out
operation. by the READ/WRITE (R/W) terminal.
R/W RS Function
L L IR write
H L Read of 'busy flag (B F) and address counter (ADC)
L H DR write
H H DR read
109
DOT MATRIX LCD CONTROLLER MSM6222B01GS - - - - - - - - -
(Example)
When DD RAM L H L H L H L
address is 2A
2 A
(1) Coordination between address and display position in the 1-line display mode
First
digit 2 3 4 5 79 80 ~ Display position
I 00
I 01 0'2 03 04 ~ 4E 4 F f - - DD RAM address (hex.)
MSB
f
LSB
When the MSM6222B-01 GS is used alone, 8 characters max. can be displayed from the first digit to the eighth
digit.
First
digit 2 3 4 5 6 7 8
I 00 01 02 03 04 05 06 07
When the display is shifted by instruction, the coordination between the LCD display position and the DD RAM
address changes as shown below:
First
(Display digit 2 3 4 5 6 7 8
shifted
to right)
I 4F
I 00 01 02 03 04 05 06
First
(Display digit 2 3 4 5 6 7 8
shifted
to left) I 01 02 03 04 05 06 07 08
110
- - - - - - - - - - - - - . DOT MATRIX LCD CONTROLLER MSM6222B-01GS
When the MSM6222GS is used with one MSM5259GS, 16 characters max. can be displayed from the first digit
to the sixteenth digit as shown below:
First
digit 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
I 00 01 02 03 04 05 06 07 08 09 OA OB OC 00 OE OF
When the display is shifted by instruction, the coordination between the LCD display and DO RAM address
changes as shown below:
First
digit 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
(Display shifted to right) 14F 1 00 I I 01 02 1 03 1 04 1 05 1 06 1 07 1 08 1 09 1OA I I
OB OC 100 I I
OE
Since the MSM6222B-01 GS has a DO RAM capacity for 80 characters, max. 9 pieces of MSM5259GS can be
connected to MSM6222B-01 GS so that 80 characters can be displayed.
First
MSM6222B-01GS display MSM5259GS (11 display MSM5259GS (2) MSM5259GS (9) display
- (8) display
111
DOT MATR IX LCD CONTROLLER MSM6222B01GS ...- - - - - - - - -
(2) Coordination between address and display position in the 2line display mode
First
First line
Second line
digit
00 01
2
I 40 I 41 I 42 I
3
02
4
03
43
5
04
I 44 I
39
26
I 66 I
::V-
40 - Display position
(Note) Note that the last address of the first line is not consecutive to the head address of the second line.
When MSM6222B-01 GS is ued alone, 16 characters (8 characters x 2 lines) max. can be displayed from the first
digit to the eight digit.
First
First line
Second line
When the display is shifted by instruction, the coordination between the LCD display position and the DD
RAM address changes as shown below:
First
2 3 4 5 6 7 8
First line
(Display shifted to right)
Second line
2 3 4 5 6 7 8
First line
(Display shifted to left)
Second line
When the MSM6222B-01 GS is used with one MSM5259GS, 32 characters (16 characters x 2 lines) max. can be
displayed from the first digit to the sixteenth digit.
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
First line
Second line
112
- - - - - - - - - 1 1 . DOT MATRIX LCD CONTROLLER MSM6222B-01GS
When the display is shifted by instruction, the coordination between the LCD display position and the DD
RAM address changes as shown below:
I\,
y Y
MSM6222B-01 GS display MSM5259GS display
J\.
y y
MSM6222B-01 GS display MSM5259GS display
Since the MSM6222B-01 GS has a DD RAM capacity for 80 characters, max. 4 pieces of MSM5259GS can
be connected to the MSM6222B-01 GS in the 2-line display mode.
3 4 5 6 7 a 9 10 11 12 13 14 15 16 17
First line
Second line
~ ________ ~ ________ -J~ ________ ~ ________ .-J'~~ ________ ~ _ _ _ _ _ _ _ _- J
113
~
~
:-
Table 2 Table of correspondence for character codes and characters (character pattern)
c
o
-f
~ s
MSB
Lower BIT
-
1101
0000 0010 0011 0100 0101 0110 0111 1010 1011 1100 1110 1111
,
4 BIT
0000
LSB
CG
RAM (1) 08 @fij p ~ " .... p p -
'/ ~ : ~ 0: liP -f
::0
! 1 Ag X
Q~ a~ q~ 'J :,
'Ii .~ 'Iq
...
(2)
! I D ri
0001 r
n
r ftP He
.. I. r [ f
0010
(3) 2 ~.. B B R f( b 1:.1 r
., ,
....
01 c
n
0011
(4)
"i C 55 3::=; c cC sS .1 "'.~ ''''l 0000 '. :e f,
~
.~
o
:2
-f
$$ 44 DD T I
0100
0101
(5)
(6)
55 EE u l
~ ~..
d c:I I t ... , I I,t- \' l' ~ IJ Q~
eEl uL .
~" ' t 'J ~ 13 iiU
'
. ::0
o
r
r
m
--
::0
0110
m && 6 F vU 6 F ff vl) 7::; 11 '3 r: I;
Pp S
0111
1000
(8)
(1)
,
(
77 ~
wLL gg J 77
( 88 HH xX hh xx [ .j
G [ ... w ... :-' ::<
'/ ., i:;
,~ ~g
" 1.1 V .,
rrJl
~
\:.-,.:..
en
S
en
I\)
I\)
I\)
I Yy ii . .J '.J to
) It -I
Yy
.
(2) ) 9Q I Y~ ~ 'r
6
1001 " 'l
-i ....a
lJ zZ i..l zz !~
iJ r~
G')
1011
(4)
+ ; K~ [ [ klc: { { ~" "~ "t II Ij X :-:
lin
1100
(5)
. J LL I 1 I I '.' .,., >:J ,..,.I "- (l
'.I l' .~ 1'1 PI
--
"
"0.
1101
1110 (7)
, > ) 1\ A
n rl -~ '3 1:~ : ;t . .. ...
~ n
I.)
1111
(8)
1/ o (
- - 0 --Eo ' IIJ 'J
"~
a
- - - - - - - - - - DOT MATRIX LCD CONTROLLER MSM6222B-01GS-
7. Character Generator RAM (CG RAM) character code "00" (hex.l or "OS" (hex.l.
When the S-bit character code of the CG
The CG RAM is used to display user's original char- RAM is written to the DD RAM, the
acter patterns other than the CG ROM. character pattern of the CG RAM is dis-
The CG RAM has the capacity (64 bytes = 512 bits) played on the LCD display position cor-
to write S kinds for 5 X 7 dots and 4 kinds for responding to the DD RAM address. (DD
5 X 10 dots. RAM data, bit 0-2 correspond to CG
When displaying character patterns stored in the RAM address, bit 3-5.)
CG RAM, write Sbit character codes (00-07 or
02 to OF; hex.) on the left side as shown in Table 2.
(2) When character pattern is 5 x 10 dots
It is then possible to output the character pattern
(See Table 3-2)
to the LCD display position corresponding to the
DD RAM address. A method to write character pattern into
The following is a description on how tel write and the CG RAM by the CPU
read character patterns to and from the CG RAM. Four bits of CG RAM address, bit 0-3,
correspond to the line position of the char-
(1) When the character pattern is 5 X 7 dots acter pattern.
(See Table 3-1).
First, set increment or decrement by the
A method to write character pattern into CPU, and then input the address of the CG
CG RAM by CPU: RAM.
Three bits of CG RAM address 0-2 corre- After this, write the character pattern code
spond to the line position of the character into the CG RAM, line by line from DBo-
pattern. DB7.
First, set increment or decrement by the DBo to DB7 correspond to CG RAM data,
CPU, and then input the CG RAM address. bit 0-7, in Table 3-2.
After this, write character pattern codes It is displayed when "H" is set as the
into CG RAM through DBo "'" DB7 line by input data, while it is not displayed when
line. "L" is set as the input data.
DBo to DB7 correspond to CG RAM data As the ADC is automatically incremented or
0-7 in Table 3-1. decremented by 1 after the writing of
It is displayed when "H" is set as input data to the CG RAM, it is not necessary to
data and is not display when "L" is set set the CG RAM address again.
as input data. The line in which the CG RAM address a
Since the ADC is automatically incremented to 3 is "A" (hex) is ORed with cursor at
or decremented by 1 after the writing of the cursor position and displayed on the
data to the CG RAM, it is not necessary to LCD.
set the CG RAM address again. When the CG RAM data, bit 0-4, CG
The line, the CG. RAM address 0-2 of RAM address, bit 0-3, is "a" "'" "A",
which are all "H" ("7" in hexadecimal it is displayed on the LCD as the display
notation), is the cursor position. It is ORed data. When the CG RAM data, bit of 5-7,
with the cursor at the cursor position and and CG RAM, bit data is 0-4 and CG RAM
displayed to LCD. address data is "B" "'" "F", it is not output
For th is reason, it is necessary to set all to the LCD.
input data that become cursor positions But in this case, CG RAM can be used as
to "L". RAM and it can be written into/read out.
Although CG RAM data 0-4 bit are output So, it can be used as the data RAM.
to the LCD as display data, CG RAM data
bit 5-7 are not. The latter can be written A method to display the CG RAM character
and read to and from the RAM, it is there- pattern to the LCD:
fore allowed to be used as data RAM. The CG RAM is selected when 4-upper
Accordingly, it is necessary to set all input order bits MSB of the character code are
data which become cursor positions to "H". all "L".
0-4 bit of CG RAM data are output to the As MSB and LSB of character code LSD
LCD as the display data, however, 5-7 bit are invalid, the display of "year" ~ in Kanji
of CG RAM data are not. But it can be used character is selected by character codes
as RAM because data can be written/read "00", "01", "OS", and "Og" (hex.l as in
into/from it. Table 3-2.
A method to display the CG RAM character When the CG RAM character code is written
pattern to the LCD: to the DD RAM, the CG RAM 'character
The CG RAM is selected when 4-upper pattern is displayed on the LCD display
order bits MSB of the character code are position corresponding to the DD RAM
all "L". address.
As character code bit 3 is invalid, the dis- (DD RAM data bit 1, 2 correspond to CG
play of "a" in Table 3-1, is selected by RAM address bit 4,5.)
115
DOT MATRIX LCD CONTROLLER' MSM6222B-01GS .....- - - - - - - - -
L
\L
H
H
H
H
H L
L
L
H
H
L
L
H
L
H
L
\ H
H
L
L
X X X H
L
L
H
L
L
L
L
H
L
L
L
L
H
L
L
H
H
L
L
H
L L L L X L L L
l~
L L H
~
L H L H L H L L
L H H H H L L L
H L L H L H L L L L L L X L L H
H L H H L L H L
H H L H L L L H
H H H L L L L L
I-- _________ -
I~-
- ~~ -----.....
H H H L L L X X X LI!!..H,!!JL
L H L L H L L
~
L
L H L L L H L L
)
L H H L L H L L
H L L L L H L L L L L t X H H H
H L H L L H L L
H H L LfE Hf:ilL
H H H L L L L L
X: Irrespective of H/L
Table 3-1 Relation between CG RAM data (character pattern) vs. CG RAM address and DO RAM data vs. charac-
ter pattern when the caracter pattern is 5 X 7 dots. Above example indicate "OKI".
116
- - - - - - - - - - . DOT MATRIX LCD CONTROLLER MSM6222B01GS.
H~
L L L H
L L H L IH L LIH L
L H
L L H H L H H H H
L H L L L HITIH L
L H L H IHHHHH L L L L X L L X
L H H L L L L H L
L H H H L L L L L
H L L L L L L L L
H L L H L L L L L
HLHL LLLLL
-- - - \-1- - -- - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - f-- - - - - - - - - - - - - - - - - -
H L H H X X X X X
~~~; )
L H L L L L X X X L L L L L
L L L H L L L L L
L L H L L H H H H
I~ H~ ~
L L H H
L H L L
L H L H L L L L X L H X
L H H L L H H H H
L H H H L L L L H
H L L L L L L L H
H L L H L H H H L
H L H L L L L L L
-- - - tTH- [- "H-R - - - - - - - -- - -X-X-X -X -X- - -- - - - - - - - - - - - - - - - - - - - - - ------
)
:H H L L )
IH H L H
IH H H L
:H H H H
--- -- ______ I--::
/~----...--
L L L L X X X L L L L L
L L- L H L L L L L
L L H L H H L H H
L L H H L H L H L
L H L L IHLLLIHl L L L L X H H X
L H L H IHLLLIHI
L H H L L H H H L
L H H H L L L L L
H L L L L L L L L
H L L H L L L L L
IH L H L L L L L L
IH-I.-"H-"H-- - ---- --- -- -X-X-X- X-)f ---:--- -- - - -- - - -- -- --- - -- -------
:H H L L
:H H L H
:H H H L
IH H H H
)
X: Irrespective of H/L
Table 3-2 Relation between CG RAM dada (character pattern) example vs. CG RAM address and DO RAM data
vs. character pattern when the character pattern is 5 X 10 dots. Above examples indicate Sf. , g, v respec-
tively.
117
DOT MATRIX LCD CONTROLLER MSM6222B-01GS . 1 1 - - - - - - - - -
DBO
ADC I L ILL L
' - - _ - - ._ _ -J.~
o 7
First
digit 2 3 4 5 6 7 8 9 79 80
In l-linedisplay mode I I I
00 01 02 1 03 1 04 1 05 1 061 ~71 081 ~14E 14FI
l Cursor and blink position
First
digit 2 3 4 5 6 7 8 9 39 40
Fi rst line
In 2line display mode {
Second line
(Note) The cursor and blink are displayed even when the CG RAM address is set to ADC.
For this reason, it is necessary to inhibit the cursor and blink display while the CG RAM address is set to the
ADC.
118
- - - - - - - - - . DOT MATRIX LCD CONTROLLER, MSM6222B-01GS.
I
I
0.2 V I 0.2 V
Voo I I
I
~I
tOFF
I
tON;;;;' 100 ms tOFF;;;;' 1 ms
11. Data Bus with CPU The first time data input/output is made for
4-high order bits (DB4 to DB7 when the
The data bus with CPU is available either once for interfaces data length is 8 bits) and the second
8 bits or twice for 4 bits allowing the MSM6222B- time data input/output is made for 4-low
01GS to be interfaced with either an 8-bit or 4-bit order bits (OBO to DB3 when the interface
CPU.
data length is 8 bits!' Even when the data
input/output can be completely made through
(1) When the interface data length is 8 bits
4-high order bits, be sure to make another
Data buses DBO to DB7 (8 pes.) are all used input/output of 4-low order bits. (Example:
and data input/output is carried out simul- Busy flag Read)
taneously. Since the data input/output is carried out in
two steps but as one execution, no normal
(2) When the interface data length is 4 bits data transfer is executed from the next input/
The 8-bit data input/output is carried out in output if accessed only once.
two steps by using only 4-high order bits of
data buses DB4 to DB7 (4 pes.!.
119
DOT MATRIX LCD CONTROLLER MSM6222B01GS - - - - - - - -
RS
/
I \
III R/W
Busy
J
(internal
operation) ===>< No
I
X 7 ~
'"
IR7 \'Bus y
DB7
Busy
120
__________________________________ ~I
RS
-
OJ
Fig. 3 Example of 4bit data transfer 6
G)
... en
~
~
- DOT MATRIX LCD CONTROLLER MSM6222B-01GS - . . . . - - - - - - - - -
Instruction code
R/W
L
RS
L L L
DBS
L L L L L
DBo
H
When this instruction is executed, the LCD (Note) All DO RAM data goes to "20" (hex.).
display is cleared. while the address counter (ADC) goes
When the cursor and blink are 'in display. the to "00" (hex.). The execution time,
blinking position moves to the left end of the when the OSC oscillation frequency
LCD (the left end of the first line in the 2line is 250 KHz is 1.64 ms (max.).
display model.
When this instruction is executed. the blinking (Note) The address counter (ADC) goes to
position moves to the left end of the LCD (to "00" (hex.). The execution time, when
the left end of the first line in the 2-line display the OSC oscillation frequency is
mode) when the cursor and blink are being 250 KHz, is 1.64 ms (max.).
displayed.
When the display is in shift, the display returns
to its original position before shifting.
CD When the I/O is set. the 8bit character code shifts to the left (I/O = H) or to the right
is written or read to and from the DO RAM, (I/O = L) by 1 character position.
the cursor and blink shift to the right by 1 When the character is read from the DO
character position (I/O = H; increment) or RAM when SH = H is set, or when the
to the left by 1 character position (I/O = L; character pattern data is written or read
decrement) . to or from the CG RAM when SH = H is
The address counter is incremented (I/O = H) set. the entire display does not shift. but
or decremented (I/O = L) by 1 at this time. normal write/read is performed (the entire
Even after the character pattern code is display does not shift. but the cursor and
written or read to and from the CG RAM. blink shift to the right (I/O = H) or to the
the address counter (ADC) is incremented left (I/O = L) by 1 character position.
(1/0= H) or decremented (I/O = L) by 1. When SH = L is set, the display does not
@ When SH = H is set, the character code is shift. but normal write/read is performed.
written to the DO RAM. and then the The execution time when the OSC oscillation
cursor 3nN blink stop and the entire display frequency is 250 KHz is 40 Jis.
122
- - - - - - - - - . DOT MATRIX LCD CONTROLLER MSM6222B01GS.
CD The 01 bit controls whether the character @ The blink is cancelled when B = L and it is
pattern is displayed or extinguished. executed when 01 = Hand B = H.
When 01 is "H", this bit makes the LCD In the blink mode, all dots (including the
display the character pattern. cursor), displaying character pattern, and
When 01 is "L", this bit distinguishes the cursor are displayed alternately at 409.6 ms
LCD character pattern. The cursor and (in 5 X 7 dots character font) or 563.2 ms
blink are also cancelled at this time. (in 5 X 10 dots character font) when the
(Note) Different from the display clear, esc oscillation frequency is 250 KHz.
the character code is absolutely The execution time when the esc
oscillation
not rewritten. frequency is 250 KHz is 40 /lS.
(3) The cursor goes off when C = L and it is
displayed when 01 = Hand C = H.
When DIC = Land R/L = L, the cursor and blink positions are shifted from the first line
blink position are shifted to the left by 1 to the second line when the cursor is shifted
character position (A DC is then decremented to the right next to the fortieth digit (27; hex.)
by 1). in the first line. No such shifting is made in
When D/C = Land R/L = H, the cursor and other cases.
blink position are shifted to the right by 1 When shifting the entire display, the display
character position (A DC is then incremented pattern, cursor, and blink positions are in no
by 1). case shifted between lines (from the first line
When D/C = Hand R/L = L, the entire display to the second line or vice versa).
is shifted to the left by 1 character position. The execution time when the esc oscillation
The cursor and blink positions are also shifted frequency is 250 KHz is 40 /lS.
with the display (ADC remains unchanged).
When D/C = Hand R/L = H, the entire display
is shifted to right by 1 character position. The
cursor and blink positions are also shifted
with the display (ADC remains unchanged).
In the 2line display mode, the cursor and
123
DOT MATRIX LCD CONTROLLER MSM6222B01GS - - - - - - - -
@ The 5 X 7 dots character font is selected This initial set has to be accessed prior to
when F = L, while the 5 X 10 dots character other instructions excepting the busy flag
font is selected when F = Hand N = L. read after powering ON the MSM6222B
01GS.
When CG RAM addresses, bit C s to Co from the CPU begins with addresses, bit Cs to
(binary), are set, the CG RAM is speCified, Co, starting from CG RAM selection.
until the DD RAM address is set. The execution time, when the OSC oscillation
Write/read of the character pattern to and frequency is 250 KHz, is 40 J,ls.
When the DD RAM addresses D6 to DO (binary) Likewise, in the 2line mode, D6 to Do (binary)
are selected, the DD RAM is specified until must be set to one of the values among
the DD RAM address is set. "00" '" "27" (hex.! or "40" - "67" (hex.!.
Write/read of the character code to and from When any value other than the above is input,
the CPU begins with addresses D6 to Do it is impossible to make a normal write/read
starting from DD RAM selection. of character codes to and from the DD RAM.
In the lline display mode (N = H), however, The execution time, when the OSC oscillation
D6 to Do (binary) must be set to one of the frequency is 250 KHz, is 40 J,ls.
values among "00" to "4F" (hex.1.
124
- - - - - - - - - 1 . DOT MATRIX LCD CONTROLLER MSM6222B01GS.
When E7 to EO (binary) codes are written to display shift". The execution time, when the
the DD RAM or CG RAM, the cursor and OSC oscillation frequency is 250 KHz, is
display move as described in" (5) Cursor and 40 ~s.
The busy flag (BF) is output by this instruction match the DD RAM address or CG RAM
to indicate whether the MSM6222B.Q1 GS is address. The decision of whether it is a DD
engaged in internal operations (BF = "H") or RAM address or CG RAM address is made by
not (BF = "L"). the address previously set.
When BF = "H", no new instruction is ac Since the address counter value when BF = "H"
cepted. It is therefore necessary to verify BF = is sometimes incremented or decremented by 1
"L" before inputting a new instruction. during internal operations, it is not always a
When BF = "L", a correct address counter value correct value.
is output. The address counter value must Execution time is 1 ~s.
Character codes (bit P7 to Po) are read from (Note) Conditions for the reading of correct
the DD RAM, while character patterns (P7 to data:
PO) from the CG RAM. 1 When the DD RAM address set or
Selection of DD RAM or CG RAM is decided CG RAM address set is input
by the address previously set. before inputting this instruction.
After reading those data, the address counter 2 When the cursor/display shift is in
(ADC) is incremented or decremented by 1 put before inputting this instruction
as set by the shift mode mentioned in item in case the character code is read.
"(3) shift mode set". 3 Data after the second reading from
The execution time, when the OSC oscillation RAM when read more than 2 times.
frequency is 250 KHz, is 40 ~s. Correct data is not output in any
other case.
125
DOT MATRIX LCD CONTROLLER MSM6222B01GS - - - - - - -
126
- - - - - - 1 1 . DOT MATRIX LCD CONTROLLER MSM6222B-01GS.
S \, 12 1 3 1 4 \ 5161 7 IS 19 1'12
ooM' c,~r
1 =f1~1 ttl!ttlljjlljj"~1ttll.:ttII~1
Vs
1t=1 =====
1-=111=1=1
I ' frame I
I
ooM+f -+I-HII-It--I++11-t-t11-H11-t-11H-1++11++II-tI-I- - -
l
COMS !"rVs
II I I I III I I I I I I I III I I I I
COM91Vl .~:D -11-+-1I~I+-+1I +-+11-+-+11--+-1111-+-1+-+-11+-+11-+-+11-+-11IH-I- - -
V. --'--'L....I......I..................l........l-.I.--'-L-I...~-'--'--'~'----_ __
Vs
COM' 61Vl.~:D
V.
--tl--+-ll I~I+-+-1I +-+11+-+11-+-1111-+-1+-+-1I +-+11+-+1I-HIIr-t--I- - -
Vs
SEG
(Output
"del
jVl.~:D ---1..-1
V.
+-r--I
.
. I------J.-111---r-------
I -----L.-f---rll .I . .
V, '--'"
t 1
-......,/ y L'ghtong
'---------"------"--- waveform
DF --
127
- DOT MATRIX LCD CONTROLLER' MSM6222B01GS ---- - - - -
11 I 1 I2 I 3 I 4 I 5 16 I 7 I8 I 9 I 10 111 I 1 I 2 I
I 1 frame I
OOM' F~1 II II II I I II II II II II II II II II II
COMI6{V:~; =1=1=11=11=11=11=11=1=11=11=11=11=1=11=11=11==
V~ - - - - - - - - - - - -
Extinguishing
r-.-----y------(.,......--_........-, waveform
~ r ,~ ,-
waveform
OF - I I I I I I I I I I I I I I I I I I I I I I I I I I I I
L -- I I I I I I I I I I I I I I ____ __
128
----II. DOT MATRIX LCD CONTROLLER MSM6222B-01GS.
'DO "I I:' I , I' I ' I ' I , I ' I , J " I" I " I" I " I " I "I j :'
OM'~:V: I:
{
I
11111111111111111111111111111
I
I 1 trame I
OM2 {r ~~
III
I
II 11111111111111111111111111111
I
OOM";~ {
'DO II_ 111111111111111111111] 1111111
II II
:
V~ 1
OF -
L -- I I I I I I I I I I I I I I I I I I
129
DOT MATRIX LCD CONTROLLER MSM6222B01GS - - - - - - - - -
Range
Item Symbol Unit
MIN TYP MAX
R/W and RS set-up time tB 140 - - nS
E and H pulse width tw 280 - - nS
R/W and RS holding time tA 10 - - nS
E rise time tr - - 25 nS
E fall time tf - - 25 nS
E and L pulse width tL 280 - - nS
E cycle time tc 667 - - nS
DBo to DB, input data set-up time tI 180 - - nS
DBo to DB, input data holding time tH 10 - - nS
Range
Item Symbol Unit
MIN TYP MAX
R/W and RS set-up time tB 140 - - nS
E and H pulse width tw 280 - - nS
R/W and RS holding time tA 10 - - nS
E rise time tr - - 25 nS
E fall time tf - - 25 nS
E and L pulse width tL 280 - - nS
E cycle time tc 667 - - nS
DBo to DB, data output delay time tD - - 220 nS
DBo to DB, data output holding time to 20 - - nS
Table 5: Output characteristics to the CPU
130
- - - - - - - - - 1 1 . DOT MATRIX LCD CONTROLLER MSM6222B.01GS.
Output characteristics to MSM5259GS
(Voo = 4.S ...... S.SV. Ta = -20 ...... +7S0C)
Range
Item Symbol Unit
MIN TYP MAX
Figures 7. 8 and 9 show input timing from the CPU. output timing to the CPU and output timing to
MSM5259GS respectively.
I, If
II
l!&
Inpul
~
DBO - DS7 )jVIH VIH
K VIL dala VIL
tr.
Figure 7
131
DOT MATRIX LCD CONTROLLER MSM6222B01GS .11---------
Output timing to the CPU
11 RS )1 VIH
"'" VIL ~:t l(
IW
~
IB
IL
VIL
VIH VIH ~ VIL ~
Ir If
~ r!2-
Oulpul
DBO - DB7 ) cVOH
kYOL dala
VnH
VOL K
IC
Figure 8
DO
CP
OF
Figure 9
132
- - - - - - - - - 1 . DOT MATRIX LCD CONTROLLER MSM6222B-01GS.
TYPICAL APPLICATION
Interface with LCD and MSM5259GS
Display examples V'Jhen setting the 5 X 7 dots Examples of these bias voltages are shown in Figures
character font lline mode, 5 X 10 dots character 13, 14, 15, and 16. Basically, this can be done by
font 1line mode, and 5 X 7 dots character font dividing the voltage of the resistors as shown in
2line mode through instructions are shown in Figures 4 and 5. If the value of resistor R is made
Figures 10, 11, and 12, respectively. larger to reduce system power consumption, the
When the 5 X 7 dots character font is set in the LCD operating margin decreases and the LCD drive
1line display mode, the COM signals COM9 to To prevent this, a bypass condenser is serially
COM 16 are output for extinguishing. connected to the resistor to lower voltage division
Likewise, when the 5 X 10 dots character font impedance caused by the splitting of resistors
(l-line is set, the COM signals COM12 to COM16 as shown in Figures 15 and 16.
are output for extinguishing. As the values of R, VR, and C vary according to
The display example shows a combination of 16 the LCD size used and VLCD (LCD drive voltage),
characters (32 characters for the 2line display mode) these values have to be determined through actual
and the LCD. When the number of MSM5259GSs experimentation in combination with the LCD.
are increased according to the increase in the number (Example set values:
of characters, it is possible to display a maximum R = 3.3 - 10 Kn, VR = 10 - 30 Kr2, and
of 80 characters. C = 0.0022 J.lF to 0.047 J.lF)
Besides, it is necessary to generate bias voltage Figure 17 shows an application circuit for the
required for LCD operation by splitting resistors MSM6222B01GS and MSM5259GS including a bias
outside the IC to input it to MSM6222B01GS and circuit.
MSM5259GS. The bias voltage has to maintain the following
potential relation:
VDD > VI > V 2 ~ '.13 > V4 > Vs
COMl
~
LCD
COM8 -
~ -........
SEGl 01 - - - - - - - 0 4 0
- - - - - - - SEG40
DO I- 011
MSM6222B01 GS MSM5259GS
CP I- CP
OF l LOAD OF 0020 0121
-{ I u
Figure 10
133
DOT MATRIX LCD CONTROLLER MSM6222B-01GS ...- - - - - - - - -
COMl
~
COMll
LCD
-.......,., -...,
SEGl _____________ SEG40 01 --------040
I I U
I j
Figure 11
COMl
COM7
~
COM8
COM9
) --
... -
--
COM15
--
COM16 -- --
_________ 040
SEG1~SEG40 01
CP I - - - CP
OF L LOAD OF 0020 0121
l l
J
u
Figure 12
134
----------11. DOT MATRIX LCD CONTROLLER MSM6222B-01GS.
Bias voltage circuit (1line display mode) Bias voltage circuit (2line display mode)
-
Voo ~----~~--~--
VOO
~ R
Vi
R
V2
MSM6222B-01 GS MSM6222 B01GS ~
V3 B VLCO
V3
V4
R
Vs V4
VR R ~VR
Vs ....
Figure 13 Figure 14
Bias voltage circuit (1line display mode) Bias voltage circuit (2line display mode)
Voo
Voo ~----~~---.--~------
V2
MSM6222B-01GS MSM6222B01 GS
V3
Vs
Figure 15 Figure 16
135
f!
...
w
en '/ C
Z l>
"C
~
0
-I
~
0'
1C 0 ~
0'
s:
::J :t>
-I
\ ~. JJ
?~
~
~
n
~~ ~~ ~. X
r
n
c
n
COM1 -16 SEG1 -40 01 -040 01 -040 01 -040
0
:2
MSM5259GS MSM5259GS MSM5259GS -I
JJ
~
DO 011 0040 011 0040 011 0040
-.--- CP 0020 r-- CP 0020 r--- CP
0020
0
r
r--
LOAD
OF
0121 tJ r-- LOAD
.--- OF
0121
.--
...-
LOAD
OF
0121
r
m
JJ
VOO VSS V2 V,l VEE Ivoo VSS V2 V) VEE VOO VSS V 2 V) VEE
"T1
cO'
s:
C/)
t:
iil
CP ~
s:
m
~
MSM6222B-01 GS L
OF
\t-- N
N
VOO
\\ N
OJ
6
~
C)
GNO C/)
V,
V2 I
V)
V4
Vs ':"
( I
('
~+.f- HI
C C C C
/1
H~ H~ II
' \ II
1/
"
-vv v v "'I';
A A A A A VA
() () 6
+5V -5V OV
OKI semiconductor
MSM6240GS
DOT MATRIX LCD CONTROLLER
GENERAL DESCRIPTION
The OKI MSM6240GS is a CMOS Si-gate LSI to control large size dot matrix LCD in characters and graphics_
Three kinds of display modes are provided; Semi-graphic mode, Full-graphic mode and Character mode.
FEATURES
Number of characters: 32,40,64 and 80/line Applicable LCD duty: 1/32, 1/48,1/64,1/72,1/80,
Number of lines: 4 X 2, 6 X 2, 8 X 2 and 16 X 2 1/96, ;/108, 1/128, 1/144
Font composition (vertical): 8, 12, 18 and 20; here- Low power CMOS Silicon gate technology
inafter called VP (vertical pitch) Single +5V power supply.
Font composition (horizontal): 5,6, 7, 8, 10, 12, 14
and 16; herei nafter called HP (horizontal pitch)
60 pin plastic flag package (bent lead)
PIN CONFIGURATION
(Top View) 60 Lead Flag Package
s: s: s: s: s: s: s: s: s: s: s: r- r- r- r- r-
l>
;; l' :t J' ? ? 1: ? ~ ~ J> 1: ? ~ ~ J>
MAil GNO
Do 0 C5"
01 C5 1
02 5"
OJ 51
04 52
vOO SJ
O~ OEEN
Db XT
07 XT
MCE CL
002 HS o
E02 HS I
001 HSl
m z r- ....
!;)
~ ~
." CD 0
~
." 0 (") C C
0 (") :IJ
~ :;; ~
m
~ iii ~
s: in VI Z ~
-< Z Z ;:j .... Z Z
137
r:!
...w to
(Xl
r o
o
("') o
OlEN OEEN ~O) ED) 0;)2 E02 CP
-i
"o :s:
DATA 8bit 8bit Cursor
C)
l>
-i
JJ
JJ
OO~07 Register Latch PIS Control
l> X
Control LIP :s: r
("')
FRP
o
FRM ("')
REN
BUSY
o
Z
OAEN -i
MCE
Attribute JJ
CHBL
UOEN
Control o
r
r
UOBL m
CSEN JJ
TEST1
:s:
VJ
TEST2 Test
Blink
Counter
:s:
0)
Control N
,J::I.
C
~~
C)
VJ
CL ~ CLR
Address 3 State MAo-MA))
Counter Buffer LAo~LA4
Temporary
XT Address
XT Counter
OPERATING RANGE
INPUT CHARACTERISTICS
10%, Ta = 25C)
(VOO = 5V
MAo - MAll,
"H" Output current 10H VOH = 2.8V -500 - - J.1A LAo - LA4, 001,
EOl, 002, E02,
"L" Output current 10L VOL = Oo4V 2.1 - - mA CP, BUSY, FRM,
FRP, MCE, LIP
139
DOT MATRIX LCD CONTROLLER MSM6240GS. - - - - - - - - - - -
POWER CONSUMPTION
(Ta = 2SoC)
11
SWITCH ING CHARACTER ISTICS
(VDD = sv 10%)
i1 b
10%
~ 1
/ "--
tr tf
Parameter Symbol Load condition MIN TYP MAX Unit Applicable terminal
Clock pulse tr CL = 150PF - - 100 ns
All output terminals
Rise and fall time tf CL = 150PF - - 100 ns
Parameter
Oscillation frequency
140
- - - - - - - - - - - . DOT MATRIX LCD CONTROLLER MSM6240GS.
Refresh cycle
(CL BOpF)
Drawing cycle
DIEN
... O.BV 2.4V I
tA d 2
2.4V 2.4V "l
display
address display address
O.BV O.BV
bus floating
(CL = 150pF)
141
DOT MATRIX LCD CONTROLLER MSM6240GS. - - - - - - - - - - -
J
11
BUSY
MAil
l I
D7 -D o
CP
4.2V
0.8V
4.2V
0.8V
142
- - - - - - - - - - . DOT MATRIX LCD CONTROLLER MSM6240GS.
BUSY
D,-D u
CP
(CL 80pF)
143
DOT MATRIX LCD CONTROLLER MSM6240GS. - - - - - - - - - - -
PIN DESCRIPTION
11 LIP
FRP
0
-
0
Latch pulse for one line
(Frame pulse)
Signal input to Y driver
- (Frame)
FRM 0
Frame inversion signal
(Shift clock pulse)
CP 0 Shift clock pulse for X driver
- "READY" SIGNAL
BUSY 0
L druing suspension of serial transfer
(Display enable)
DIE~J I
Display enable signal; active H
(Chip Enable)
MCE 0 Memory chip enable control signal
(Clear)
a. I
Clear terminal
XT I (X'tal OSC)
- -
XT 0 Crystal oscillation
VOD +5V
GND OV
OEEN I Odd-number even-number data enable; active H
144
- - - - - - - - - - - . DOT MATRIX LCD CONTROLLER MSM6240GS.
Terminal
name 1/0/2 Function
HSo
(Horizontal select)
5
HS 2
I
HP programming
145
DOT MATRIX LCD CONTROLLER MSM6240GS. - - - - - - - - - - -
FUNCTIONAL DESCRIPTION
1. Selection of HP
L L L 5 dot
L L H 6
L H L 7
L H H 8
H L L 10
H L H 12
H H L 14
H H H 16
(Example) (Example)
HP = 8 (HS2 HS 1 HS o :011) HP = 5 (HS 2 HSI HSo:OOO)
CNH = 5
Do Do DATA
0 0 0 -0 E 0 0 o C
0 0 o 0
0 0 :1 00 0 0 0 3 F
0 0 1 1 0 o 4
0 0 0 0 0 1 F 0 o 4
0 0 1 1
Not displayed
0 o 4
0 0 1 1 0 0 1 8
o 0 o 0
:3:do, ~ ~--H-P--=r------ 5 x 8 font
....._sp-a-ce-_ _ _C_N_H_ _ ~-l 8 X 8 font
1
HP
HP = CNH No space
*The data Ds - D, are invalid for display.
HP < CNH No space
146
- - - - - - - - - - . DOT MATRIX LCD CONTROLLER MSM6240GS.
147
- DOT MATRIX LCD CONTROLLER . MSM6240GS------------
*Number of lines on above table is half of the actual number of lines on the LCD panel.
When all of S3 - So are set at high level (which means HP is 16 and number of characters/line is 80), the display on
the LCD panel becomes as shown below because the capacity of the display RAM overflows.
HP = 8
{ Number of lines = 12
VP = 16
Number of characters/line = 80
4. Attribute Function
This function is determined by the data of the
external attribute RAM. The attribute function
per font is available.
148
- - - - - - - - - - - . DOT MATRIX LCD CONTROLLER MSM6240GS.
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 - Cursor
Blink
The blink cycle is 640 ms (FRP = 50 Hz) and is
cynchronized to FRM signal.
FRM
~ ________ ________r--
~"\
640 ms
Display inversion
Inversion
REN = L REN = H
149
DOT MATRIX LCD CONTROLLER MSM6240GS. - - - - - - - - - - -
11
CHARACTER GENERATOR R:l~1
Out
Upper Panel
Lower Panel
p"-----
The character code is programmed in the Display The MSM6240GS is capable of controlling 4,096
RAM in 8-bit configuration. The data of Display characters maximum, however, this capacity is
RAM is converted to the data necessary to display affected, as is shown on the Sec. 13, by the LCD
a character on the LCD, and is input to Do -- 0 7 , drivers speed.
display data input, of the MSM6240GS.
150
- - - - - - - - - - - . DOT MATRIX LCD CONTROLLER MSM6240GS.
VP = 8 VP = 12
r' L L L rt L L L L
L L H L L L H
L H L L L H L
L H H L L H H
H L L L H L L
H L H L H L H
H H L L H H L
H H H L H H H
H L L L
H L L H
H L H L
'- H L H H
VP = 18 VP = 20
LA4 LA3 LA2 LAl LAo LA4 LA3 LA2 LAl LAo
r+ L L L L L r" L L L L L
L L L L H L L L L H
L L L H L L L L H L
L L L H H L L L H H
L L H L L L L H L L
L L H L H L L H L H
L L H H L L L H H L
L L H H H L L H H H
L H L L L L H L L L
L H L L H L H L L H
L H L H L L H L H L
L H L H H L H L H H
L H H L L L H H L L
L H H L H L H H L H
L H H H L L H H H L
L H H H H L H H H H
'- H L L L L H L L L L
H L L L H
H L L H L
'-- H L L H H
151
DOT MATRIX LCD CONTROLLER MSM6240GS . - - - - - - - - - - -
11 1
2
3
80
64
40
16
16
16
000 -4FF (H)
000 -3FF (H)
000 - 27F (H)
4 32 16 000 - 1 FF (H)
(Note) Number of lines on above table is half of the actual number of lines on the LCD panel.
Memory address MAll' MAIO I MA9 I MAs' MA, I MA6 i MAs ,MA4 'MA3 : MA2 ,MAl 'MAo
Start address L ,
I
L I L I L I L :, L I L ,
I
L I L I L ,
I
L I L
End address L ,
I
L
I
H ,
I
H
I
H , L ,
I
H
I
H
I
H
I
H
I
H
I
H
Start address H ,
I
I
,
I I
I
I
L
I
, L
I
L
I
,
I
L
I
,
I
L
, I
L
I
,
I
L
I
,
I
L
L L L I
,
I
,, I
, I
,
End address H I' L ,I H
I
H H
: L
I
I
H
I
I H
I
H
i
I
H
I
H ,
I
H
152
DOT MATRIX LCD CONTROLLER MSM6240GS.
Set HP at 8 or less I
No.1 In the case of 80 characters/line (Number of lines: 161ines max.)
The table above shows the memory address to the LCD panel.
It only shows the address to the upper part of the LCD panel. Whether it be the upper or lower will be determined
by the H/L condition of MAll.
The table above shows the memory address to the LCD panel.
It only shows the address to the upper part of the LCD panel. Whether it be the upper or lower will be determined
by the H/L condition of MAll.
153
DOT MATRIX LCD CONTROLLER MSM6240GS . - - - - - - - - - -
The table above shows the memory address to the LCD panel.
It only shows the address to the upper part of the LCD panet. Whether it be the upper or lower will be determined
by the H/L condition of MAll.
The table above shows the memory address to the LCD panel.
It only shows the address to the upper part of the LCD panel. Whether it be the upper or lower will be determined
by the H/L condition of MAll'
154
- - - - - - - - - - - . DOT MATRIX LCD CONTROLLER MSM6240GS.
ISetHPat10- 1s l
NO.5 In the case of 80 characters/line (Number of lines: 12 lines max.)
The table above shows the memory address to the LCD panel.
It only shows the address to the upper part of the LCD panel. Whether it be the upper or lower will be determined
by the H/L condition of MAll.
The table above shows the memory address to the LCD panel.
It only shows the address to the upper part of the LCD panel. Whether it be the upper or lower will be determined
by the H/L condition of MAll'
155
DOT MATRIX LCD CONTROLLER MSM6240GS. - - - - - - - - - - -
The table above shows the memoray address to the LCD panel.
It only shows the address to the upper part of the LCD panel. Whether it be the upper or lower will be determined
by the H/L condition of MAll.
The table above shows the memory address to the LCD panel.
It only shows the address to the upper part of the LCD panel. Whether it be the upper or lower will be determined
by the H/ L condition of MA 11.
156
- - - - - - - - - - - . DOT MATRIX LCD CONTROLLER' MSM6240GS.
I r~------Y
Out
DISPLAY
RAM
'" ,/
11 11 LA o -LA 4
~ MAo-MAII
IMAIII MA91 MAR I MA7 I MAo I LAl I LAI I LAo I MAs I MA41 MA31 MAl (MAl I MAo I
0000
0040
0080
003F
007F
OOBF T
Upper
surface
8K byte
,LJ ~L
, ...
t
,~
1FCO 1FFF
2000 203F
2040 207F
2080 20BF
Lower
surface
8K byte
,'- ~'-
157
DOT MATRIX LCD CONTROLLER MSM6240GS .---.-------~
11
external RAM by half.
In this case, the data is sent to 00 1 (upper part)
8. ODD/EVEN Number Data Processing and 00 2 (lower part).
CP
1st line stop 2nd line stop 3rd line stop lst line stop
I I I I I I I I I I
Memory address =:JJ..J...1.ll-:::::a:::::::x:t::.-'~.:.~::: x:crr.j~=x:x:xxxx: :'.::Y:C:J.
LIP ..Il ~ If 'l--fr" !l-
FRP id
I ,
~I I rf---1 :I L
FRM
: : : I If ~
I I I I I
I I I ,
X driver
j ~ 1st I,"ne X 2nd I,"ne v..---,f-v
~------(l-~-"!'!!''':'::'':;=-----1'I'-....!.!.~~---f'---JJ-A N th line
I
pilline
Y driver _y....:.l_ _ _ _---J1 I : If i
~IY-2~-------------J: ~/r'-------~I-- I
I I
_'y~N~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___{fl~ ~
_y~I~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~%~------~r---
158
- - - - - - - - - - - . DOT MATRIX LCD CONTROLLER MSM6240GS.
XT
et------f s
XT
R
Power ON reset
No. of
1\ characters 32 40 64 80
"
Duty
1/128 4.1-5.7 4.9-6.9 7.4 -10.3 9.0 -12.6
1/96 3.1 -4.3 3.7 -5.2 5.5- 7.7 6.8- 9.5
1/64 2.0-2.9 2.5 -3.5 3.7- 5.18 4.5- 6.3
1/48 1.5-2.1 1.8 -2.5 2.8- 3.9 3.4 - 4.8
HP = 7, FRP = 507'"' 70 Hz
~Duty
No. of
characters 32 40 64 80
1/128
1/96
"" 3.6-5.0
2.7 -3.8
4.3 -6.0
3.2 -4.5
6.5 -9.1
4.8-6.7
7.9 -11.1
5.9- 8.3
1/64 1.7-2.5 2.2 -3.1 3.2-4.5 3.9- 5.5
1/48 1.3 -1.8 1.6-2.2 2.5-3.5 3.0- 4.2
159
DOT MATRIX LCD CONTROLLER MSM6240GS . - - - - - - - - - - -
HP = 6. FRP = 50 ...... 70 Hz
1\ Duty
No. of
characters 32 40 64 80
1/128
1/96
'" 3.1 ...... 4.3
2.3 ...... 3.2
3.7 ...... 5.2
2.8 ...... 3.9
5.6 -7.8
4.1-5.7
6.8 ...... 9.5
5.1 ...... 7.1
1/64 1.5 ...... 2.1 1.9 ...... 2.7 2.8 ...... 3.9 3.4 ...... 4.8
11 1/48 1.1 ...... 1.5 1.4 ...... 2.0 2.1 -2.9 2.6 ...... 3.6
HP = 5. FRP = 50 ...... 70 Hz
~
No. of
characters 32 40 64 80
Duty '\
1/128 2.6 ...... 3.6 3.1 ...... 4.3 4.6 -6.4 5.6 ...... 7.8
1/96 1.9 ...... 2.7 2.3 -3.2 3.4 ...... 4.8 4.3 ...... 6.0
1/64 1.3-1.8 1.6 ...... 2.2 2.3 -3.2 2.8 ...... 3.9
1/48 0.9 ...... 1.3 1.1 ...... 1.5 1.8 ...... 2.5 2.1 ...... 2.9
1\ Duty
No. of
characters
'\
32 40 64 80
1/128 8.2 ...... 11.5 9.8 ...... 13.7 14.7 ...... 20.6 18.0 -25.2
1/96 6.1 ...... 8.5 7.4 ...... 10.4 11.1 - 15.5 13.5 ...... 18.9
1/64 4.1 ...... 5.7 4.9 ...... 6.9 7.4 - "10.3 9.0 ...... 12.6
1/48 3.1 ...... 4.3 3.7 ...... 5.2 5.5 - 7.7 6.8 ...... 9.5
The value on above tables are affected by the For example. the fosc is limited as follows when
maximum frequency of LCD driver's shift clock MSM5260GS. whose maximum frequency of shift
input and an maximum frequency of fos c . pulse is 3.3 MHz. is connected to MSM6240GS.
The relation between fosc and shift clock is as When ODD/EVEN data processing is proceeded
follows. fosc ~ 10 MHz
When ODD/EVEN data processing is proceeded When ODD/EVEN data processing is not pro-
CP = fosc/4 ceeded
When ODD/EVEN data processing is not pro- fosc ~ 6.6 MHz
ceeded
CP = fosc/2
160
- - - - - - - - - - - . DOT MATRIX LCD CONTROLLER MSM6240GS.
LIP
FRP
L...--4-___ FRM
L=============~~===ti~======jt~========~---cp
161
OKI semiconductor
MSM6255GS
DOT MATRIX LCD CONTROLLER
GENERAL DESCRIPTION
III The OKI MSM6255GS is a CMOS Si-gate LSI designed for use in controlling large size of DOT MATRIX LCD panels
in characters and graphics,
FEATURES
Display control capacity Scrolling and paging
16
Graphic mode: 512,000 dots (2 bytes) Display system: AC inversion at each frame
. Memory address MA?6"'" MA1S Data output (upper and lower display outputs)
- Character mode: 65,536 characters (2 bytes) 4-bit parallel output, 2-bit parallel output
Display address MAo"'" MA15 1-bit serial output
Direct interface with 8085 or Z80 CPU Crystal oscillation
Duty: 1/2 to 1/256 selectable Low C-MOS Silicon gate process
Attribute Single +5V power supply
Screen clear 80-pin flat package
- Cursor ON/OFF/blink
PIN CONFIGURATION
Xl ADF
Xl
VSS
TEST1
0 DISN
BUSV
CHq,
TESl2 UD"
DiV UD,
MAB UD,
MAI4 UDo
MAIJ VDD
MAil LDJ
MAil LD,
MAIO LD,
MA.,
MA.
MA,
LOu
FRMB
CLP
MA., CEI'>
.;; ; .;. .t' <t <i <t <t <t <t <t <t J
.; ,f .i .;; ; .; ,f' <t <i "- "-
ex: :::;
::; ::; ::; ::; ::;::;
162
OJ
r-
o
n
RD - - - - - - - - ,
WR - - - - - - - ,
"5>c
G')
CS ::0
l>
DBo S
S
DB,
Instruction
_r1'!l!s!.eL _____ _
~
.,-
R/W control
MAo
:;;e
.;::J
~
MA IS
1-0
RES - - c
ADF
o-i
S
l>
-i
::0
II lAo X
S r-
~-------DIEN
A I5
n
c
:;~::;s ==> Rto RA.l
n
o
2-bit parallel 2:
output -i
-4-bi;-p-;;a~I---~UDO-UD3 ::0
~U}I?':!.t_______ LDo-LD.l or-
8 bit parallel/ -CLP
senal r-
TImIng generator -CEq, m
circuit for CH ::0
PS and Load
II jRpO
XT R~
S
_ FRP en
DIV
J.
:I:
>- ~
Vl..J ~
U :J - FRMB 0)
(I]
N
U1
U1
G')
... en
al
W
DOT MATRIX LCD CONTROLLER MSM6255GS ....- - - - - - - - - -
11 OPERATING RANGE
INPUT CHARACTERISTICS
(VDD = 5V 5%, Ta = -20 - 85C)
"H" input voltage VIH 2.4 - - V DBo - DB 7 , CS, RD, WR, Ao - AIS,
"L" input voltage - - V DIEN,ADF, RDo -RD 7
VIL 0.7
"H" input voltage VIH 4.5 - - V RES,DIV, XT
"L" input voltage VIL - - 1.0 V
"H" input voltage IIH - - 1 pA DBo"" DB 7 , CS, RD, WR Ao "" AIS.
"L" input voltage - - -1 DIEN. ADF RDo - RD 7 RES. DIV
IlL pA
"H" input voltage IIH - - 250 pA TEST1, TEST2
"L" input voltage IlL - - -1 pA
164
- - - - - - - - - - - - DOT MATRIX LCD CONTROLLER MSM6255GS-
CURRENT CONSUMPTION
(Voo = 5V 5%, Ta = -20 - 85C)
Note: TESTl and TEST2 are open, and other inputs are either VOO or GNO.
SWITCHING CHARACTERISTICS
/ 1\ [0.2 VOO
- ,I-
Parameters Symbol Load condition MIN TYP MAX Unit Applicable terminals
Rising time tr 60 pF - - 100 ns
All output terminals
Falling time tf 60 pF , - - 100 ns
165
DOT MATRIX LCD CONTROLLER MSM6255GS ....- - - - - - - - - -
- -
11
Clock rising/falling time tcr/ tcf 20 ns
Character clock delay time tCH - - 200 ns
Memory address clock delay time tMA - - 100 ns
Memory address disable delay time tAD1 - - 40 ns
Memory address enable delay time tAD2 - - 40 ns
CPU address delay time tAD3 - - 100 ns
Refresh address delay time tAD4 - - 100 ns
Reset "H" level pulse width tRES 1 - - /.IS
tcp
XT
External
clock
CHcp
MAo-MAlS Floating
RAo-RA3
tAD2
DIEN \~ }
l-tREs~
166
- - - - - - - - - - - . - DOT MATRIX LCD CONTROLLER MSM6255GS-
AH
r----
Ao, CS
=x ~ tew
:~
/
WR,RD \.- ,k'
tDH
DBO"-'DB7
(WRITE) ~: :K
DBo"'DB7
(READ)
7 f-
~ Ie-
VALID
:>-
tACC tOH
167
- DOT MATRIX LCD CONTROLLER MSM6255GS - - - - - - - - - - - - -
11 - -
Latch signal "H" time tLiP 1.46 ns
Chip enable clock delay time tCE - - 200 ns
Chip enable clock "H" time tCEI/> 730 - - ns
Ready signal delay time tB - - 200 ns
Ready signal "H" time tBUSY 5.11 - - p.s
Frame signal delay time tFRP 2tCHI/> - 2tCHI/> +200 ns
Alternating frame signal delay time tFR - - 200 ns
CLP
UDO"'UD3-------+~
LD o"'LD 3 ______-+-J
CHI/>
LIP
CEI/>
BUSY
tB tB
LIP
FRP
FRMB
tFR tFR
168
- - - - - - - - - - - . DOT MATRIX LCD CONTROLLER MSM6255GS.
CHc/>
RDO-RD7
169
DOT MATRIX LCD CONTROLLER MSM6255GS --.- - - - - - - - -
PIN DESCRIPTION
11 22
23
24
25
A lS
FRP
LIP
CE>
0
0
0
Frame signal .... Synchronization of display
Display data latch signal
Chip enable clock for LCD segment driver.
26 CLP a Display data shift clock
27 FRMB 0- AC signal
28 LDo
S
31
S 0- Display data parallel output for lower side.
LD3
32 VDD Supply voltage
33 UDo
) S a Display data parallel output, Upper display 4bit output
(001, ED1, 002 and ED2 outputs)
36 UD3
37 CH> 0" Character clock
45 DBo
S
52
S
DB,
I/O/Z 8bit data bus ... Common terminal for three state I/O.
53 ROo
ROM/RAM data input ... Dot pattern data for the
S S I
character generator
60 RD,
61 RAo
Raster address output.
S
64
S O/Z
*This output is not used in the graphic mode.
RA3
65 XT I
X'tal osc .... When an external clock is used by setting
- 01 V to "L", feeds it to XT.
66 XT a
67 Vss Ground pin.
"H": EXT clock.
70 DIV I
"L": Selfexcided oscillation
170
-----------11. DOT MATRIX LCD CONTROLLER MSM6255GS.
FUNCTIONAL DESCRIPTION
Instruction
Data bit
CS Ao register Register Register name READ WRITE
3 2 1 0 7 6 5 4 3 2 1 0
H X X X X X Invalid - -
L H X X X X IR Instruction register 0 0 X X X X
Mode control
L L L L L L MOR
register
X 0 X
Character pitch
L L L L L H PR
register
0 0 X
Horizontal character
L L L L H L HNR
number register
0 0 X
Instruction register
The instruction register is a register for specifying the address of the data register which is accessed.
This register is cleared when ~ input is "L".
171
DOT MATRIX LCD CONTROLLER MSM6255GS .
.------------
The mode control register is specified by writing "OOH" in the instruction register.
06 05 04 03 O2 0 1 Do Output system
L L l-bit serial
H L 2-bit parallel
L Character display
X H
4-bit parallel
X H
H/L H/L H/L H/L
L L l-bit serial
H L 2-bit parallel
H Graphics
X H
4-bit parallel
X H
.JL
.=
]!
e
--
Qi
~~
Q)
E
.;; .. u. ..
u. :0 u.
>u. <C <CQ)
...0. c.",
:c ......
W
.JL 00 0 ..!!!O
"'--
.= :;2
iii UO u
~
:J
0.--
.~ 2
00 N
:C:C
~..:.
0
0
~
L.,..-l
LH' Display ON
L: Display OFF
05 04
L L Cursor OFF
L H Cursor OFF
H L Cursor ON
H H Cursor blink
H: 16 frames
Half of blinking cycle
L: 32 f rames )
172
-----------11. DOT MATRIX LCD CONTROLLER MSM6255GS.
Register Ao 07 I 06 I Os I 04 03 02 1 01 I 00
Instruction register H L I L I L I L L L T L 1 H
Ao 07 06 I 05 I 04 I 03 I 02 I 01 I 00
Instruction register H L L I L I L I L I L I H I L
Character number register L L (HN -1)
where HN = 2 -128.
Register Ao 07
I 06
I 05 I 04 I 03 I 02 -, 01 I 00
I nstruction register H L I L I L I L I L I L I H I H
Time division register L (NX - 11
Nx = 2 -256
Register Ao 07
I 06 I 05 I 04 03 I O2 I 01 I 00
Instruction register H L I L I L I L L
I H
1 L
1 L
Cursor position register L (Cpu -11 (Cpd - 11
The cursor is displayed on the lines from Cpu to The cursor is not displayed in graphic mode.
Cpd in the character display mode. The length of The relation between the cursor and Vp is as
the cursor in the horizontal direction is equal to follows.
the character pitch in the horizontal direction.
Hp.
173
- DOT MATRIX LCD CONTROLLER MSM6255GS - . - - - - - - - - - - -
o O--t---t--+--+--+--+-+- o
3 3--r--t-;--+--r-~~- 3
4 4---+-+--+-+--+-+--+-- 4 ---fH~R-TH-+R-~~~~--
5 5---r--tr-~-+-+--+-+-- 5--~~~B-~~~H-eT-
6 6-~-+R-~-A~~~~~- 6---r--t--+--+-+--+-t--
7 7---tt:Ji-fH--tili-fH--fH1--fH--fR~ 7---+--1----f---1----f---1---f---
Register Ao 07 I 0 I 05 I 0 I 0 3 I Dz I 0 1 I Do
6 4
Instruction register H L IL I L IL I L I H I L I H
Display start address register (lower byte) L Start address (lower)
Register Ao 07 I 0 6 I 05 I 0 4 I 0 3 I Oz. I 0 I Do 1
Instruction register H L IL I L IL I L I H IH I L
Display start address register (upper byte) L Start address (upper)
The display start address shows an address of The start address is composed of upper and
the RAM which stores data displayed at the left lower 8 bits (16 bits in total I.
end and the most upper position.
Register Ao 07 I 0 6 I 05 I 0 4 I 0 3 I Dz I 0 1 I Do
Instruction register H L I L I L I L IL H I I H I H
Cursor address register (lower byte) L Cursor address (lower!
Register Ao 07 I 0 6 I 05 I 0 4 I 0 3 I Dz I 0 1 I Do
Instruction register H L IL I L IL IH I L IL IL
Cursor address register (upper byte) L Cursor address (upper)
174
- - - - - - - - - - - - DOT MATRIX LCD CONTROLLER MSM6255GS-
2. LCD Display
000 001
00.000_01
I
01:1_000.0 I
~ gg:~~~:gl 1
> 00.000.01
DI:1. a 00. a./" cpu I
'-P--- -r-
::~ :::~ :I.c- Cpd
----f-- ---
~r-----l--
l - - - - ---1----
1
> 8: I I
2 I
I 1
I I
'----- - -t--- ----~-----
I 1
I I
I I
I
--- ------- ---I--
I
OJ I I
>!---- - I - - - - - - - - r - - -
I 1
1 I
I I
1 I
Table 2 Legend
175
DOT MATRIX LCD CONTROLLER MSM6255GS ....- - - - - - - - - -
HSB LSB
/1 word
v------.
0000 I 0001 I I 004E
~
I 004F I
0050 I 0051 I I 009E I 009F I
UPJJe r
+
lEFO 11EFI I 11F3E I lF3F I
1 F40 11 F41 I J lF8E I lF8F I
lF90 11F91 I 11FDE I lFDF I
Lowt~1
3E30 13E31 I
{
0000 0001 004E 004F
010
011
Line 1
100
101
110
111
000
0000
0050
0001
0051
-- 004E
009E
004F
009F
! l
0370 0371
-- 03BE 03BF
u,,,, fOO
r111
000
0370
03CO
0371
03Cl
--
-- 03BE
040E
03BF
040F
Line 13 ~
Low
line 24
177
DOT MATRIX LCD CONTROLLER MSM6255GS ...- - - - - - - - - -
8. Output Mode
Three kinds of modes, 1 bit serial, 2bit parallel
and 4 bit parallel, are available as output modes.
Data flow of each mode is shown below.
Data shift
Segment UDo
driver
Upper
LCD panel
Lower
Segment
driver
Data shift
Upper
------------------~~~~
Lower
i I
r- - oJ. .....
I ~4-------
178
----------11. DOT MATRIX LCD CONTROLLER MSM6255GS.
CEcp
Upper
LCD panel
Lower
179
!!
...
co
o
C
o~
s:
~
fs J1J1I1JUUl..flI-_ ::0
X
CHr/>~ _ _ _ r-
(')
C
M~~A1S ENON EN~I ~=~~~~_~_A_N~_S_~_M~ILs_T_A_~_I~I_s~T_A_M_+l~I_ _~_ _~_ _~_ _~_ _~ (')
Suspension of data o
transfer z
~
::0
CLP ------ -- or-
-------- r-
m
UOo I I I I I I I 10710610514131211100 1071615141312111 061 07\6151413121110J II ::0
Note: STAN: First memory address of one horizontalline.in the upper side
STAM: First memory address of one horizontal line in the lower side
EN DN: Last memory address of one horizontal line in the upper side
ENDM: Last memory address of one horizontal line in the lower side
I Suspension of data
/--!!Jlnsfer
-J
CLP
LO o I 04 DO I 04 Do 04 Do 04 I Do
,. ENOM-l data
I ENOM data STAM data STAM+l
1 data
l
CD FRP X (HN + 8) X Hp X VQ X 2 9.856
@ FRP X (HN + 8) X VQ X 4 2.464
H
CD FRP X (HN + 8) X Vp X VQ 4.&28
Note: (1) Table 3 shows a calculation example assuming that FRP = 70 Hz, HN = 80, Hp = 8 and VQ = 100, how
ever, the example of Hp = 4 - 7 in 4-bit parallel is not included.
(2) Output mode CD Hp = 4 """ 7 in l-bit serial, 2-bit parallel and 4-bit parallel
Output mode @ : Hp = 8 in 4-bit parallel
Noto: Table 4 shows an calculation example assuming that FRP = 70 Hz, HN = 80, Hp = 8 and VQ = 100.
183
DOT MATRIX LCD CONTROLLER MSM6255GS . - - - - - - - - - -
oiV
XT
(oW = 1)
fs functions as a dot clock in LCOC and the dot counter inside the IC is counted up at the tailing edge of f s .
The dot counter operates in N number system and its signals are output as CH</>.
(Refer to time charts Fig. 7-9 and Fig. 14.1
15. Access to the Display RAM BUSY is high), the display on the screen does
not flicker.
In writing/reading the data to/from the CPU, 01 EN
should be low level. By setting 01 EN signal at low Note: This method is effective when the size of
level, the address from the CPU are output from screen is small. In the case of big size
MAo-MAts, and this enables the access to the screen, 640 x 200 dot, 1-character needs
display RAM. approx. 1.6ps. So, in this case, the period
There are 3 method about accessing display RAM when BUSY is at high level is 11.2ps,
from the CPU. which is impossible to write a lot of data.
184
- - - - - - - - - - - - . DOT MATRIX LCD CONTROLLER MSM6255GS.
DIEN
display
RAM
OUT
legend
TC Period wihen the address bus is MAo-MAts output address to the upper side
occupied by CPU when DIEN is high and CHI/> is low_
Period when the LCDC fetches To perform synchronized access method, the
the refreshed data timing between DIEN and CHI/> should be as
tRAM Refresh address delay time + described in Figure 10.
memory access time
tUDS Upper side data set-up time
tUDH Upper side data hold time
M-WR
M-RD
V-RAM
SELECT--------~
DIEN
READY
DATA LATCH
Display RAM must meet following require- should be synchronized so that the write pulse
ment. should occur during the period of TC. In read-
ing the pattern data from the CPU, the data of
TL>tRAM + tUDS
display RAM should be talched first.
In writing data into the display RAM, LCDC Figure 11 shows the controlling circuit.
185
DOT MATRIX LCD CONTROLLER" MSM6255GS ...- - - - - - - - - -
16. DIEN
DIEN has to be generated when the display RAM is
accessed by Synchronized access method described
in 15-(3).
XT
[)o-- DIEN
CHI/>
=Er D Q
17. ScrollPaging
Scroll"paging is enabled by setting the display start
address to the scroll address register.
186
----------__ DOT MATRIX LCD CONTROLLER MSM6255GS-
MSM6255GS
I""r- ",....
8085 -
~ - ~
WR
- '-- -
WR ~r- ~ RD
AD
101M
~r- r- r- - Decoder - C
A -A., CS
ADo-AD7 U
bel
I--
ALE
HLDA
As-A 1S
LJ1 '--
-,
DBo-DB7
Ao-A 1S
"'~
MSM6255GS
280
'" f"
~ l- """\.. WR
-
~I-- I- '- RD
WR
RD
--
~f- f - I- r---c f-c
-
CS
IORQ A -A., Decoder
,
I-
0 0 -0 7 DB o -o8 7
I--
'--
Ao-A1S Ao-A 1S
jjj If-.
187
DOT MATRIX LCD CONTROLLER MSM6255GS ....- - - - - - - - - - - - - -
MSM6255GS
8086
11
*Minimum mode
MSM6255GS
6800
VMA
t----(1 CS
188
I I
r
I II I I I I
cs FD DR L MSM
L
~
1'-
~
i'-.J
B l~
=> DBo-DB7
.UDo
S
,
4 bit
5279GS l-
I--
f::
I--
~
n6~40H245
DIEN
UD3
CLP
.----
\ \
CEq)
I
V
~
V
RDO-RD7 LIP
Jr>
'---
WR
lID
Display
FRP
FRMB
MSM
5278GS
rLb
~
1----- - - - - - - - - - - -
RAM
MSM6255GS
l
It MAo
MA 1S
~ f--
~
~
0 r--
P
~
r--
I I r Ir~
or J
Decoder
I I 1
Ao-A 1S LDo....,.LD J
1 I
Ao-AIS 0
Figure 12 System configuration in graphic mode
...co
co
~
r!
-
U)
o
o
--- o
-f
3:
ill :r>
-f
~~;7~S~ "~
:0
CS RD WR X
UDo I
C")
S 4 bit
o
.. I
ROO
S
UD J
CLP
r---
II IJ C")
o
2:
-f
RD7 CE.p r----\ :0
CPU
Character
RAo
~ o
,,
generator I
S LIP
I
RAJ r-- 1---------- - - - - - m
MSM
:0
L::flS
FRP 5278GS
MSM6255GS
FRMB 3:
'\ (I)
OlEN
I- OlEN 3:
~I
en
>
N
WR
<l . I
DBo
S
DB7 11 U1
U1
C)
(I)
Ao~AIS
h
Decoder
~
STA+3
address
Memory N I Start address
LIP I
I
TliP I
I
I c
CE<p TCE4J o-.of
,- -,
s:
BUSY -----------~-- ______________ ~-----+--~~~~----------------~------------------------
-.of
FRP :c
CHcj>
X
r-
n
c
n
o
z
Figure 14 Time chart during suspension of shift clock -.of
:c
CH = Ts X Hp
or-
Condition: 4-bit parallel output mode r-
TlIP=2CH m
:c
1
HP = 5
TCE</> = CH
s:VJ
TBUSY = 7CH
~
C')
N
(J1
(J1
G)
... en
~
~
DOT MATRIX LCD CONTROLLER MSM6255GS ....- - - - - - - - - -
11
N
.,
c
:.::i
en
~
a:
u.
"tl
c:
(tJ
a.
a:
u.
a.-
::i
a
., ~
~
N
., c
:.::i
0
(1)
c
:.::i E
i=
It)
Q)
:;
Cl
'0 ii:
c .>I.
0
.;;; g
~ u
~ :&
(I)
., z
Q)
c c
:.::i :.::i
z
>-
Q.
a:
u.
'">
~
x
192
~~5":!!
~g:~~
:Tc.~
:gr-
a en -.. _
Q)
(I)
HC257 :Jcr(l)Cln
G
N' ~ ~ ~
-;:; ~g:3c.-i
Au ADR- S
1A 1YM'RD
ro~~
D XI
14 ADR-t4
ADR-13
.---------~13B 2Y M'WR Q)en "E." _
g m' ~ ce' 0
:~ :~::~
13
S.144MHz 0 ADR-12
ADR-II
, - - - - - - -....... ~ ~.~ @ 2:
1B
~ X,
ADR-IO 2B g ~ ;. ~ ~
~~:;l3- :D
+5V
50 pF ADR- 3A
80C85A
ADR- 4A 8.~~~ C')
.----------q SELIA) U;.:J rm C
0,
D II
ADR-,
ADR-6
ADR-S
HC138
cc.o-o
~-o:I:
~ II
0
g ~.
~ -i
_
~
ADR-4 mtoC. o
n' !:..:J
Q~~'-'
0 n (I) n
51 k ADR_, ~ en'::;'
ADR_I G,A ~. ~ g. o
RST-IN
0
ALE
ADR_o G,B
GI
VRAMSEl 3
(I)
0:;:
X o
5- -i
RESET
'"oo
SWi
l-
22
~J
-rE- o
c.
o c.
S
-i
+5V
~
B~' H~l~l
~
L-- HCT ~ :D
L- 245
c.
U;. X
~ -0
r-
L----iIA
Di'
-< n
D'BUS-, < o
D'BUS-I J)
n
D'BUS-o
~
o
"I
2:
lit-
WAr'-------------------~
+5V
-i
:D
o
r-
r-
IO.Mi'_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ .....J m
:D
ClK ClK
S
RSTOUT~-------------------------~~o_--~ en
READY READY RES S
C')
1.-_____________ eLK-OUT
N
C1I
C1I
C)
Figure 16-1 en
...
CD
W
~
...
f!
U)
~
C
0
+5V
-t
:s:
ADR.14 -n"'------1
-t
::c
ADR15
X
r-
HWR (")
0
M~~~ =111 I I 'I I1 (")
0
Z
VRAMSEL
-t
-HII+I--+----+----i'-----' ::c
rr----------~~:
READY
0
HC04 r-
r-
,~i
m
::c
111111. IA
+5V :s:
en
HCT374
DBO
:s:
C)
DB,
DB,
N
HC32 DB, UI
DB. UI
CLK-OUT IIII II II ~ o DB.
DB_
DB'
:g== ~
AOR- 2
G)
en
AOR- 3
ADR- 4
OE OlEN ADR- 5
AOR- 6
XT AOR- '
CS
RD
:g:=I!
ADA-II
ADR-U
WR AOA- ll
ADA-14
ADA-u
I!~:i I
DeUS-1
111/1111 ''111111
LCDC:~~~====~=-------------------------------------------------------------------~
:~::~==-------------------------------------------------------------------=========~J
Figure 16-2
~------------------------------------~ICs
DBO-DB, I \ \ IDB.-DB,
~lS125 I IBUSY
AD
ADO-RD,
rlo+ RAO-RA)
c
o
It;,! ($) -I
l
Z80 ~
L-+-
-I
MSM6255
I . . . . MSM516~RS :0
I
i2764
~
V (BKxBblt)
X
r
C")
C
:~~,.",
C")
'-+___ ~----II--- _ _~~-I-_ _ _~--+_--jl---..L___--,~_--I MAO-MA" o
Z
5V
-I
BiVI.J: :0
U= o
r
MA 12 - MA U r
m
A O-A12 '-"'T=T-"--"'-r"----' LS138
All-AU
'" :0
~
A.-A" I ) ) lAo-A" en
s:
REs' en
r--------------------_IRES N
1 U1
U1
C)
...
cg Figure 17
en
UI
~
OKI semiconductor
MSM6265GS
DOT MATRIX LCD CONTROLLER
GENERAL DESCRIPTION
The OKI MSM6265GS is CMOS Si-gate LSI to control large size dot matrix LCD in characters and graphics.
FEATURES
PIN CONFIGURATION
LOl
LJ HP1
LO .
HP,
UOo HPo
UO,
4BIOOEV
U'o2
NC
NC
6400
UO.I
MAl/>
VOO
Is
CHI/> OINH
BUSY OIV
EXBL TEST l
AOF TEST,
RS MONO
cs
AD
WR 0 VSS
Xl
XT
co co
o 0
co
o z
U co
0
0 U 0 (S 0 0
a: z a: a: a: a:
aa: 0
a:
0' : <i
a: a: a:
196
- - - - - - - - - - - . DOT MATRIX LCD CONTROLLER MSM6265GS.
BLOCK DIAGRAM
XT XT OIV F1ES
CH
j
I
MONO
197
f!
...co en
m -<
en C
~ 0
m ~
CRT/LCD switching signal
s: s:
OJ l>
..... r ~
-I
CRT controller
r- - 0
(')
JJ
X
~
r---I
6845
CRT screen "
C r
(')
C
l>
11
Ci) (')
Address
bus 1 1 JJ
l>
0
2:
M
s: ~
\ I=>
'--
,.... t---
P V-RAM II- JJ
~ X I'" 0
....,
~ r
CPU
- r-
I-
M
.1:"""" ---u
M
code
Data
r
m
JJ
s:en
)
- t--"1
L---
~
r-
-"-(
H
P
X
t-""'1,--
h
r---I
CG
ROM [ Driver circuit
J s:en
Data
bus
0
g
0
JJ
t
0
s:
f0
;;: JJ
j l - -
-
J I\)
en
(J1
Ci)
en
~ .. r:
JJ
l>
l> ~
0
)
Character data
J1
JJ
0
LCD driver
~~
V
-
2 .)
LCD controller
-
t--
f----
r----;
LCD
driver
W LCD panel
640 x 200
II ~
OPERATING RANGES
INPUT CHARACTERISTICS
(VDD= 5V 10%, Ta = -20 - 85C)
OUTPUT CHARACTERISTICS
(VDD = 5V 10%, Ta = -20 - 85C)
199
DOT MATRIX LCD CONTROLLER MSM6265GS . - - - - - - - - - - -
POWER CONSUMPTION
ITa = 25C)
Note: TEST1 and TEST2 are open, and other inputs are either VDD or GND level.
SWITCHING CHARACTERISTICS
(VDD = 5V 10%, Ta = -20 to 85C)
80% r ~
20"10 ~
I 1\
-t-
~ f-- tr
- f--tf
200
- - - - - - - - - - - . DOT MATRIX LCD CONTROLLER MSM6265GS.
PIN DESCRIPTION
Pin No, Pin name I/O/Z Function
1 WIDE I Expansion mode when "H", Normal when "L",
2 MAl3
Address output to display RAM,
I I O/Z
High impedance when ADF = "L",
17 MAo
18 FRP 0 Frame signal
19 LIP 0 Display data latch signal
20 CE 0 Segment Drv chip enable clock
21 CLP 0 Display data shift clock
22 FRMB 0 Alternate signal
23 LDo
I I 0 Display data parallel outputs (lower side)
26 LD3
27 UDo
I { 0 Display data parallel outputs (upper side)
30 UD3
32 VDD +5V
33 CH 0 Character clock
34 BUSY 0 Ready status signal. "H" during serial transfer halt period,
35 EXBL I Cursor control signal input
36 ADF I Address floating input, Floating when "L",
37 RS I Register select input
38 CS I Chip select, , , selection status when CS =" L"
39 RD I Read, , , data reading possible while RD = "L"
40 WR I Write, , , data writing executed by WR leading edge,
41 RES I Reset signal input, Reset when "L",
42 DBo 8-bit data bus, , , three-state input/output common pins
I I I/O/Z Pull-up registor on-chip
50 DB7 Positive logic
51 RDo
I I I ROM data inputs, , , Dot pattern data of CGROM,
59 RD7
60 RAo
I I O/Z Raster address outputs, High impedance when ADF = "L",
64 RA4
65 XT I Crystal oscillator pins
66 xl' 0 External clock is input to XT, (XT is open,)
67 GND OV
Change R9, R 10, and R 11 contents when "H ",
68 MONO I
Normal when "L", Direct VDD and GND connections possible
69 TEST I Test input pins
I
70 TEST2 Left open for use,
External clock when "H", Self-oscillation when "L",
71 DIV I
Direct VDD and GND connections possible,
72 DINH I display OFF signal input. Display OFF when "L",
73 fs 0 Dot clock
74 MA 0 Memory address counter clock output
40-character memory address output and 80-character data read-
75 640D I ing when "H"
Normal when "L"
4-bit parallel output when "H", ODD/EVEN output when "L",
77 4B/ODEV I
Direct VDD and GND connections possible,
78 HPo 1 font horizontal pitch program input,
I 1 I Direct VDD and GND connections possible,
80 HP2
201
DOT MATRIX LCD CONTROLLER MSM6265GS . - - - - - - - - - - -
tCH tCH
tMAH
tMAH
tMAL
I~
-'r
1- ItREA
tWRA
tRES l
_}.....------.I\'---------
202
- - - - - - - - - - - . DOT MATRIX LCD CONTROLLER MSM6265GS.
203
DOT MATRIX LCD CONTROLLER MSM6265GS . - - - - - - - - - - -
tAH
I---
~K
111
RS,CS
l-: ,I-
tRCS
tcw
\ -V
tDS tDH
I.
DBo ..:. DB7
(WRITE) Ix~ VALID
,:K
DBO - DB7
./
(READ) ~~
VALID
l-
"
,/
t ACC
tOH
204
- - - - - - - - - - - . DOT MATRIX LCD CONTROLLER MSM6265GS.
CLP
UDo - UD3
LDo - LD3 _ _ _--1---'
LIP
BUSY
LIP
FRP
tFRP
FRMB
FR t'=-R
205
DOT MATRIX LCD CONTROLLER MSM6265GS . - - - - - - - - - - -
-
-
-
-
200
-
200
ns
ns
ns
Ready signal "H" time tSUSY 5.11 - - J1s
Frame signal delay time tFRP 2tCH - 2tCH+ 200 ns
AC signal delay time tFR - - 200 ns
CH~
MAo to MAIJ
RAo to RA4 _ _ _oJ
ROo to RD7
tUDS
tUDH
206
- - - - - - - - - : - - - - - . DOT MATRIX LCD CONTROLLER MSM6265GS.
FUNCTIONAL DESCRIPTION
1. LCDC Internal Registers Cursor display mode B
o
1
4) Cu rsor start raster regi ster (R 10)
2
This is one of the cursor control registers. The 3 --~-+--~4--+--~4--
raster address of the top edge of the cursor is 4 --~-+--r-;--+--~;--
specified in the five lower order bits, and the
5 ---r-;--+--r--~4--+--
cursor display mode is specified in the two
higher order bits. The cursor display mode is 6 ---r--r-~~--+--+--+--
207
DOT MATRIX LCD CONTROLLER MSM6265GS . - - - - - - - - - - -
o o-+--+---I-+--t--t-+--
1
2 2~Hi--ttlf-t-tt-tti--ffHft-ffi-
3 3-ffi-H~ft-~~~Hi-~~
4 4-~~~~tiT~~~~-
5 5--ffi-ti~~~~ft-~~~-
6 6--~~-+--+~r-+--t---
7 7--~---i--+--+--+--+--~-
8 8--+~-+--+~r-+--+---
9 9-+--+-t-~~-+--+-
10--~~~~~~~~~ L
o
1
2
3
4
5
6
7
8
9
~ .... ....
10 I' t' t' I' I' +' " --- Displayed up to the maximum raster address.
Maximum raster address < cursor start address;:i cursor end address.
Cursor display is switched off.
Note: When the cursor overlaps pattern data, the result of an EX-OR operation between the cursor signal and the
pattern data is displayed.
6) Start address registers (R12 & R13) 7) Cursor registers (R14 & R15)
Register for setting the memory address The cursor display address is specified by two
corresponding to the first character in the first bytes. The LCDC controls the cursor when the
line on the screen. The LCDC commences data memory address MAxx reaches this address
display from this address. Both reading and while within the R10/Rl1 range.
writing are possible, and when reading, the two Both reading and writing are possible, and when
higher order bits become "00". reading, the two higher order bits become "00".
208
- - - - - - - - - - . DOT MATRIX LCD CONTROLLER MSM6265GS.
Horizontal display
L H L L L H Rl X 0 X
character count
Maximum raster
L H H L L H R9 X 0 X X X
address
L H H L H L RIO Cursor start raster X 0 X B P
L H H L H H Ru Cursor end raster X 0 X X X
L H H H L L R12 Start address (H) 0 0 X X
L H H H L H Rl3 Start address (L) 0 0
Note 1: B denotes cursor blinking, and P denotes the blinking cycle period.
Note 2: "00" is read if registers marked X are read.
[22LI
Set V p -l
R9 setting R9 re-reading
0"'7 o to 7 (according to setting)
8 '''IF(H) Fixed at 7
R 1 0 setting R lOre-reading
0"'6 o to 6 (according to setting)
7 '''IF(H) Fixed at 6
209
DOT MATRIX LCD CONTROLLER MSM6265GS . - - - - - - - - - - -
'17
210
Is
o
o
CLP -t
s:
UOo fD;fD;1 0;- I~ 10 3 r0
2 l O-;-I~r 07 1Ob lOs 10 10 4 3 J
-I
jJ
s:en
s:en
N
en
UI
C)
~
en
~
f!
~
N
o
o
-I
fs ~
-I
CH ----,.......
_-----' :II
X
MAO to MA13 r STAN -I STAM - 1- STAN+l - - 1- STAM+l STAN+2 STAM+2 [ .-n
o
n
o
z
CLP -I
:II
U03 0, Os I 03 D) 07 I Os 03 I D)
o.-
.-
m
UOl I 0, OS, 03 ,D) 07 - , - 05 --I -D31 D) :II
~
UO, I 06 I 04 , 01 'DO , 06 ,- 04 O2 ' DO rn
~
en
UOo 1 06 1 04 1 02 1 Do 1 06 - 1- 0 4 -, - O2 1 Do N
en
STAN+l data
U1
STAN data C)
rn
L03 0, O s , - 03 I D) 0, I Os I 03 I D)
LO) '06 04 I 02 I Do , 06 I 04 I 02 I Do
Raster
address !
1 characte; \ ~~~n~~nsfer
-r
I
000 0000 0001 004E 004F
001 0000 0001 004E 004F
010
011
Line 1
100
101
110
111 0000 0001 004E 004F
000 0050 0051 009E 009F
Up per
Coo" ( sid
l 1
000 0370 0371 03BE 03BF
001
010
011
Co"," (
100
101
110
111 0370 0371 03BE 03BF
000 03CO 03Cl 040E 040F
001
010
011 1-
Coo," ( 100
101
110
111 03CO 03Cl
-- 040E 040F
l l
000 0730 0731 077E 077F
Lo wer
sid
Coo," (
111
000
0730
0780
0731
0781
-- 077E
07CE
077F
07CF
001
010
011
Co"," ( 100
101
110
111 0780 0781
-- 07CE 07CF
-
Figure 5 Refresh memory address (MAo"'MA131
213
DOT MATRIX LCD CONTROLLER . MSM6265GS.-----------
2) Upper and Lower Screen Division Simultaneous output of upper and lower
screen halves
Since the screen is divided into upper and lower The upper and lower screen half addresses
halves, MAxx for the upper side and MAxx for are sent upon being switched within a single
the lower side are sent by LCDC. character period. The upper side address is
sent when the CH is "L" while the lower
side address is sent when CH is "H ".
------~---
MAu to MAl J ~1~O_O_OO~I_03_C_O~I_OO_O_l~_03_C_1~I_OO_O_2~I_O_3C_2~1______ _ I 004F I
040F I
I. One horizontal memory address
I
Simultaneous output of upper side and lower side data under 2-bit parallel
Mode 1 L
data processing mode.
Simultaneous data output of upper side and lower side data under 4-bit
Mode 2 H
parallel data processing mode.
The time charts for modes 1 and 2 are shown in Figure 10 - Figure 13.
214
- - - - - - - - - - - . DOT MATRIX LCD CONTROLLER MSM6265GS.
, . . . - - - - - - , _ UD 1
Data shift
UDo
Upper side
LCD panel
Lower side
Common Drv
- t - - - UD 2
Data shift UD 3
-
Note: MSM5260GS is used for the segment and common drivers. See Figure 8 and Figure 9
for the time chart.
Figure 6 Mode 1 data flow
LCD panel
Common Drv
LDo to LD J
Note: MSM5279GS is used for the segment driver, and MSM5278GS is used for the common driver.
See Figure 10 and Figure 11 for the time chart.
215
~
~
al
C
o
-i
~
Is
CH
J1JUUU1J1Jl.JlJ
_~r-_-_____
----
=I ---- ----- -i
:c
X
r-
(")
----r----""T----r- - - - - --
MAO to MA IJ ENON ENOM I STAN I STAM I STAN+l I STAM+l 1
C
---- (")
o
,- Oata transfer stopped
2
-i
:c
CLP o
r-
r-
m
UOo 1 0 7 10 5 1 0 31 0 1 10-7-1~loJ 10 1 IV 7 10~ID;TDI I :c
UOI I Ob rO~TD2 1 0 0 ---rD;;ID~1 O 2 1 O;-r 0b 104 1 02 I O~ ~
C/)
CN
s:
en
s:
en
N
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Figure 9 Mode 1 memeory address and data transfer in the expansion mode
~
en
....
~
DOT MATRIX LCD CONTROLLER MSM6265GS.
~
0 0
0'" 0'" 0- 0 0'" 0 0- 0
0 0
.0
0'"
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0 0 .0'" 0'" 0
..
0'"
0
0
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Q)
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0 c. 0 0 c:i 0 0
.. u:
z
o
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-s. o o
:r
Q.
...J O' 0 0 o o o
u U ~ ~ ~ ~ ...J ...J
218
DOT MATRIX LCD CONTROLLER MSM6265GS.
e o o 0 6 @)
c: c:
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Cl
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o
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c:
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c5 0 0 u::
z
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z
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u
o::> 0
::>
0
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r5
::>
219
DOT MATRIX LCD CONTROLLER MSM6265GS . - - - - - - - - - - -
220
Is - - nnnnnnnnnn - - - _ -
_ _ JUUUUUUUUUL _ _
CHI/>
MAO to MAI3
CLP
LIP
CEI/>
-I~------------------------------
,-------------------- - - - - -
BUSY
C
Figure 12 Mode 2 data transler stop interval 0
~
3:
~
jJ
X
r-
LIP (')
CLP
-----I
I r----,
I
I nnnn ~n _n9I'n _
I
C
(')
I 0
I Z
LCDC internal
counter
----------~------------~----------------~~~~~ ~
jJ
I 0
I r-
I r-
I
m
CE ~ n~ ____ jJ
Segment driver 3:
carry output
L- en
3:
m
Valid I N
en
U1
G)
N Figure 13 POWER DOWN time chart en
~
~
DOT MATRIX LCD CONTROLLER MSM6265GS . - - - - - - - - - - -
~--f~1
1- ---
M
a:'"
'"
a:'"
Q. Q. i).
::; [f :I:
U
-'"
a:'"
.; >- ;' 8
>-
222
- - - - - - - - - -.... DOT MATRIX LCD CONTROLLER MSM6265GS"
APPLICATION NOTE
1. Mono-Chro Mode
Only character mode is available in Mono-Chro
mode_ There is no graphic mode in this mode.
Description of character mode is described as follows.
Character box :8 x8
Character font : According to the CGROM
contents
Shape of cursor : 2 rasters
Display : 80 characters x 25 lines
Shape of cursor
The shape of cursor is determined by R 10 and Cursor blink
R 11 contents. Since the vertical pitch (14) is The cursor blink frequency should be supplid
read as 8, the R 10 and R 11 contents have to be from the external source to EXBL.
re-read.
Setting MONO input pin at "H" enables this
re-reading as follows.
(example)
MSM6265 CRT Software
RlO : 6 +- RlO B
R11 : 7 +- Rll C
223
DOT MATRIX LCD CONTROLLER MSM6265GS - - - - - - - - - -
fs
Clock XT
MSM6265
VDD
RAo
MONO l
RA4
640D
WIDE
RDo
- l Q)
EXBL RD, ~g
.~ c
.... 0
;:(u
Cursor blink
224
- - - - - - - - - -.... DOT MATRIX LCD CONTROLLER MSM6265GS
Figure 16
MPX ~--------r--------------'
Is odd
number
address
RAo
I ~--------------~
RA4
Cursor blink
Figure 17 Color mode (Character mode: 80 ch. x 25 lines, 40 ch. x 25 lines, graphic mode: 640 dots x 200 dots)
225
DOT MATRIX LCD CONTROLLER MSM6265GS ....- - - - - - - - - -
3. DISPLAY METHOD
V-RAM is provided in the system configuration. So, Writing data into V-RAM has to be done during the
inadequate access of CPU to the V-RAM results course of the CPU cycle. So, external circuit is
flickers on the display. Therefore, refresh cycle and necessary to generate timing for WR signal. In read-
CPU cycle should come alternatively, in other words, ing the data of the V-RAM, the data bus has to be
without omitting the refresh cycle, the V-RAM is latched as the address bus is changing alternatively.
accessed. This is commonly called the "Cycle Steal Figure 19 shows an example circuit.
Method". Figure 18 shows the timing chart.
'+z
'z+
'+z '+
:::i:
'+
:::i:
--------- -----
'+ z "C
0
:::i: z '5
(1)
E
ro
~
(1)
"0
>-
()
:::i:
z ~
e
:J0>
u:
~ ~
co co
"C "C
~:E
(1) (1)
.r:"C
.1- ....0> '"... ....,.u;
I- ~ I- 0> ...
x
() 0 ::c ~
c: (1)
.- c.
c: (1)
226
-----------11. DOT MATRIX LCD CONTROLLER MSM6265GS.
M-WR
M-RD
V-RAM
SELECT
OlEN
READY
DATA LATCH
Legend
Symbol Function
M-WR Write signal to V-RAM from CPU
M-RD Read signal to V-RAM from CPU
V-RAM SEL Address bus of CPU is decoded and being output
ADR SEL Address bus switching signal. 1/4 of fs signal is to be output
READY Signal which let the CPU to wait
WR Write signal of V-RAM
DATA LATCH Signal to latch the data output from V-RAM
227
All specifications and details published are subject to change Without notice.
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