410 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO.

3, MARCH 1998

A High-Efficiency CMOS Voltage Doubler

Pierre Favrat, Associate Member, IEEE, Philippe Deval, and Michel J. Declercq, Senior Member, IEEE

AbstractA charge pump cell is used to make a voltage doubler

using improved serial switches. A complete power efficiency
theory is presented which fits the measurements. The importance
of capacitors is shown with plots of power efficiency versus load
and stray capacitors. Several problems arising at low voltage
or high frequency are developed and some optimizations are
presented. The substrate current is totally suppressed by the
technique of bulk commutation. A power efficiency of 95% has Fig. 1. Charge pump cell from [1].
been reached using external capacitors. A fully integrated charge
pump is also presented and shows a maximum power efficiency
of 75%.
Index Terms Charge pump, dcdc converter, power effi-
ciency, voltage doubler.

I. INTRODUCTION

I N the framework of deep submicrometer technologies and

low power applications where the supply voltage is often
reduced to 1 or 2 V, the voltage doubler appears as a very
important block. It can be used in low-voltage mixed-mode Fig. 2. DC output charge pump with PMOS bias [2].
circuits to supply the analog part or the most critical analog
blocks. This paper is focused on the power efficiency of a
new CMOS voltage doubler.
A circuit, viable in a CMOS technology as a clock booster,
has been proposed in [1]. This circuit has the particularity of
cross-connecting NMOS transistors from their source (Fig. 1).
This use of NMOS is efficient, not only because of higher
carrier speed, but particularly since it provides automatic Fig. 3. Cross section and equivalent schematic of the PMOS.
reverse bias of the junctions. Unfortunately, with this circuit,
to obtain a doubled dc output we need a serial switch, and this
charge pump. Nevertheless, a much better solution, with no
can only be achieved by a PMOS transistor to avoid the
charge loss in the junctions, is possible. It requires only two
drop. The problem arising from the use of PMOS is to ensure
minimum-sized transistors and no second charge pump.
the reverse bias of the junctions.
In addition, we suggest some optimization techniques to
A solution was proposed in [2] using two charge pump
improve the power efficiency. Some are useful at low voltage,
blocks, one for the supply and the other to boost the bulk
others at high frequencies. The maximum achievable power
voltage of P1 (Fig. 2). This solution prevents a direct biasing
efficiency is calculated and plotted for all types of integrated
of the P1 junctions but does not solve the problem for P2. In
capacitors.
the second charge pump, the P2 bulk is connected only to a
The series switch problem for an N-well process was
capacitor, and is thus floating. Therefore, P2s bulk voltage
studied in [4]. The parasitic elements (two vertical bipolars
will rise with junction current. This implies that the drain-to-
and a lateral bipolar shown in Fig. 3) are taken into account
bulk voltage of P2 stays close to the junction potential. The
in a simple way. This allows an approximating simulation
result is a quasi-permanent charge loss. Of course, this loss
of the series switches. In any case, this paper presents a
is not very important compared to the whole efficiency of the
solution to eliminate these parasitic effects, and so an accurate
Manuscript received August 5, 1997; revised October 17, 1997. This work modelization is not necessary.
was supported by the Swiss Program for Scientific Research Encouragement
CERS. Part of this work was presented at the CICC97 and ISCAS97
Conferences. II. REALIZATION
P. Favrat and M. J. Declercq are with the Electronics Laboratories,
Department of Electrical Engineering, Swiss Federal Institute of Technology, To eliminate the effect of the vertical bipolars, one can tie
CH-1015 Lausanne, Switzerland. the well to the higher voltage between source and drain. The
P. Deval is with MEAD Microelectronics Engineering Applications and
Design SA, CH-1025 St-Sulpice, Switzerland. schematic diagram used for fulfilling this function is shown
Publisher Item Identifier S 0018-9200(98)01703-X. in Fig. 4. To keep parasitic elements to a minimum, M1, M2,
00189200/98$10.00 1998 IEEE
FAVRAT et al.: HIGH-EFFICIENCY CMOS VOLTAGE DOUBLER 411

Fig. 4. Connecting the bulk to the highest voltage.

Fig. 7. Parasitic capacitors of the pump capacitors.

The power efficiency is given by

(2)

Fig. 5. The proposed voltage doubler. where is the energy delivered to load

(3)

and is the energy loss

(4)
Fig. 6. Resistors and voltage conventions. Here, is the drop due to , is the total
stray capacitances of the circuit, and is the load resistor.
and M3 must share the same bulk [3]. Of course, the problem is therefore the output of the voltage divider between
is only solved with proper control of M2 and M3, which must and (Fig. 6)
select the higher voltage between source and drain. There is no
(5)
unique solution for solving this problem, as it depends upon
the application. In the next section we show the use of this The total stray capacitance is assumed to be a fixed fraction
technique for the charge pump cell presented in [1]. of the pump capacitor which represent its parasitics
The voltage doubler described in the introduction can be
significantly improved by using a dual series switch and the (6)
principle of bulk switching (Fig. 5). M3 and M4 are the series
The of the integrated pump capacitor was chosen equal
switches, and M5, M6 switch to the highest voltage. If M5 and
to the bottom plate capacitance of the pump capacitor.
M6 are missing, having a large capacitor is of absolute
The top plate capacitance was assumed to be negligible
necessity, because must always stay between 2 V and
(Fig. 7). The of the external pump capacitors was chosen
2 V to avoid switching on the vertical bipolar ( :
equal to output driver capacitance plus pads and board wiring
junction potential). With M5 and M6 included, need
parasitic capacitance. Here, driver output capacitance and
not be large since the voltage drop at the output can be greater
switches associated parasitics must be taken into account
than without affecting the charge-pump efficiency. The
because they are of the same magnitude order of the pads
capacitor (Fig. 5) can be small, but it is still necessary to
and board wiring. They are present on both ports of the
preserve the bulk potential when switching.
pump capacitors and are approximately equal .
Practically, is very small versus the pump capacitor and
III. POWER EFFICIENCY THEORY therefore it does not modify the voltage conversion efficiency.
So an estimated value for is easy to obtain. Then to fulfil
Using bulk switching technique, the power efficiency is the two cases above, the stray capacitance of is defined as
limited only by the losses of the source resistance ( in
Fig. 6) and the switching losses. (7)
Neglecting the resistance of the switches, the source resis- The resulting power efficiency can be expressed as
tance is given by
(8)
(1)

and the power efficiency maximum is reached for

The factor 2 comes from the two capacitors C1 and C2
(Fig. 1), which act at each phase of the clock. It was also (9)
assumed that the voltage drop of M1 through M4 is negligible.
412 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 3, MARCH 1998

At high frequencies, the resistance of the switches and the

time needed to switch between the states is not negligible
because nonoverlapping switching is mandatory for high effi-
ciency. This time depends on how the command signals are
generated, and it can be a few nanoseconds, which is not
negligible at frequencies above 10 MHz. The resulting time
needed to transfer the charges is

(10)

where
period of the clock;
total switching time including nonoverlaping interval.
is directly linked with the RC constant of the circuit
Fig. 8. Power efficiency versus VOUT for f =1 MHz, C = 100 pF, and
so a first-order low-pass term must be added to [5] VIN = 1:5 V showing the importance of capacitors to obtain a small VOUT
drop with good efficiency.

(11)

The cutoff frequency of the system is given by

(12)

If
(13)

Finally, is the absolute minimum value of the source

resistance. The effective value of is not easy to calculate
from the MOS transistor equation because the gate and the
source voltages vary with the output voltage. Moreover, the
capacitor plates resistance must be taken into account. We Fig. 9. Power efficiency normalized to RS =RL showing that the quasi-ideal
can only calculate a range where will be in the normal curve ( = 0:001) is not correct when RL is very high due to efficiency
calculus simplification.
operating condition. The exact value depends on the output
current.
Below the cutoff frequency defined in (12), follows (1) TABLE I
and we can say that power efficiency is altered only by the MAXIMUM POWER EFFICIENCIES
coefficient . It means that the quality of the charge pump is
only affected by the capacitors used.

IV. EFFICIENCY OPTIMIZATION

To improve the efficiency, several points must be consid-
ered. The most important components of this charge pump,
from an efficiency point of view, are the capacitors. If they are
integrated, they always have stray capacitances to the ground,
even if we use a silicon-on-insulator (SOI) technology.
A. Integrated Capacitors
When running at voltages below the maximum voltage
recommended by the process, the best thing to do is to use thin
oxide capacitors. They provide about 515% stray capacitance
and have a high capacitance per area. A second very efficient
solution is the use of double poly capacitors, since although
they have a lower capacitance per area than thin oxide, they
have the smallest stray capacitance at about 5%. It seems that
this value is close to the value of thin oxide capacitors realized
in submicrometer technologies. At very low voltage, below
1 V, the dip in the MOS capacitance versus voltage response
can be bothersome even if the capacitor is in the accumulation
mode. In this case, we recommend the use of double poly
capacitors. Power efficiencies are plotted versus load and
in Figs. 8 and 9. Table I summarizes the different capacitors
available in CMOS.
The quasi-ideal case described by is reached
when external capacitors are used and when the input voltage
is large compared to . Here, a power efficiency close to
100% can be achieved if is very high compared to .
For low input voltage ( 1.5 V), the switches and clock buffers
become very large to achieve sufficiently low ON resistance.
FAVRAT et al.: HIGH-EFFICIENCY CMOS VOLTAGE DOUBLER 413

Fig. 10. Overlapping gate signals.

Fig. 12. Normal high efficiency voltage doubler (M5 and M6 are not
represented to simplify the schematic).

Fig. 11. Nonoverlapping and full swing gate signals.

The required energy to drive these switches and clock buffers

is no longer negligible and will affect the power efficiency.
Fig. 13. Classic level shifter.

B. Nonoverlapping Switching
At high frequency (above 1 MHz), the dynamic losses
become important, and to make things work properly we must
avoid overlap in the clock signals of the two series switches
M3 and M4 (Fig. 10). This is done by adding asynchronous
delays between the two gate signals (Fig. 11). The same can
be applied to the transistors M1, M2.

C. Conductance Improvement
Up to now the gate signals of the two series switches (M3,
M4) were between and 2 (Fig. 10). The conductance
is greatly improved if these signals can range between 0 and
2 (Fig. 11). This is very important for under 1.5 V.
Assuming a of 1.5 V and a of 1 V, the ON voltage
is 0.5 V in the proposed schematic. Driving these switches
between 0 and 2 boosts the ON voltage to 2 V, thus
dividing by four the ON resistance. The entire charge-pump
circuit is represented by a block schematic in Fig. 12.
A simple and well-known circuit that can be used to
implement the function above is shown in Fig. 13. Its principle
is based on the voltage mirror (M3, M4). They generate a
command signal to an inverter (M5, M6). The whole circuit
is supplied by the output voltage of the charge pump.
For low input voltages ( mV), M1 and
M2 also have a low ON voltage. The efficiency and the
overall functionality may be significantly reduced by this. To
overcome this limitation, the gates of M1 and M2 (Fig. 12)
should be driven between and 3 . This could be
achieved by driving the gates of M1 and M2 from an auxiliary
charge pump (Fig. 1) with 02 clock signals. These clock
signals could come from the level shifters used to drive M3
and M4. In practice, the cross coupling of M1 and M2 shown
in Fig. 12 is necessary to start up the charge pump. A simple
scheme which improves the efficiency and guarantees the start-
up is shown in Fig. 14. Important remark: since we generate
Fig. 14. Low-voltage scheme of the high efficiency voltage doubler (M5 and
M6 are not represented to simplify the schematic).
3 , this last technique must be restricted to input voltage
below one third of the maximum voltage specified in the
process.
V. SIMULATED RESULTS
To illustrate the improvement achievable with bulk switch-
ing, we show two simulations beginning at start up. Once the
final voltage is reached (twice 1.5 V), the addition and removal
of a capacitive load occurs twice. First, the charge-pump circuit
is simulated without M5, M6 (Fig. 15) and compared with
the bulk-switched version (Fig. 16). The high current peaks
observed may reduce the power efficiency for capacitive load
and also reduce the circuits charge-up speed. Of course, if
a capacitor big enough to handle the load were added at the
output, the problem would not appear, but then the charge-up
speed would be greatly reduced. The cost in complexity and
the added area of two minimum-sized transistors like M5, M6
is very small for all the advantages they bring.
For measurement access reasons, we were not able to
provide the measured versions of Figs. 15 and 16.
414
Fig. 15. Simulation of the step-up without bulk switching showing the very
high current peaks flowing to the substrate due to the vertical bipolars.
Fig. 16. Simulation of the step-up with bulk switching showing that the
bulk voltage always stays higher than VOUT , a faster rise of VOUT , and no
leakage current.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 3, MARCH 1998
Fig. 17. Microphotograph of the voltage doubler and included low-voltage
oscillator. The chip size is 1.4 mm 2 0.56 mm in a 2-m technology
(capacitors are external).
Fig. 18. Power efficiency measurement versus calculated. Power efficiency
expression (7) matches well the measurements.
VI. EXPERIMENTAL RESULTS
Real application often requires a few milliampers drive
capability for the dcdc converter. Supplying such a current
requires very large capacitors (or high clock frequency). If
we use external capacitors, this constraint is compensated by
a significant improvement in the power efficiency: external
capacitors give a very low (0.002) and allow a low clock
frequency, and thus a low fCV loss in the switches. For
example, a voltage doubler with 100-nF external capacitors
and 50-kHz clock frequency gives an output resistance of
100 . This circuit has been implemented in a 2- m CMOS
technology and occupies 1 mm without pads (Fig. 17). Five
pads are required to connect the capacitors (2 2 for the
pump capacitors and one for ).
The measured and calculated power efficiency from (7) with
is plotted in Fig. 18 showing a good fit with the
theory.
The total current consumption without load is 30 A, while
only 15 A should be lost in the stray capacitors. The 15 A
comes both from the switch gates and the transient short-circuit
current of the four-stage buffer that generates and .
Another implementation using integrated capacitors was
done in a 0.7- m technology (Fig. 19). It used two MOS ca-
FAVRAT et al.: HIGH-EFFICIENCY CMOS VOLTAGE DOUBLER 415

Fig. 21. Power efficiency versus frequency showing the practical range of
the charge pump.
Fig. 19. Microphotograph of the voltage doubler in a 0.7-m CMOS digital
technology.

Fig. 22. Measured and theoretical source resistance versus frequency. Above
Fig. 20. Measured and theoretical power efficiency of the fully integrated
the cutoff frequency of the system, the source resistance reaches a minimum.
voltage doubler at 10 MHz.

Fig. 21, and the source resistances versus frequency in

pacitors of 100 pF with an (based on the technology Fig. 22.
parameters). The maximum power efficiency of this charge
pump by (8) is 75%, and of course the voltage conversion VII. CONCLUSIONS
efficiency of 90% at the maximum power efficiency. From
here we can see the main drawback of this circuit: if we The feasibility of a high-power efficiency CMOS voltage
want a good power efficiency we have a voltage conversion doubler depends on the having of a good series switch. A
solution was found for a charge pump cell, and the measured
efficiency of 90%, but the ripple is bigger because capacitors
circuit showed an improved charge-up speed and a better
are 10% discharged. Clearly, to have a low ripple we must
power efficiency for heavy capacitive loads. With all improve-
add a filtering capacitor ( ) or work at a lower power
ments presented here and with external capacitors, a power
efficiency.
efficiency up to 95% has been demonstrated.
Nevertheless, the fully integrated charge pump has some
A fully integrated charge pump was also presented. It
benefits too: it does not use any external components, and
shows a power efficiency up to 75% and a current capa-
it is very small (500 300 m for our example) because
bility of several millliamperes. The output current of this
it uses a high switching frequency. This results in an output
circuit can be regulated using the frequency in a wide range
current of 2 mA which is in the range of real applications.
(100 kHz10 MHz). This allows a power efficiency better than
A direct area comparison between the two circuits cannot be
70% with an output current ranging from 20 A to 2 mA.
performed because the processes are different. Moreover, the
The principle presented here is not restricted to voltage
first one was sized to achieve an efficiency better than 90%
doublers but can also be used for triplers and other multipliers.
for an input voltage of 1.1 V @ 1 mA ( V). In
Two doublers can also be cascaded to reach four times the
any case, for low-voltage, low-power applications, a dcdc
input voltage.
converter using external capacitors will be better, while a fully
integrated voltage doubler will always require a smaller area
because no pads are required for the capacitors. ACKNOWLEDGMENT
The power efficiency versus output load characteristics are The authors wish to thank Prof. G. Temes (OSU) for
shown in Fig. 20, the power efficiency versus frequency in reviewing and revising the original manuscript.
416 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 3, MARCH 1998

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Pierre Favrat (S89A95) was born in Lausanne,
Switzerland, on May 19, 1967. He received the
M.S. degree from the Swiss Federal Institute of
Technology, Lausanne, Switzerland, in 1994.
Since 1994, he has been a Ph.D. student at
the Electronics Laboratory, Swiss Federal Institute
of Technology (EPFL), Lausanne, Switzerland. His
current interests are in mixed digital analog IC
design particularly on dcdc converters and high-
voltage circuits.
in Brussels, Belgium, on January 28, 1945. He
received the Ph.D. degree from the Catholic Uni-
versity of Louvain, Belgium, in 1971.
From 1971 to 1973, he was Professor in elec-
tronics and semiconductor physics at the University
of Zaire, Kinshasa, within the framework of the
Belgian University Cooperation program. In 1973,
he was awarded a Senior Fulbright Fellowship and
joined Stanford University, Stanford, CA, as a Re-
search Associate in the Microelectronics Labs. From
1974 to 1978, he was Research Associate and Lecturer at the Catholic
University of Louvain, Belgium. In 1978, he joined Tractebel (Societe
Generale de Belgique), in Brussels, Belgium, where he was Group Leader
of the Electronic Systems team. In 1985, he joined the Swiss Federal Institute
of Technology (EPFL), Lausanne, Switzerland, where he is currently Professor
and Director of the Electronics Laboratory. His research activities are related
to mixed analog-digital IC design and design methodologies. He is author or
co-author of more than 100 scientific publications and holds several patents.

Philippe Deval was born in La Rochelle, France, on

July 15, 1960. He received the M.S. degree from the
Swiss Federal Institute of Technology, Lausanne,
Switzerland, in 1983. He received the Ph.D. degree
in 1992 for his work on high-accuracy A/D convert-
ers using dynamic current memories from the from
Swiss Federal Institute of Technology, Lausanne,
Switzerland.
Since 1993, he has been with MEAD Micro-
electronics, St-Sulpice, Switzerland, where he is
Analog Design Manager. His current interests are
in low-voltage/low-power mixed digital analog IC design, biomedical ASICs
including low-voltage supplies (1.1 V), and high-voltage output capabilities
(1540 V). He is author or co-author of more than 20 scientific publications.