Ucomputer & Interfacing Chapter Three PDF

Chapter 3
Intel 8086 PROCESSOR

PROGRAMING & INSTRUCTION
SETS
DTM 1
Course Instructor: Demisew T.

Outline of the chapter
Introduction
8086 Addressing Modes
Introduction to Assembly Language
Programming
Instruction Set of 8086
DTM 2
Introduction
The 8086 has about 117 different instructions with about
300 opcodes.
The 8086 instruction sets can contain no operand, single
operand, and two operand instructions.
The 8086 instructions do not permit memory to memory
operations except for string instructions which involve
array operations.
The processor can access memory in different ways that
are collectively called addressing mode.
DTM 3
The addressing modes describe the types of operands and
the way they are accessed for executing an instruction.
The number of addressing modes is determined when the
microprocessor is designed and cannot be changed. The
8086 provides a total of seven distinct addressing modes:
a) Register e) Based relative
b) Immediate f) Indexed relative
c) Direct g) Based indexed
d) Register indirect relative
MOV instructions are used to explain addressing modes.
DTM 4
A) Register Addressing Mode: MOV reg1, reg2;

Relatively fast transfer since memory is not accessed.
Examples:
MOV BX, DX ; copy the contents of DX into BX
MOV ES, AX ; copy the contents of AX into ES
ADD AL, BH ; add the contents of BH to Contents of AL.
The size of reg1 and reg2 must be the same. MOV CL, AX is illegal
for instance.
DTM 5
B) Immediate Addressing Mode: MOV reg, constant;

It can be used to load info into any of the registers except the
segment registers and flag register. Examples:
MOV AX, 2550H ; move 2550H into AX
MOV CX, 625 ; load the decimal value 625 into CX
MOV BL, 40H ; load 40H into BL
MOV DS, 0123H; is illegal! Instead we can use: MOV AX, 0123H
followed by MOV DS, AX
DTM 6
C) Direct Addressing Mode: MOV reg, [constant] or

MOV [constant], reg; here constant is not operand but
it is an offset or EA in memory of operand. Example:
MOV DL, [2400H]; move contents of DS: 2400H into DL
Exercise 3-1: Find the physical address of the memory location
and its contents after the execution of the following, assuming that
DS = 1512H.
MOV AL, 99H
MOV [3518H], AL
DTM 7
D) Register indirect Addressing Mode: MOV reg1, [reg2]
or MOV [reg2], reg1; here the address of the memory
location where the operand resides is held by a register, reg2.
reg1 can be any general purpose register and reg2 can be
either of SI, DI, or BX
Example: MOV AL, [BX] ; moves into AL the contents of the memory
location pointed to by DS:BX
MOV CL, [SI] ; move contents of DS:SI into CL
MOV [DI], AH; move contents of AH into DS:DI
MOV DX, [BX]; move contents of DS:BX into DL and contents of
DS:BX+1 into DH
DTM 8
Exercise 3-2: Assume that DS = 1120H, SI = 2498H, and AX =

17FEH. Show the contents of memory locations after the
execution of MOV [SI], AX
Solution: The contents of AX are moved into memory locations with logical
address DS: SI and DS: SI + 1;
therefore, the physical address starts at DS (shifted left) + SI = 13698. According
to the little endian convention, low address I3698H contains FE, the low byte,
and high address 13699H will contain 17, the high byte.
DTM 9
E) Based relative Addressing Mode: MOV reg1,

[reg2]+const or MOV [reg2]+const, reg1; const is an 8-
bit displacement value.
reg1 can be any general purpose register and reg2 can
only be either of BP or BX
The default segments used for the calculation of the
physical address (PA) are DS for BX and SS for BP.
PA= DS*10H+BX+const; EA=BX + const or
PA=SS*10H+BP+const and EA= BP + const
DTM 10
Examples:
MOV CX, [BX]+10 ; move DS:BX+10 and
DS:BX+10+1 into CX. PA = DS*10H+ BX + 10,
MOV AL, [BP]+5 ;PA = SS*10H + BP + 5
Alternative codings for MOV reg1, [reg2]+const is MOV reg1,
[reg2+const] or MOV reg1, const[reg2] for instance, MOV CX,
[BX]+10 is same as "MOV CX, [BX+10]" or "MOV CX, 10[BX]"
DTM 11
F) Indexed relative Addressing Mode: MOV reg1,
[reg2]+const or MOV [reg2]+const, reg1; const is an 8-bit
displacement value.
reg1 can be any general purpose register and reg2 can only
be either of DI or SI
PA= DS*10H+DI+const; EA=DI+ const or
PA=DS*10H+SI+const and EA= SI + const
Examples: MOV DX, [SI]+5
;PA = DS (shifted left) + SI + 5
MOV CL, [DI]+20 ;PA = DS (shifted left) + DI + 20
DTM 12
Exercise 3-3: Assume that DS = 4500, SS = 2000, BX = 2100, SI =
1486, DI = 8500, BP = 7814, and AX = 2512. Show the exact physical
memory location where AX is stored in each of the following. All values
are in hex.
a)MOV [BX]+20,AX c)MOV [DI]+4,AX
b)MOV [SI]+10,AX d)MOV [BP]+12,AX
Solution: In each case PA = segment register (shifted left) + offset register +
displacement.
(a) DS:BX+20 location 47120 = (12) and 47121 =(25)
(b) DS:SI+10 location 46496 = (12) and 46497 = (25)
(c) DS:DI+4 location 4D504 = (12) and 4D505 = (25)
(d) SS:BP+12 location 27826 = (12) and 27827 = (25)
DTM 13
G) Based Indexed relative Addressing Mode: MOV reg1,
[reg2][reg3]+const or MOV [reg2][reg3]+const, reg1; const is an 8-bit
displacement value.
reg1 can be any general purpose register and reg2 can only be
either of DI or SI and reg3 can only be either of BX or BP.
PA= DS*10H+BX+DI+const; EA=DI+BX+ const or
PA=SS*10H+BP+SI+const and EA= SI +BP+ const
Examples:
MOV CL,[BX][DI]+8 ;PA = DS (shifted left) + BX + DI + 8
MOV CH,[BX][SI]+20 ;PA = DS (shifted left) + BX + SI + 20
MOV AH,[BP][SI]+29 ;PA = SS (shifted left) + BP + SI + 29
Note that "MOV AX, [SI][DI]+displacement" is illegal.
DTM 14
Summary of addressing modes
DTM 15
DTM 16
DTM 17
Quiz #1
Assume that the registers have the following values (all in hex) and that
CS= 1000, DS = 2000, SS = 3000, SI= 4000, DI= 5000, BX = 6080,
BP= 7000, AX= 25FF, CX = 8791, and DX= 1299. Give the
addressing mode for each of the following, calculate the physical
address of the memory where the operand is stored and the contents
of the memory locations in each of the following addressing examples.
1. MOV [SI],AL
2. MOV [DI+6],BX
3. MOV [BP][SI]+ 10,DX
4. MOV [3600],AX
5. MOV [BP]+200,AX
6. MOV [BX+SI+100],BX
DTM 18
Programming
Program execution in any microprocessor system consists
of fetching binary information from memory and
decoding that information to determine the instruction
represented.
For us it is much easier to remember the mnemonic SUB
AX,AX than the corresponding machine code 2BC0.
For this reason, we write source files containing all the
instruction mnemonics needed to execute a program.
DTM 19
Programming
The source file is converted into an object file, containing
the actual binary information the machine will
understand, by a special program called an assembler.
Some assemblers allow the entire source file to be written
and assembled at one time.
Other assemblers, called single-line assemblers, work with
one source line at a time and are restricted in operation.
The DEBUG utility that comes with DOS and Windows
(up to Windows XP) contains a built-in, single-line
assembler.
DTM 20
Programming
We use a cross-assembler instead of single-line assembler.
Figure 3.1 shows source program assembling process.
The source file in the example, TOTAL.ASM, is presented as
input to the assembler. The assembler will convert all source
statements into the correct binary codes and place these into
the object file TOTAL.OBJ.
A second file created by the assembler is the list file,
TOTAL.LST, which contains all the original source file text plus
the additional code generated by the assembler. The list file may
be displayed on the screen, or printed. The object file may not
be printed or displayed, since it is just code. next
DTM 21
Programming
DTM 22
Programming
The sample source file, a subroutine designed to find the
sum of 16 bytes stored in memory.
DTM 23
Programming
The list file for our example subroutine looks like this:
DTM 24
Programming
Assembler Directives ORG, SEGMENT, ENDS, ASSUME,
and END
When writing 8086 source files, we separate code areas
from data areas.
We may even have a separate area reserved for the stack.
The new source file for TOTAL, which includes
separate areas called segments, contains many new
pseudo codes to help the assembler generate the correct
machine code for the object file.
DTM 25
Programming
DTM 26
Programming
Most assemblers now accept simplified segment

directives and automatically generate the necessary code
to manage segments.
The TOTAL source file, rewritten with simplified
segment directives, now looks like:
DTM 27
Programming
DTM 28
Programming
The first directive, .MODEL, instructs the assembler that
the type of program being created falls into a category
called SMALL.
All of the programs in this course are small programs.
Other models are as indicated in Table 3.4.
The .DATA directive indicates the beginning of a data
segment. There is no need to indicate the end of the data
segment. This is automatically assumed when the .CODE
directive is encountered, which begins the code segment.
DTM 29
Programming
DTM 30
Programming
When a large program must be written by a team of people, each
person will be assigned a few subroutines to write.
They must all assemble and test their individual sections to ensure
the code executes correctly.
When all portions of the program (called modules, after a
technique called modular programming) are assembled and tested,
their object files are combined into one large object file via a
program called a linker.
Figure 3.2 represents this process. The linker examines each object
file, determining its length in bytes, its proper place in the final
object file, and what modifications should be made to it.
In addition, a special collection of object files is sometimes
available in a library file.
DTM 31
Programming
DTM 32
Programming
When the linker is through, the final code is written to a file called
the load module. Another program called a loader takes care of
loading the program into memory.
Usually the linker and loader are combined into a single program
called a link-loader.
So, writing the source file is actually only the first step in a long
process.
But even before a source file can be written, the programmer must
understand the instructions that will be used in the source file.
The remaining sections will begin coverage of this important topic,
Instruction Set of 8086.
DTM 33
The instruction set of the 8086 microprocessor is divided
into seven different groups:
i. Data transfer
ii. Strings
iii. Arithmetic
iv. Bit manipulation
v. Loops and jumps
vi. Subroutine and interrupt
vii. Processor control
DTM 34
i. Data transfer Instructions: This group of instructions makes it
possible to move (copy) data around inside the processor and between
the processor and its memory.
a) MOV; MOV Destination, Source:
Transfer can be from register to register, register to memory or from memory
to register but not from memory to memory.
The source and destination must be of same type i.e. either both must be byte
or word.
MOV instruction does not affect any flags.
DTM 35
DTM 36
DTM 37
In MOV [SI], 0 the processor does not know if the 0

should be coded as a byte value, or as word value.
For cases like this, include some additional information
in the instruction's operand field.
If you wish to MOV a byte value into memory, use
MOV BYTE PTR [SI], 0. Word values require MOV
WORD PTR [SI], 0.
The byte ptr, and word ptr assembler directives stand for
"byte pointer," and "word pointer."
DTM 38
i. Data transfer Instructions:
b) PUSH and POP instructions: are used to load to or receive data from the
stack memory.
PUSH Source (Push Data onto Stack): decrements the stack pointer by 2
and copies a word from a specified source to the location in the stack segment
where the stack pointer then points.
The source of the word can be a general- purpose register, a segment register,
or memory.
No flags are affected by this instruction.
DTM 39
EXAMPLES:
PUSH BX; Decrement SP by 2, copy BX to stack
PUSH DS; Decrement SP by 2, copy DS to stack
PUSH AL; Illegal, must push a word
PUSH TABLE [BX]; Decrement SP by 2, copy word from memory in DS
at EA = TABLE + [BX] to stack
PUSHA ; Save all 16-bit registers onto the stack in the following order: AX,
CX, DX, BX, SP, BP, SI, DI. The value of the SP is that before the PUSHA
instruction.
PUSHF; copies the contents of the flag register to the stack.
DTM 40
DTM 41
DTM 42
d) POP; POP Destination: copies a word from the stack location
pointed to by the stack pointer to a destination specified in the
Instruction.
The destination can be a general-purpose register, a segment register,
or a memory location. The data in the stack is not changed.
After the word is copied to the specified destination, the stack
pointer is automatically incremented by 2 to point to the next word
on the stack.
No flags are affected by the POP instruction.
DTM 43
EXAMPLES:
POP DX; Copy a word from top of stack to DX Increment SP by 2
POP DS; Copy a word from top of stack to DS Increment SP by 2
POP TABLE [BX]; Copy a word from top of stack to memory in DS
with EA = TABLE +[BX]
NOTE: POP CS Is illegal.
DTM 44
DTM 45
POPA Destination (Pop All Registers).
All general purpose registers are popped from the stack in the order indicated
in Table 3-6.
Note that the contents of the SP are not loaded with the data popped off the
stack.
This is necessary to prevent the stack from changing locations halfway through
the execution.
DTM 46
Overflow and Underflow of Stack:

PUSH instruction decrements SP by 2. At some
point, if SP=0000H and if there is an attempt to
PUSH data on the stack, Stack overflow will result.
On the other hand, POP instruction increments SP
by 2. At some point, if SP=FFFFH and if there is an
attempt to POP data from the stack, Stack
Underflow will result.
DTM 47
IN Accumulator, Port (Input Byte or word from Port):
Data read from an input port always ends up in the accumulator.
IN: copy data from a port. Port can be direct or indirect.
Indirect: If a full 16-bit port address must be specified, the port address is loaded into
register DX, and IN AL,DX or IN AX, DX is used to read the input port.
Direct; If the port number is between 00 and FFH, for instance, to input from port 80H
we would use IN AL,80H or IN AX,80H. Using AL in the operand field causes 8 bits of
data to be read. Two bytes can be input by using AX in the operand field.
DTM 48
OUT Port, Accumulator (Output Byte or Word to Port):
With OUT, we can send 8 or 16 bits of data to an output port.
The port address may be loaded into DX for use with OUT DX, AL or
OUT DX, AX, or specified within the instruction, as in OUT 80H,AL or
OUT 80H, AX.
DTM 49
LEA Destination, Source (Load Effective Address):
Determines the offset of the variable or memory location named as the source
and loads this address in the specified 16-bit register.
Flags are not affected by LEA instruction.
DTM 50
LEA Destination, Source (Load Effective Address):
This instruction is used to load the offset of the source memory operand into
one of the processor's registers.
The memory operand may be specified by any number of addressing modes.
The destination may not be a segment register.
MOV BX, 35h
MOV DI, 12h
LEA SI, [BX+DI] ; SI = 35h + 12h = 47h
Note: The integrated 8086 assembler automatically replaces LEA with a more
efficient MOV where possible. For example:
org 100h
LEA AX, m ; AX = offset of m
RET
DTM m dw 1234h 51
END
XCHG Destination, Source (Exchange Data):
used to swap the contents of two 8-, or 16-bit operands.
One operand must be a processor register (excluding the segment registers). The other
operand may be a register or a memory location.
If a memory location is used as an operand it is assumed to be within a data segment.
Example: Registers AL and BL contain 30H and 40H, respectively. What is the result
of XCHG AL, BL?
Solution: After execution, AL contains 40 and BL contains 30.
The machine code for XCHG AL, BL is 86 C3. It may be interesting to note that the
machine code for XCHG BL. AL (which performs the same operation as XCHG AL,
BL) is 86D8.
DTM 52
XLAT Translate-Table (Translate Byte):
XLAT assumes that a 256-byte data table has been written into
memory at the starting address contained in register BX.
The number in register AL at the beginning of execution is used as an
index into the translation table.
The byte stored at the address formed by the addition of BX and AL
is then copied into AL.
The translation table is assumed to be in the data segment.
AL AL+BX+DS*10H
DTM o Only instruction adding an 8-bit to a 16-bit number. 53
Example for XLAT Instruction
Assume DS=0300H, BX=0100h and AL=0DH, ODH represents the ASCII code
of the character CR.
The execution of XLAT replaces the contents of AL by the content of the
memory location with the physical address: Ph. A = DS*10H+BX
+AL=03000+0100+0DH=0310DH; Thus AL [0310DH].
Assuming this memory locations contains 52H (EBCDIC code for CR) this
value is placed in AL; Thus AL= 52H
Therefore, XLAT Performs the direct table lookup technique often used to
convert one code to another .
Extended Binary Coded Decimal Interchange Code (EBCDIC) is an 8-bit character
encoding used mainly on IBM mainframe and IBM midrange computer operating systems
DTM 54
Reading Assignment:
LDS
LES
LAHF and
SAHF
DTM 55
ii. String Instructions:
A particularly nice feature of the 8086 is its ability to handle strings.
A string is a collection of bytes, or words that can be up to 64KB in
length.
An example of a string might be a sequence of ASCII character codes
that constitute a password, or the ASCII codes for Good Morning!.
The common operations that we can perform on any string are
copying, comparing and scanning.
DTM 56
ii. String Instructions:
A special instruction called the repeat prefix can be used to repeat the copy,
compare, or scan.
Register CX contains the repeat count necessary for the repeat prefix. CX is
decremented during the string operation, which terminates when CX reaches 0.
SI register points to the first element of the source string, which must be located
in the data segment. The destination string is located in a similar way via the DI
register and must reside in the extra segment.
Direction flag (DF) is used to control the way SI and DI are adjusted during a
string instruction. They are automatically incremented or decremented by 1, or 2,
based on the value of the direction flag and the size of the string elements.
DTM 57
.
DTM 58
Initializing the String Pointers
Before we can use any string instruction, we have to set up the SI, DS, DI, and
ES registers. The source string (SHOPPER) in Figure 3-8 could be pointed to
by these instructions:
MOV AX, 510H ; string segment-address
MOV DS, AX
MOV SI, 0 ; string offset within segment
When the contents of SI and DS are combined to form an effective address,
05100H will be the first byte accessed in the data segment.
A similar technique is used to initialize the destination string (SHOPPING):
MOV AX, 4A8H ; string segment - address
MOV ES, AX
MOV DI, 0 ; string offset within segment
DTM 59
REP/ REPE/ REPZ/ REPNE/ REPNZ: are available for use by the
programmer to control the way a string operation is repeated. They are all
recognized by the assembler as prefix instructions for string operations.
MOVS (move string) and STOS (store string) make use of the REP prefix.
When preceded by REP, these string operations repeat until CX
decrements to 0.
REPE and REPZ operate the same way, but are used for SCAS (scan
string) and CMPS (compare string). Each time SCAS or CMPS completes
its operation, the zero flag is tested and execution continues (repeats) as
long as the zero flag is set.
REPNE and REPNZ also repeat as long as CX does not equal 0 but
require that the zero flag be cleared to continue.
DTM 60
So, we have three ways to repeat string operations:

1. Repeat while CX does not equal 0. (REP)
2. Repeat while CX does not equal 0 and the zero flag is set. (REPE
and REPZ
3. Repeat while CX does not equal 0 and the zero flag is cleared.
(REPNE and REPNZ)
DTM 61
In each of the string instructions, the operand can be a byte or a word.
They are distinguished by the letters B (byte) and W (word) in the
instruction mnemonic.
DTM 62
Example: Using string instructions, write a program that transfers a
block of 20 bytes of data.
.MODEL SMALL
.DATA
DATA1 DB ABCDEFGHIJKLMNOPQRST
DATA2 DB 20 DUP(?)
.CODE
;WRITE THE CODE
DTM 63
Example: write a program that uses STOSB to store byte AAH into
100 memory locations. and uses STOSB to change 10th memory
location to 0DH.
.MODEL SMALL
.DATA
mem_location DB 100 (?)
.CODE
;WRITE THE CODE
DTM 64
Assuming that there is a spelling of teff" in an electronic dictionary
and a user types in teaf", write a program that compares these two
and displays the following message, depending on the result:
1 . If they are equal, display "The spelling is correct".
2. If they are not equal, display "Wrong spelling".
.MODEL SMALL
.DATA
DATA_DICT DB "teff"
DATA_TYPED DB "teef"
MESSAGE1 DB "The spelling is correct",'$'
MESSAGE2 DB "Wrong spelling",'$'
.CODE
DTM 65
;write the code here
iii. Arithmetic Instruction
This group of instructions provides the 8086 with its basic
integer math skills.
Floating point math operations are handled by a separate
group of instructions.
Addition, subtraction, multiplication, and division can all be
performed on different sizes and types of numbers.
DTM 66
Addition Instructions: includes

ADD: Addition
ADC: Addition with carry
INC: Increment (Add 1)
DTM 67
ADD/ADC Instruction: ADD destination, source /ADC
destination, source.
These instructions add a number from some source to a number from
some destination and put the result in the specified destination.
ADC also adds the status of the carry flag into the result.
The source may be an immediate number, a register, or a memory
location. The destination may also be a register or a memory location.
The source and the destination in an instruction cannot both be
memory locations.
The source and the destination must be of the same type.
All Flags are affected: AF, CF, OF, PF, SF, ZF.
DTM 68
DTM 69
INC Instruction: INC Destination

The INC instruction adds 1 to a specified register or to a
memory location.
AF, OF, PF, SF, and ZF are affected (updated) by this
instruction.
Note that the carry flag (CF) is not affected. This means
that if an 8-bit destination containing FFH or a 16-bit
destination containing FFFFH is incremented, the result
will be all 0's with no carry.
DTM 70
DTM 71
Example:
Write a program that adds the following two multiword
numbers and saves the result: DATA1 =
548FB9963CE7H and DATA2 = 3FCD4FA23B8DH.
The result should be saved in DATA3.
DTM 72
Subtraction Instructions: This group of instructions

consist of the following group of instructions.
SUB: Subtraction
SBB: Subtraction with borrow
DEC: Decrement
NEG: 2s Complement of a number
DTM 73
SUB/SBB Instruction: SUB destination, Source ; SBB

destination, and Source.
These instructions subtract the number in the source from
the number in the destination put result in the destination.
The SBB, instruction also subtracts the status of CF from
the result.
The source my be an immediate number, a register, or a
memory location. The destination may be a register or a
memory location. The source and destination both must
be word or byte.
Flags Affected: AF, CF, OF, PF, SF, and ZF.
DTM 74
DTM 75
DEC Instruction: DEC destination.

The DEC instruction subtract 1 from the specified destination.
The destination may be a register or a memory location.
The AF, OF, PF, SF and ZF flags are affected.
Note that: The CF is not affected. If the contents of 8-bit register are 00H
and 16-bit register are 0000H, after DEC instruction contents of
registers will be FFH and FFFFH respectively without affecting CF.
DTM 76
NEG This Instruction: Form 2s complement; NEG
Destination
This instruction replaces the number in a destination with the
2s complement of that number.
The destination can be a register or a memory location.
instruction can be implemented by inverting each bit and
adding 1 to it.
The flags that can be affected are: AF, CF, SF, PF, ZF and OF.
DTM 77
CMP (Comparison instruction): CMP Destination,

Source
This instruction compares a byte from the specified source
with a byte from the specified destination, or a word from
the specified source with a word from the specified
destination.
The source can be an immediate number, a register, or a
memory location. The destination can be a register or a
memory location.
DTM 78
The comparison is actually done by subtracting the source

byte or word from the destination byte or word.
The source and the destination are not changed, but the
flags are set to indicate the results of the comparison.
AF, OF, SF, ZF, PF, and CF are updated by the CMP
instruction.
DTM 79
DTM 80
Multiplication Instructions: This group of instructions

consist of following group of instructions:
MUL: Unsigned Multiplication
IMUL: Signed Multiplication
DTM 81
MUL Instruction: MUL source
This instruction multiplies an unsigned byte from source and
unsigned byte in AL register or unsigned word from source
and unsigned word in AX register.
The source can be a register or a memory location.
When the byte is multiplied by the contents of AL, the result
is stored in AX. The most significant byte is stored in AH and
least significant byte is stored in AL.
When the word is multiplied by the contents of AX, the most
significant word of result is stored in DX and least significant
word of result is stored in AX.
Flags: MUL affect AF, PF, SF, and ZF flags.
DTM 82
DTM 83
IMUL Instruction: IMUL source
This instruction multiplies an signed byte from source and
signed byte in AL register or signed word from source and
signed word in AX register.
The source can be a register or a memory location.
When the signed byte is multiplied by AL, the signed result is
stored in AX. The most significant byte is stored in AH and
least significant byte is stored in AL.
When the signed word is multiplied by AX, the most significant
word of result is stored in DX and least significant word of
result is stored in AX.
DTM 84
If the magnitude of the product does not require all the bits
of the destination, the, unused bits will be filled with copies
of the sign bit.
If the upper byte of a 16-bit result or the upper word of a
32-bit result contains only copies of the sign bit (all 0's or
all 1's), then CF and the OF will both be 0.
If the upper byte of a 16-bit result or the upper word of a
32-bit result contains part of the product, CF and OF will
both be 1.
You can use the status of these flags to determine whether
the upper byte or word of the product needs to be kept.
AF, PF, SF, and ZF are undefined after IMUL.
DTM 85
DTM 86
Division Instructions: This group consists of the

following group of instructions
DIV
IDIV
[READING ASSINGEMENT]
DTM 87
BCD and ASCII arithmetic instructions

The 8086 allows arithmetic manipulation of both
BCD and ASCII data.
This is accomplished by instructions that adjust the
numbers for BCD and ASCII arithmetic.
DTM 88
BCD Arithmetic: Intel 8086 provides two instructions to

support BCD arithmetic.
The DAA (Decimal Adjust after Addition) instruction that
follows BCD addition &
The DAS (Decimal Adjust after Subtraction) which follows
BCD subtraction.
Both instructions correct the result of the addition or subtraction
so that it is a BCD number.
DTM 89
The DAA (Decimal Adjust after Addition)

this instruction works as follows:
1. If the value of the low-order four bits (D3-D0) in the AL is
greater than 9 or if AF is set, the instruction adds 6 (06) to
the low-order four bits.
2. If the value of the high-order four bits (D7-D4) in the AL is
greater than 9 or if carry flag is set, the instruction adds 6 (60)
to the high-order four bits.
DTM 90
DTM 91
The DAS (Decimal Adjust after Subtraction)

This instruction works as follows:
1. If the value of the low-order four bits (D3-DO) in the AL is
greater than 9 or if AF is set, the instruction subtracts 6 (06)
from the high-order four bits.
2. If the value of the high-order four bits (D7-D4) in the AL is
greater than 9 or if carry flag is set, the instruction subtracts 6
(60) from the high-order four bits.
DTM 92
DTM 93
ASCII Arithmetic: Numerical data coming into a computer from

a terminal is usually in ASCII code. In this code, the numbers 0
to 9 are represented by the ASCII codes 30H to 39H. The 8086
provides four instructions for ASCII arithmetic.
AAA: ASCII adjust after addition
AAS: ASCII adjust after subtraction
AAM: ASCII adjust after multiplication
AAD: ASCII adjust before division
DTM 94
AAA: ASCII adjust after addition

Used to add the ASCII codes for two decimal
digits without masking off the "3" in the upper
nibble of each.
After the addition, the AAA Instruction is used to
make sure the result is the correct unpacked BCD.
DTM 95
DTM 96
AAS: ASCII adjust after subtraction
Used to subtract the ASCII codes for two decimal digits without masking the "3"
in the upper nibble of each.
The AAS instruction is then used to make sure the result is the correct unpacked
BCD. Some simple numerical examples will show how this works.
The AAS instruction leaves the correct unpacked BCD result in the low nibble
of AL and resets the upper nibble of AH to all 0's.
If you want to send the result back to a CRT terminal, you can OR AL with 30H
to produce the correct ASCII code for the result.
If multiple-digit numbers are being subtracted, the CF can be taken into account
by using the SBB instruction when subtracting the next digits.
The AAS instruction works only on the AL register. It updates AF and CF, but OF, PF, SF, and
ZF are left undefined.
DTM 97
DTM 98
AAM: ASCII adjust after multiplication

After the two unpacked BCD digits are multiplied, the AAM
instruction is used to adjust the product to two unpacked BCD
digits in AX.
DTM 99
AAD: ASCII adjust before division
AAD converts two unpacked BCD digits in AH
and AL to the equivalent binary number in
This adjustment must be made before
dividing the two unpacked BCD digits in AX
unpacked BCD byte.
After the division, AL will contain the
unpacked BCD quotient and AH will contain
the unpacked BCD remainder.
PF, SF, and ZF are updated. AF, CF, and OF are
undefined after AAD.
DTM 100
DTM 101
iv. Bit manipulation Instructions

The instructions in this group are used to perform Boolean
(logical) operations on binary data, shift or rotate bits left
or right in register or memory operands.
These operations are very useful when converting data
from one form to another or for manipulating specific
patterns, such as a single bit that moves through each
position of a register.
These instructions include: NOT, AND, OR, XOR, TEST, SHL/SAL,
SHR, SAR, ROL, ROR, RCL, & RCR
DTM 102
NOT Instruction; NOT Destination
o The NOT instruction inverts each bit (forms the 1's
complement) of the byte or word at the specified destination.
o The destination can be a register or a memory location.
o No flags are affected by the NOT Instruction.
EXAMPLES:
NOT BX ; Complement contents of BX register
NOT BYTE PTR [BX] ;Complement memory byte at offset [BX] in
data segment
DTM 103
AND Instruction: AND Destination, Source
ANDs each bit in a source byte or word with the same number bit in a destination
byte or word. The result is put in the specified destination.
The contents of the specified source will not be changed.
A bit can be masked (reset) by ANDing it with 0.
The source operand can be an immediate number, the contents of a register, or the
contents of a memory location.
The source and the destination cannot both be memory locations in the same
instruction.
Flags: CF and OF are both 0 after AND. PF, SF, and ZF are updated by AND. AF
is undefined. Note that PF has meaning only for an 8-bit operand.
DTM 104
EXAMPLES :
AND CX, [SI] ;AND word in DS at offset [SI] with word in CX register
;Result in CX register
AND BH, CL ;AND byte in CL with byte in BH Result in BH
AND BX, 00FFH ;AND word in BX with immediate 00FFH.
Masks upper byte, leaves lower byte unchanged
If BX = 10110011 01011110 then AND BX, 00FFH Mask out upper 8 bits
of BX and the Result: BX = 00000000 01011110 CF, OF, PF, SF, ZF = 0
DTM 105
OR Instruction; OR Destination, Source
This instruction ORs each bit in a source byte or word with the corresponding bit in a
destination byte or word. The result is put in the specified destination.
The contents of the specified source will not be changed.
A bit in the destination operand can be set to a 1 by simply ORing that bit with a 1 in the same
bit of the source operand. A bit ORed with 0 is not changed.
The source operand can be an immediate number, the contents of a register, or the contents of
a memory location .
The source and the destination cannot both be memory locations in the same instruction.
Flags: CF and OF are both 0 after OR. PF, SF, and ZF are updated by the OR instruction. AF is
undefined after OR.
DTM 106
EXAMPLES (SYNTAX):
OR AH, CL ; CL ORed with AH, result in AH. CL not changed
OR BP, SI ; SI ORed with BP, result in BP. SI not changed
OR SI, BP ; BP ORed with SI, result in SI. BP not changed
OR BL, 80H ; BL ORed with immediate 80H. Set MSB of BL to a 1
OR CX, TABLE [BX][SI] ; CX ORed with word from effective address TABLE[BX][SI] in
;data segment.
OR CX, 0FF00H ; If CX = 00111101 10100101 then OR CX with immediate
;FF00H, Result in CX = 11111111 10100101
;CF=0,OF=0,PF= 1,SF= 1,ZF=0.
DTM 107
XOR Instruction; XOR Destination, source
This instruction Exclusive-ORs each bit in a source byte or word with the same
number bit in a destination byte or word.
The result replaces the contents of the specified destination. The contents of the
specified source will not be changed.
A bit Exclusive-ORed with a 1 will be inverted. A bit Exclusive-ORed with a 0
will not be changed.
The source operand can be an immediate number, the contents of a register, or
the contents of a memory .
The destination can be a register or a memory location. The source and
destination cannot both be memory locations in the same instruction.
Flags: CF and OF are both 0 after XOR. PF, SF, and ZF are updated. PF has
meaning only for an 8-bit operand. AF is undefined after XOR.
DTM 108
EXAMPLES:
XOR CL,BH ;Byte in BH Exclusive-ORed with byte in CL. Result in CL.
;BH not chanced
XOR BP,DL ;Word in DI Exclusive-ORed with word in BP. Result
;in BP. DI not changed
XOR WORD PTR [BX], 00FFH ;Exclusive-OR immediate number
;OOFFH with word at offset [BXI in data
;segment. Result in memory location [BX]
; If BX = 0011110 01101001 , CX = 00000000 11111111
XOR BX,CX ; Result: BX = 0011110110010110 Note bits in lower
;byte are inverted CF,OF,SF,ZF = 0, PF = 1, AF
DTM 109
TEST Instruction; TEST Destination, source
This instruction ANDs the contents of a source byte or word with the
contents of the specified destination word.
Flags are updated, but neither operand is changed.
The TEST instruction is often used to set flags before a Conditional Jump
instruction.
The source operand can be an immediate number, the contents of a register,
or the contents of a memory .
The destination operand can be in a register or in a memory location. The
source and the destination cannot both be memory locations in an
instruction.
Flags: CF and OF are both 0's after TEST. PF, SF, and ZF will be updated to
show the results of the ANDing. PF has meaning only for the lower 8 bits
DTM of the destination. AF will be undefined. 110
DTM 111
Shift and rotate instructions
PF, SF and ZF flags are affected by shift instructions but left unchanged
by the rotate instructions
Shift Instructions: (SHL, SHR, SAL, SAR)
SHL Shift Logical Left Instruction : SHL Target, Count ;
o SHL Target, 1 ;
o SHL Target, C L;
SHL mu lt ipl ies the nu mber sig ned o r unsigned by 2 on each
shift
The target can be a register or a memory
112 DTM
SHR Shift Logical Right Instruction : SHR Target , Count;
o SHR Target, 1;
o SHR Target, CL;
SHL di v ides t he n u mber s ig ned o r unsign ed by 2 on each
shif t
Th e t a r g e t c an b e a r e g i s t er o r a m e m o ry

Carry
SHR 0
Target
Ex: MOV AL,8
SHR AL,1
MOV BL,16
MOV CL,3
SHR BL,CL ;
113 DTM
Shift Instruction
SAL Shift Arithmetic left Instruction :

o SAL Target, 1;
o SAL Target, CL;
SA L d i v i d e s a s i g n e d n u m b er b y 2 o n e a c h shif t
The t a r g e t c an b e a r e g i s t er o r a m e m o ry
Carry
SAL 0
Ex: MOV AL,8 Target
SAL AL,1
MOV BL,16
MOV CL,3
SAL BL,CL ;
11
4
Shift Instruction
SAR Shift Arithmetic Right Instruction :

o SAR Target, 1;
o SAR Target, CL;
SA L d iv ide s a sig ne d n u mber b y 2 o n e ach shif t(The MS B
rema i n s t he s a m e)
Th e t a r g e t c an b e a r e g i s t er o r a m e m o ry

Carry
SAR
Ex: MOV AL,6 Target
SAR AL,1
MOV BL,-16
MOV CL,3
SAR BL,CL ;
115 DTM
Example: A 16-bit unsigned number
X is present in AX register. Write a
program to compute 10*X (ten
multiplied by X), assuming that final
result can be filled in 16 bits.
116 DTM
Rotate Instruction
ROL/ROR Rotate Left (Right) Instruction :

o ROL/RO R Target, 1;
o ROL/RO R Target, CL;
All exc ep t i mm edia t e an d s e gment r e gis ter s.
Carry Carry
ROR
ROL
Target Target
Ex: MOV AL,BCh

ROL AL,1
ROL AL,1
ROR AL,1
ROR AL,1
117 DTM
Rotate Instruction
RCL/RCR Rotate Through Carry Left (Right) Instruction :
o RCL/RC R Target, 1;
o RCL/RC R Target, CL;
Al l exc ep t i mm edia t e an d s e gment re g ister s.
Carry Carry
RCL RCR
Target Target
Ex: Consider a 64-bit number X=X63X62X0 located in DXCXBXAX

registers. Write an assembly code to shift X one position left.
118 DTM
Rotate Instruction
RCL Shift Arithmetic Right Instruction :

o SAR Target, 1;
o SAR Target, CL;
A ll ex cep t i m m ed ia t e an d s e g me nt registe rs.
Co u nt m ust b e 1 or CL .
Ex: MOV AL,6
SAR AL,1
MOV BL,-16
MOV CL,3
SAR BL,CL ;
119 DTM
v. Loops and Jumps:

When there is a need to change the path of program
execution by forcing the processor to fetch its next
instruction from a new location we can use Jump
instructions.
When there is a need to execute some portion of the
program more than one times we can use loop
instructions.
DTM 120
Jump instructions are classified as

Unconditional Jump (JMP)
Conditional Jump (J cond)
DTM 121
JMP-Unconditional jump to Specified Destination
This instruction will always cause the 8086 to fetch its next
Instruction from the location specified in the instruction rather than
from the next location after the JMP instruction.
If the destination is in the same code segment as the JMP instruction,
then only the instruction pointer will be changed to get to the
destination location. This is referred to as a near jump.
If the destination for the jump instruction is in a segment with a
name different from that of the segment containing the JMP
instruction, then both the instruction pointer and the code segment
register contents will be changed to get to the destination location.
This is referred to as a far jump.
The JMP instruction affects no flags.
DTM 122
DTM 123
DTM 124
Conditional Jump Instructions
Conditional jumps are always short jumps in the 8086.
These instructions will cause a jump to a label given in the
instruction if the desired conditions occurs in the program
before the execution of the instruction.
The destination must be in the range of -128 bytes to +127
bytes from the address of the instruction after the
conditional transfer instruction.
If the jump is not taken (jump condition is not fulfilled),
execution simply goes on to the next instruction.
DTM 125
DTM 126
Example: Write an assembly language program that

adds two numbers from memory in data segment at
offsets of 1100H and 1101H and stores the result at
an offset of (1102H if it is positive, 1103H if it is
negative and 1104H if it is zero.
DTM 127
Start
N1+N2
Store
Result<0 Yes result in
1103H
No
Store
Result=0 result in
Yes 1104H
No
Store
result in
1102H
DTM 128
End
Solution:
MOV AL, [1100H] ; AL=N1
ADD AL, [1101H] ; AL=N1+N2
JS NEGATIVE
JZ NULL
MOV [1102H],AL; POSITIVE
; RESULT
JMP END
NEGATIVE: MOV [1103H], AL;
NEGATIVE ;RESULT
JUMP END
NULL: MOV [1104H], AL; NULL
RESULT
DTM
END: HLT 129
Loop: LOOP Label

This instruction is used to repeat a series of instruction some
number of times. The number is specified in the CX register.
The CX register is automatically decremented by one, each
time after execution of LOOP instruction. Until CX=0,
execution will jump to a destination specified by a label in the
instructions.
The destination address for the jump must be in the range of -
128 bytes to +127 bytes from the address of the instruction
after the iteration control instruction.
DTM 130
For LOOPE/LOOPZ and LOOPNE/LOOPNZ

instructions there is one more condition for exit
from loop, which is given below.
DTM 131
Examples
MOV BX, OFFSET PRICE ;Point BX at first element in array
MOV CX, 40 ;Load CX with number of elements in array
NEXT: MOV AL, [BX] ; Get elements from array
ADD AL, 07H ;Add correction factor
DAA ;decimal adjust result
MOV [BX], AL ; Put result back in array
LOOP NEXT ; Repeat until all elements adjusted.
MOV BX, OFFSET ARRAY ;point BX at start of the array

DEC BX
MOV CX, 100 ;put number of array elements in CX
NEXT: INC BX ;point to next element in array
CMP [BX], 0FFH ;Compare array elements FFH
DTM 132
LOOPE NEXT
vi. Subroutine and interrupt Instructions

CALL call a procedure:
The CALL instruction is used to transfer
execution to a subprogram or procedure.
There are two basic types of calls, near and far.
DTM 133
A near call is a call to a procedure, which is in the same
code segment as the CALL instruction.
When the 8086 executes a near CALL instruction, it
decrements the stack pointer by 2 and copies the offset of
the next instruction after the CALL onto the stack. This
offset saved on the stack is referred to as the return address.
A near CALL instruction will also load the instruction
pointer with the offset of the first instruction in the
procedure.
A RET instruction at the end of the procedure will return
execution to the instruction after the call by copying the
offset saved on the stack back to IP.
DTM 134
A far call is a call to a procedure, which is in a different segment
from the one that contains the CALL instruction.
When the 8086 executes a far call, it decrements the stack
pointer by 2 and copies the contents of the CS register to the
stack. It then decrements the stack pointer by 2 again and copies
the offset of the instruction after the CALL instruction to the
stack.
Finally, it loads CS with the segment base of the segment, which
contains the procedure, and loads IP with the offset of the first
instruction of the procedure in that segment.
A RET instruction at the end of the procedure will return
execution to the next Instruction after the CALL by restoring
DTM
the saved values of CS and IP from the stack. 135
DTM 136
RET-Return Execution from Procedure to Calling

Program
The RET instruction will return execution from a
procedure to the next instruction after the CALL
instruction which was used to CALL the procedure.
If the procedure is a near procedure (in the same
code segment as the CALL instruction), then the
return will be done by replacing the instruction
pointer with a word from the top of the stack.
DTM 137
If the procedure is a far procedure, then the instruction
pointer will be replaced by the word at the top of the stack.
The stack pointer will then be incremented by 2. The code
segment register is then replaced with a word from the new
top of the stack.
A RET instruction can be followed by a number, for
example, RET 6. In this case the stack pointer will be
incremented by an additional six addresses after the IP or
the IP and CS are popped off the stack. This form is used
to increment the stack pointer over parameters passed to
the procedure on the stack.
The RET instruction affects no flags.
DTM 138
INT-interrupt Program Execution-INT Type
Interrupt is an instruction that breaks the normal sequence of
execution of instructions, diverts its execution to some other
program called Interrupt Service Routine (ISR).
After executing ISR, the control is transferred back again to the
main program which was being executed at the time of
interruption.
Normal program can be interrupted by three ways:
By external signal
By a special instruction in the program or
By the occurrence of some condition.
DTM 139
Therefore, there are two major types of

interrupts
Hardware generated (derived from a
hardware signal or external signal)
Software generated (internally derived from
the execution of an instruction which
could be by special instruction in the program or
condition produced by instruction)
DTM 140
External Signal (Hardware Interrupt)

In case of 8086, there are two interrupt pins, viz.
NMI and INTR.
The NMI is a non-maskable interrupt input pin,
which means that any interrupt request at NMI input
cannot be masked, or disabled by any means.
The INTR interrupt, however, may be masked using
the interrupt flag (IF).
DTM 141
Special Instruction (software Interrupt)
Intel 8086 supports special instruction for interrupt,
called INT, to execute special program.
Example: INT 21H, INT 10H
Condition Produced by Instruction (software Interrupt)
Intel 8086 can be interrupted by some condition
produced by execution of an instruction.
Example: MOV BL, 00H then DIV BX ; divide by
zero ISR is executed
DTM 142
At the end of each instruction cycle. the 8086 checks to

see if any interrupts have been requested.
If an interrupt has been requested, the 8086 responds to
the interrupt by stepping through the following series of
major actions.
It decrements the stack pointer by 2 and pushes the
flag register on the stack.
It disables the 8086 INTR interrupt input by clearing
the interrupt flag (IF) in the flag register.
DTM 143
It resets the trap flag (TF) in the flag register.

It decrements the stack pointer by 2 and pushes the
current code segment register contents on the stack.
It decrements the stack pointer again by 2 and pushes
the current instruction pointer contents on the stack.
It does an indirect far jump to the start of the
procedure you wrote to respond to the Interrupt.
DTM 144
DTM 145
Interrupt Vector
This vector gives us information about the
location of an I.S.R. in the memory.
An interrupt vector is a 4-byte number. The first
two bytes give us the value of IP (offset) for the
I.S.R, where the last two bytes contain the value
of CS register.
The physical address (20 bits) is defined by :
CS*10h + IP
DTM 146
The interrupt vectors are located in the first 1K byte

area of the memory
Intel reserves the first 32 interrupt vectors for the
present and features microprocessor products
The remaining interrupt vectors (32-255) are
available for the user.
DTM 147
DTM 148
Examples:
INT 35; New IP from 0008CH, new CS from 0008EH
Example of MS-DOS interrupts
INT 21h /AH=1 read character from standard
input, with echo, result is stored in AL. If there is no
character in the keyboard buffer, the function waits
until any key is pressed.
Example: MOV AH,1
INT 21h
DTM 149

INT 21h /AH=2 write character to standard output
entry. DL register contains the character to write,
after execution AL = DL.
Example: MOV AH,2
MOV DL, B
INT 21h
DTM 150
INT 21h / AH=9 - output of a string at DS:DX. String must
be terminated by $.
Example:
.model small
.data
msg db Hello word $
.code
MOV DX, OFFSET msg
MOV AH, 9
INT 21h
hlt
DTM 151
Example of BIOS interrupt
INT 16H/ AH=00H get keystroke from keyboard (no echo).
AH= BIOS scan code.
AL= ASCII character.
(if a keystroke is present, it is removed from the
keyboard buffer).
FOR MORE INTERRUPT AND DETAILED

DISCUSSION READ CHAPTER FIVE
DTM 152
vii. Processor control instructions

Flag Set/clear Instructions:
STC: sets the carry flag, STC doesnt affect any other flag.
CLC: resets the carry flag to zero. CLC doesnt affect any
other flag.
CMC: complements the carry flag. CMC doesnt affect any
other flag.
DTM 153
STD: sets the direction flag. It doesnt affect any other flag.
CLD: reset the DF. It doesnt affect any other flag.
STI: sets the interrupt flag to one. This enables INTR
interrupt of the 8086. It doesnt affect any other flag.
CLI: resets the interrupt flag to zero. Due to this 8086 will
not respond to an interrupt signal on its INTR input. It
doesnt affect any other flag.
DTM 154
External hardware synchronization instructions:

These instructions include: HLT, WAIT, ESC, LOCK,
NOP
HLT instruction:
The HLT instruction will cause the 8086 to stop fetching
and executing instructions. The 8086 will enter a halt state.
The only ways to get the processor out of the halt state are
with an interrupt signal on the INTR pin, an interrupt signal
on the NMI pin, or a reset signal on the RESET input.
DTM 155
WAIT-Wait for Test Signal or interrupt Signal

When this instruction executes, the 8086 enters an idle condition in
which it is doing no processing.
The 8086 will stay in this idle state until the 8086 TEST input pin is
made low or until an interrupt signal is received on the INTR or the
NMI interrupt input pins.
If a valid interrupt occurs while the 8086 is in this idle state, the 8086
will return to the idle state after the interrupt service procedure
executes.
It returns to the idle state because the address of the WAIT
instruction is the address pushed on the stack when the 8086
responds to the interrupt
DTM 156
ESC-Escape
This instruction is used to pass instructions to a coprocessor,
such as the 8087-math coprocessor, which shares the address
and data bus with an 8086.
Instructions for the coprocessor are represented by a 6-bit
code embedded in the escape instruction.
As the 8086 fetches instruction bytes, the coprocessor also
catches these bytes from the data bus and puts them in its
queue. However, the coprocessor treats all the normal 8086
instructions as NOPs.
DTM 157
When the 8086 fetches an ESC instruction, the

coprocessor decodes the instruction and carries out the
action specified by the 6-bit code specified in the
instruction.
In most cases the 8086 treats the ESC instruction as a
NOP.
In some cases the 8086 will access a data item in memory
for the coprocessor.
DTM 158
LOCK-Assert Bus Lock Signal

Many microcomputer systems contain several
microprocessors.
The LOCK prefix allows a microprocessor to make
sure that another processor does not take control of
the system bus while it is in the middle of a critical
instruction which uses the system bus.
The LOCK prefix is put in front of the critical
instruction.
DTM 159
When an instruction with a LOCK prefix executes, the 8086

will assert its bus lock signal output. This signal is connected
to an external bus controller device, which then prevents any
other processor from taking over the system bus.
LOCK affects no flags.
EXAMPLE:
LOCK XCHG SEMAPHORE, AL ;
The XCHG instruction requires two bus accesses. The LOCK prefix prevents
another processor from taking control of the system bus between the two accesses.
DTM 160
NOP-Perform No Operation
This instruction simply uses up three clock cycles
and Increments the instruction pointer to point
to the next instruction.
NOP affects no flags. The NOP instruction can
be used to increase the delay of a delay loop.
When hand coding a NOP can also be used to
hold a place in a program for an instruction that
will be added later.
DTM 161
DTM 162

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Chapter 3

Intel 8086 PROCESSOR

Course Instructor: Demisew T.

A) Register Addressing Mode: MOV reg1, reg2;

B) Immediate Addressing Mode: MOV reg, constant;

C) Direct Addressing Mode: MOV reg, [constant] or

Exercise 3-2: Assume that DS = 1120H, SI = 2498H, and AX =

E) Based relative Addressing Mode: MOV reg1,

Most assemblers now accept simplified segment

In MOV [SI], 0 the processor does not know if the 0

Overflow and Underflow of Stack:

So, we have three ways to repeat string operations:

Addition Instructions: includes

INC Instruction: INC Destination

Subtraction Instructions: This group of instructions

SUB/SBB Instruction: SUB destination, Source ; SBB

DEC Instruction: DEC destination.

CMP (Comparison instruction): CMP Destination,

The comparison is actually done by subtracting the source

Multiplication Instructions: This group of instructions

Division Instructions: This group consists of the

BCD and ASCII arithmetic instructions

BCD Arithmetic: Intel 8086 provides two instructions to

The DAA (Decimal Adjust after Addition)

The DAS (Decimal Adjust after Subtraction)

ASCII Arithmetic: Numerical data coming into a computer from

AAA: ASCII adjust after addition

AAM: ASCII adjust after multiplication

iv. Bit manipulation Instructions

SAL Shift Arithmetic left Instruction :

SAR Shift Arithmetic Right Instruction :

ROL/ROR Rotate Left (Right) Instruction :

Ex: MOV AL,BCh

Ex: Consider a 64-bit number X=X63X62X0 located in DXCXBXAX

RCL Shift Arithmetic Right Instruction :

v. Loops and Jumps:

Jump instructions are classified as

Example: Write an assembly language program that

Loop: LOOP Label

For LOOPE/LOOPZ and LOOPNE/LOOPNZ

MOV BX, OFFSET ARRAY ;point BX at start of the array

vi. Subroutine and interrupt Instructions

RET-Return Execution from Procedure to Calling

Therefore, there are two major types of

External Signal (Hardware Interrupt)

At the end of each instruction cycle. the 8086 checks to

It resets the trap flag (TF) in the flag register.

The interrupt vectors are located in the first 1K byte

Example of MS-DOS interrupts

FOR MORE INTERRUPT AND DETAILED

vii. Processor control instructions

External hardware synchronization instructions:

WAIT-Wait for Test Signal or interrupt Signal

When the 8086 fetches an ESC instruction, the

LOCK-Assert Bus Lock Signal

When an instruction with a LOCK prefix executes, the 8086

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