Documente Academic
Documente Profesional
Documente Cultură
Cherif Salama
Faculty of Media Engineering
and Technology
R2 CLR R3
X
CSEN 402 Computer Organization T0
and System Programming n n
Spring 2014
Exercise 1: LD R1
Represent the following conditional control statement by two register transfer statements
with control functions:
If (X = 0) then (R1 R3) else if (Y=1 and Z = 1) then (R1 R3+R2) The values stored by the end of the clock cycle as follows:
R1 = 7 + 3 = 10
Solution: R2 = 7
X : R1 R3 R3 = 0
XYZ: R1 R3+R2
Exercise 3:
Exercise 2: A digital computer has a common bus system for 16 registers of 8 bits each.
Draw a block diagram for the hardware that implements the following statement. Include 3-1) If the bus is constructed with multiplexers.
the logic gates for the control function. Assume that registers are connected point to point a. How many multiplexers are there in the bus?
and not through a common bus. b. What size of multiplexers is needed?
X T0 + yT2: R3 0, R1 R2 + R3 c. How many selection inputs are there in each multiplexer?
If the values stored in the Registers just before this clock cycle as follows: R1 = 9, R2 = 3-2) If the bus is constructed with three state buffers.
7, R3 = 3. State the values stored in the Registers by the end of the clock cycle a. How many three state buffers are needed?
represented by the above RTL statement. b. How many decoders are needed?
c. What is the size of decoders needed?
Solution:
1 2
Solution:
S C0
A0 X0
S FA Output 0
B0 0
2×1 MUX Y0
1 1
C1
C1
A1 X1
S FA Output 1
B1 0
2×1 MUX Y1
1 1
C2
C
Exercise 5:
3 4