Rony Parvej’s EEE Question Bank FASTRAC ANONTEX LTD.

Recruitment Test Question of FASTRAC ANONTEX LTD. ( an I.C. design company )

Compiled by: Rony Parvej (IUT, EEE’07)
Post: Assistant Engineer (Electrical)
Time: 90 minutes Full Marks: 100
Exam Date: February’2012 Venue: head office

1. Write the elaboration: VLSI, ASIC, CMOS, RTL, FPGA and DFT. 3

2. Write Linux command for the following operations: 5

(a) Change directory to /etc
(b) List all the files in current directory
(c) Rename ‘myfile’ to ‘yourfile’
(d) Count the number of lines in ‘myfile’
(e) Concatenate ‘file2’ at the end of ‘file1’

3. Draw the schematic of a CMOS inverter and it’s layout. Also draw the transfer characteristics curve
( input-vs-output voltage) of the inverter and indicate the point where current is maximum.

4. Which one is faster between NAND and NOR gate? Why?

5. What happens to the delay when you (a) decrease the load capacitance (b) include a resistance at the
output. And why?

6. Write the difference between Moore and Mealy type state machine.

7. Please briefly describe the following:

(a) setup time
(b) race time
(c) hold condition

8. Draw a gate level schematic implementation of a D flip-flop.

9. Make a JK flip-flop using a D flip-flop and 4-to-1 multiplexer.

10. Write the difference between the latch and flip-flop. Write the HDL code for both Latch and flip-
flop.

11. Write the usage of buffer in the digital circuits.

12. Can you implement a XOR using 2-to-1 multiplexer(s)? If yes, then implement it.

13. Design a four input NAND gate using two input NAND gates.

14. Implement a comparator that compares two 2-bit numbers A and B.

The comparator should have 3 outputs: A>B, A<B, A=B.
Do it in two ways: (a) Using combinational logic (b) Using multiplexers.
Write HDL code for your schematic at RTL.

15. Draw a circuit which can divide a frequency by two.

Rony Parvej’s EEE Question Bank FASTRAC ANONTEX LTD.

16. How do you convert a XOR gate into a

(a) buffer
(b) inverter
Use only one XOR gate for each.

17. Define FPGA and ASIC. What is look up table (LUT) in an FPGA? How is ASIC different from
FPGA?

18. Write the difference between a RAM and FIFO. Where is the FIFO used? Is the RAM volatile or
non-volatile?