372 IEEE TRANSACTIONS ON ELECTRONIC COMPUTERS
Analysis of Signal Transmission in Ultra High Speed
Transistorized Digital Computers
F. C. YAO t, MEMBER, IEEE
Summary-The transmission of digital signals plays an impor-
tant role in high speed computers, not only because the traveling time
on the connecting wire is a significant portion of the total delay, but
also because the wire is a distributed parameter coupling network
which, as a transmission line, becomes an integral part of the com-
puter circuitry and affects the over-all performance.
The classical theories of transmission lines are applied to study
the signal waveforms. In the case of low input impedance loads, the
radial (or parallel) transmission line scheme should be used. A
mathematic relationship can be derived among the ramp slope of
signals, the input current to the loads, the length and the impedance
of the lines, and the terminations. Then the reflections can be pre-
dicted. Guided by this, one chooses the optimum line impedance,
the maximum length and the proper termination.
For high input impedance loads, the tapped transmission line
scheme can be used. The multiple junction reflections are expressed
in terms of a series which can be worked out by hand or by machine
computation. Likewise, there is a relationship among the impedance
of the tapped lines and the feeding line, the spacing of loads and the
terminations. There are rules to be followed to decide the transmis-
sion scheme.
I. INTRODUCTION
NTIL RECENTLY, the interconnection prob-
lem in digital computers did not receive much
attention. As the speed and size go up, the means
of interconnecting calls for careful planning. On the
mechanical side, consideration should be given to
accessibility, size and weight, and reliability as well as
module replaceability. On the electrical side, one should
be aware of the magnitude of crosstalk and the neces-
sity of impedance matching. This paper will endeavor
to serve as a guide for planning the interconnecting
scheme for the electrical viewpoint, as a result of signal
transmission analysis.
For high speed computation, the circuit delay should
be short. To send more information per unit time, it is
essential for signal pulses to have a sharp rise and fall
time in order to achieve a high repetition rate. Within
the maze of interconnecting wiring, a fast switching
circuit creates noises in neighboring circuits due to
electromagnetic and electrostatic coupling. The cross-
talk induced depends on the transmitting voltage and
current, speed of switching and geometry of wire rout-
ing. The last item is extremely difficult to predict.
Therefore, no attempt will be made here to evaluate
the crosstalk.
* Received 1March 18,
t Electronic Data Processing Division, RCA, Camden, N. J.
16.will now be conducted according to the types of logic
Authorized licensed use limited to: UNIVERSIDAD TUCUMAN. Downloaded on August 3, 2009 at 16:18 from IEEE Xplore. Restrictions apply.
August
To insure reliable operations in a densely packaged
computer, a certain form of shielding is necessary to
eliminate or to reduce the crosstalk. The shielding of
.
wiring introduces the proximity of the ground and
therefore decreases the characteristic impedance. In
order to send signals via those cables, the logic building
blocks should have a large output current to drive the
gt
rativl l pedac e tr i line n an
ultra high speed computer the logic element should
preferably be a line driver powerful enough to feed the
line as well as the loads.
II. DESIGN CONSIDERATIONS OF BASIC LOGIC BLOCKS
Contrary to low speed circuits, the interconnection
should be studied first, before the basic logic blocks
are designed. The connecting cable is a distributed
parameter coupling network and becomes an integral
part of the computer circuitry. In other words, the
whole machine is one gigantic circuit with a high degree
of complexity.
The matching of transmission lines calls for careful
consideration. Any mismatching causes reflections
which impair the pulse waveforms. As a result, the
repetition rate has to be reduced or else erroneous logic
operations would be introduced. To maintain a good
over-all performance of the computer, the reflections
should be reduced below tolerable limits.
The proper terminations are required to match the
lines. The current demand on the driver therefore in-
creases. A driver with high output current usually is
implemented by a large input current. Such a large
input current drive can be supplied by either a power-
ful preceding stage or by an internal current amplifier.
The former case represents a low input impedance and
the latter a high input impedance. These impedances
act as loads to the transmission lines.
Due to the presence of reactive components, the in-
put current may have a higher transient magnitude
than the steady state. This high level transient current
makes it hard to match the transmission line. One
should use a current amplifier, such as an emitter
follower, at the input to reduce the driving current, in
its transient as well as its steady state.
Because the interconnection scheme and the design
of basic logic blocks influence each other, the discussion
block input impedance.
1963 Yao: Signal Transmission in Ultra High Speed Digital Conmputers 373

n-FA W >== i ~ ~~Rc A

~
B~
~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~~~

RS R ~~~~~~ZL
T E-
Fig. 1. Radial transmission line scheme. I

III. The Low INPUT IMPEDANCE AND THE RADIAL

TRANSMISSION LINE SCHEME 0 r

If the input impedance of the logic blocks is very VV

low because of the large input drive required, it im-
poses a serious matching problem on the transmission
line. The conventional way of wiring a medium speed
computer where all the loads are tapped oIn the line 7
would not be practical here. The reason is that the lo
tranismissioni line impedance would have to be im-
practically low in order to keep the reflections below a
tolerable limit.
The more efficient way is to interconinect the loads
radially, i.e., one line to each load. This of course in- Fig. 2. Reflections lattice for radial scheme.
creases the total number of lines. The radial schemne
improves the nmatching problem. Each line can be
chosen to match the load impedance which is at the tiOll of the cable length. Let us take the worst case
end of the line. where all loads have the intended maximum cable
UTnfortunately, the input impedanice varies due to length and all but one have other coincident signals even
gating. In other words, the input current changes de- though all lines are properly matched under normal
pending on the state of other gating signials. When the conditions. A diagram is shown in Fig. 1 and the re-
driving pulse reaches the gate, initially the load current flections are arranged in lattice form in Fig. 2.
may be zero because the gate has been driven by other A represents one of the receiving ends with load
signals. This condition is called "load exclusion."
Therefore, the line sees an open circuit in the beginning
exclusion, B the sendigg
end, and C the receiving end
without load exclusion The sending and receiving end
and the load impedance gradually goes down as the reflection factors are
driving pulse shares the load current, which distrib- / zo
utes among the drivers of gating signals according to R, -Zo
their voltage levels and source impedances. In order to n-l
reduce this initial reflection, a resistor termination /R1
K
Zo \
n-li ± Z0
should be put in parallel with the load and the line
impedance should be modified accordingly.
Assume that the transistor driver is connected in the rL = R - (at A, in the worst case)
common-emitter configuration. The output impedance R + ZO
is high during switching, so the reflector factor r, is
approximately +1. After the transistor is fully on, the
output impedance goes low in case of saturated mode. To = 1 + rS.
The r8 will reverse its sign and become close to -1. This Let
change of sign stabilizes the waveform rapidly, because r'= r8 + (n -2) To
the positive reflections generated by -lr8 are com- where
pensated by the negative reflections produced by -r2. faous
For a logic circuit with multiple fan-outs, the re- W=fl-us
flections are very complex. As mentioned above, the TShe reflectionl factor at C is zero because the line is
magnitude of reflection is proportional to the extent of matched. The voltage waveforms can be expressed in
mismnatching and the duration of staircases is a func- Laplace transform notation as follows:

Authorized licensed use limited to: UNIVERSIDAD TUCUMAN. Downloaded on August 3, 2009 at 16:18 from IEEE Xplore. Restrictions apply.
374 IEEE TRANSACTIONS ON ELECTRONIC COMPUTERS August
At A
Va(p) = [LVo(t)][(1 + rL)e-P(11)
+ rLr8'(1 + rL)e-P(31I + *** (1)
At B
Vb(P) = [LVo(t)] [f + rL(1 + r.')e-P(111)
+ rz'r.'(1 + r')e-P(41/) + 1- (2)
At C
Vc(p) = [LVo()] [e-P(1l) + (n - 1) TorLe-(3111) RECEIVING END
(Gate driven by other signals)
+I (n - 1) TorL2r/te-'(511l + ***], (3)
where u = traveling speed of wave, andd

Vo(t) =
n
I = E

during switching on and

Vo(t) = - load current
X impedance seen by driver during switching off
-E Zo (n - 1)Zo + R RECEIVING END
/ R\ X-= _ nR E. (Gate not driven by other signals)
(1 ) -1it,Z. Vertical Scale 1 v./Div.

Assume that the voltage drop from the collector to Horizontal Scale 10 ns/Div.
the emitter is negligible. Also, the collector capacitance Fig. 3-Waveforms of radial transmission schemie at 10 Mc.
as well as the attenuation are ignored here. With all
the parameters known, the voltage waveforms at any
point can be translated into time domain and plotted. The resultant rise time of (5) is'
For the viewpoint of signal propagation, the voltage 2 2 2
waveform at point C is of great interest. The rise time /j(/r)2 + (6)
is the same as that of the driver if the line is matched, /VC
but the fall time deteriorates due to reflections. The By assigning the resultant fall time of the waveform
d
overshoot during switching on would affect the repeti- '_desired a
at the load, the reflection factor rL can be found
tion rate if the line is too long, and the slow fall time of when the maximum length of line, and the rise and fall
switching off will definitely increase the delay time time of the driver circuit are known. Then, R and Z0
and the switching time of the load. The waveform at can be selected accordingly.
C during switching off after one trip can be written as If t.is made long, the repetition rate has to be lowered.
follows: On the other hand, a short tf can be achieved only by
Vc(t) = E n 1 R R Zo e-Clt (4) small reflection factors or by the reduction of allowable
cable length. The small reflection factors mean small
where fan-out (n), or low line impedance (Zo) and small ter-
1 1 minating resistor (R), or both. A compromise should be
C, =-In * (See Appendix I.) worked out with all those points taken into considera-
2T rLr,' tion. The following is a numerical example:
Assume that the output impedance during switching Rise and fall time of the driver are 5 ns, respectively.
is very high (which is true in case of transistors) and The load requires 14-ma input with a 3 v swing. We have
the rise time is tr, then (4) can be approximated as ZL = 214 Q
follows:
Vc(/) b=- 2. 2 X 10-9s.
b n-1I R-ZO
=E e-bf _ (e-clt - ebt) .(5)
b- b !il R ] G. E. Valley and Henry Walliman, Eds., 'VaWtcum Tube Ampli-
tiers," MNcGraw-Hill Book Co., Inc., New York, N. Y., p. 77 and p.
(See Appendix II.) 66; 1948.

Authorized licensed use limited to: UNIVERSIDAD TUCUMAN. Downloaded on August 3, 2009 at 16:18 from IEEE Xplore. Restrictions apply.
1963 Yao: Signal Transmission in Ultra High Speed Digital Computers 375

SENDING END SENDING END

RECEIVING END RECEIVING END

(Gate driven by other signals) (Gate driven by other signals)

RECEIVING END RECEIVING END

(Gate not driven by other signals) (Gate not driven by other signals)

Vertical Scale 1 v./Div. Vertical Scale 1 v./Div.

Horizontal Scale 10 ns/Div. Horizontal Scale 10 ns/Div.
Fig. 4-Waveforns of radial transmission scheme Fig. 5-Waveforms of radial transmission scheme
at 10 NIc with load exclusion. at 25 Mc with load exclusion.

A. \WC choose Then we find

n =3 R = 198, for which we may use 200 ohms
max. I = 3 ft and
resltant tf = 10 X 10s Zo = 103, for which we may use 100 ohms.
I Fig. 3 shows the above example A with same layout
- = 3 X 1.6 X 10-9s for coaxial cable. as shown in Fig. 1. Due to the use of an npn transitor,
JA the positive-going pulse discussed above is replaced by
Sul) in (6) a negative-going pulse. Accordingly the tf will be ap-
R 153 162 ohms
plied to the rising edge.
= use Fig. 4 shows the same case except two of the three
Z0 = 89 use 90 ohms. loads have "load exclusion." The waves at various points
are the worst-case forms. Fig. 5 shows the same circuit
1. WN'e choose max. I= 2 ft. operating at 25 Mc also with two out of three loads
'I'hel tf can be shortened to be 8 ns. pulled down by other drivers.

Authorized licensed use limited to: UNIVERSIDAD TUCUMAN. Downloaded on August 3, 2009 at 16:18 from IEEE Xplore. Restrictions apply.
376 IEEE TRANSACTIONS ON ELECTRONIC COMPUTERS August

SENDING END SENDING END

RECEIVING END RECEIVING END

(Gate driven by other signals) (Gate driven by other signals)

RECEIVING END RECEIVING END

(Gate not driven by other signals) (Gate not driven by other signals)
Vertical Scale 1 v./Div. Vertical Scale 1 v./Div.
Horizontal Scale 10 ns/Div. Horizontal Scale 10 ns/Div.
Fig. 6- Waveformls of radial tralisnmission scheme Fig. 7- -Wavefornis of radial transmiiissioin scheme
at 10 Mlc with R=36() ohms. at 25 Mlc with R=360 ohms.

If we choose R to be 360 ohlmis for the samne case in
order to save some driving current, theni the results are
shown in Figs. 6 and 7 operating at 10 anid 25 Mlc,
respectively.
IV. TIHE HIGH INPtTT IMPEDANCE AND TAPPED
TRANSAIISSION LINE SCHEIME
The radial transmission line scheme makes the wir-
ing quite bulky. In order to use the tapped line method,
the input circuitry of low impedance should be con-
verted into a current amplifier such as an emitter
follower.
An emitter follower demand(ls a negligible base cur-
rent in a steady state. Ilowever, it needs a transient
input current to charge the transitioni and diffusion
capacitances for switching required output current.
This input impedance behaves like an RC network. The
resistance is very high, so it canl be igniored. Theoreti-
cally, this capacitance is nonlinear. Based on the imeas-
tirement, however, it can be satisfactorily approxi-
mated by a linear capacitor.
The loads are tapped along the line. As the wave
front travels on the line, it encounters a mismatch at
every junction. The reflection factors and the trans-

Authorized licensed use limited to: UNIVERSIDAD TUCUMAN. Downloaded on August 3, 2009 at 16:18 from IEEE Xplore. Restrictions apply.
1963 Yao: Signal Transmission in Ultra High Speed Digital Computers 377

SENDING RECEIVING RECEIVING 2 RECEIVING63 RECEIVING 4

D -L- d,1I d2 d3

Rst T Z°LOAD p 0
I di -SPACING
FOR THE WORST CASE ¢, = d2 d3
MIN ALLOWABLE SPACING

TO T02~~~~~~~~~~~~~~~~~~~~~~~

r ( Z0) - of second order).

178(p) =V(p){ 1 + r(l-r~)

To ==1+ r. (8)
Let .[e-2p + To2e-2DPe 2dp + ...] } (7)
2 Vr (p) =V(p) { Toe-DP
zoc
+ r[TO2e DPe-2dP + To4e-DPe-2dp + ]
Thlerefore, we halve
r
P rr4 Toe-3 + To3e3DPe2dP + . } (8)
}E _ __ 6rT
where D is the traveling time from the driver to the
a first load and d is the traveling time between loads with
p+a (1)minimnum allowable spacing which creates the worst
reflections.
An example will be used fo)r illustrative p:urposes. As mentioned previously, the low output imlpedanlce
Assume that a line feeds 4 loads. Fig. 8 shows the re- of the saturated common-emitter transistor permits the
flections in lattice form. The voltage at the receivinlg w7aveform at the loads to settle down quickly. On the

Authorized licensed use limited to: UNIVERSIDAD TUCUMAN. Downloaded on August 3, 2009 at 16:18 from IEEE Xplore. Restrictions apply.
378 IEEE TRANSACTIONS ON ELECTRONIC COMPUTERS August
other hand, the r, stays the same after the transistor is an E -tn_1 (n -)tn-2
turned off. The reflections last longer and so the wave- L-'[V(p)To] - e
tL - a2
form when turning off is worse than when turning on.
We shall, therefore, investigate the waveform devel- (n - 1)(n - 2)t,3 1
oped upon turning off in relation to the interconnecting + 3 + j
scheme.
Notice that the r8 can be made zero if a resistor equal (n-i)!]
to the characteristic impedance of the line is placed n-1
at the sending end. One then obtains the following
equations: -e-a (r
t_ _ - -l
V8(p) = I/(p) { 1 + r[e-2DP + (To2e-2dp ± To4e-41pb -a (b-a)2
+ To6e66dP)e-2Dp] } (9) + e bt F(-l),& 1a 1)
(-

Vrl(p) = V(p){ Toe-DP + r[To2e-2dp + To4e-4dl (b - a) nj

+ To06e-6dP]e-Dp} (10) (See Appendix IV.) (13)

Vr2(P), Vr3(p), etc. A computer progranm using (9)-(10) was devised to
calculate the waveforms at the loads. The parameters
is2
TeIch
which were varied were driver rise time, load spacing,
F(n, at) and line impedance. The load impedance was realis-
To= 17(1, at) or Ton- ( ) T
tically chosen as 5 y,uf. The results checked well with
P(n, the laboratory experiments. Parts of the data have
where F(n, at) = (n-I, at)! is the incomplete gamma been plotted for illustrative purposes. As a rule, the
function. The rise time of the main wave front (for a worst waveform occurs at the first load. Therefore this
step input) is2 waveformii is used here.
en X n!_ X Zo X_C . Figs. 9-11 demonstrate the effect of load spacing.
_r
=
2n"
They have the same inputs and line inmpedance. Fig. 9
has the shortest load spacing and so it has the most
For the case of an input wave with form 1 -e-bt, the severe reflections. Figs. 12 and 13 show less reflections
resultant rise time is than Fig. 9 because of the fact that the input rise times
have been increased to 3 and 8 ns, respectively. Figs.
(tr) ±(2. 2)2 13 and 14 have the same input and load spacing. How-
2+ b (11) ever, the latter suffers from more reflections because
of the higher line impedance.
The general reflection term for a step input is as Figs. 15-22 show the worst-case reflections vs the
follows: minimum load spacing for different line impedances.
an Each plot has a constant rise time (t4) for the driver.
rTo0 = - _ tne-at. With the driver rise time known, the line impedance
n! and minimum allowable load spacing can be chosen
If the inpuit wave has the form (1 -e-bt) then the reflec- from the plotted curves so that the worst reflections
tion term becomes more complex, as follows: will not exceed a certain limit. This limit should be
designed into the noise immunity of circuits.
anb ( r t ntn-' The reflection plots also apply to cases where the
! Lb- a (b - a)2 load capacitance is other than the 5 ut,uf assumed
in this example. However, the line impedances shown
+ n(n-l)tfl2 can be calculated according to the following relation:
(b-) zo1c1
ZOC = ZoC. ZC

- e(br()1)n If the fan-out is not 4, (9)-(10) should be modified

L (b
-a)j
(See Appendix III.) (12)
~~~~and a separate set of reflection plots would be generated.
Numerical example: Assume that we have t,.-5 ns,
fan-out=4, ZL=5 ,u,f; minimum spacing of loadss 4
Likewise thle mlain transmitted wvave fronlt can be inl. Froml Fig. 17, we finld case A, Z0=50 for making
written in the following: reflection < 10 per cent, and case 13, Z, = 100) for making
reflection < 15 per cent.
.
2 L. V1. Bewvley, "Traveling \Vaves on Tranlsmissionl . Systems,' ~~Figs. 23 and 24 show the waveforms at various loca-
John W0iley- & Sons, Inc., N\ew York, NT. y., pp. 102-104; 1951. tions of loads for cases A and B, respectively.

Authorized licensed use limited to: UNIVERSIDAD TUCUMAN. Downloaded on August 3, 2009 at 16:18 from IEEE Xplore. Restrictions apply.
 ---

Z
/i

X /k
T
10.

12.

12.
11.

1_.
LOAD
~
REFLECTIONS

aeoma
~~
~

IZ =25a

RISE

T|l 7.Wort-CaseRflcionv.^LadScing
SPACING

3~~~-Inch Load Spanin;

_______ W-InRh
Load Spacing

~~~9-InchILoa nspcn

Waveform

/~~~~~LA SPCN
~~~~RISE TIME
~~~~~~~~2

at First Load for

6-Inch Load

* 1----

0 :25aQ{j
~~~~~~Z
Z~~~~~~~~~~~

9-Inch Load Spacing

MIN,~

s-I
~~~~RISE

3t
TlME:Sns

4ca S5acn
~
~

TIME

Fis

~
~

/ 8 ~ ~ v

Load
Ins
~

3" ~ ~~ ~
~ ~

Waveforml at First Load for ins Input Rise Time,

'

Waveform at First Load for lns Input Rise Time,

Walveform at First Load for lns Input Rise Time,

Spacing(Z=2 hs t~

~
ns

Waveform at First Load for lns Inp-it Rise

~
|

(Z = DP'is
I~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~t Ins[z
~

forIN
isv

~ ~~
AXREFLECTION 8.5%

~
~
~

MAX 9EFLECTION

T~ZRE

lns Input Rise

3
<

2
llllll|

ns
_

|
~
~
~

6.MAREFLECTION
FLEC
MA

/~~
na i Ris
%

Ti

3jNns

II
|
~

8%
TION E%|

1
~

3
~

~
~

0
~

Tins,

Time,

~~~~~~~~~~~~~~~~~~~~~~~NLOAD SPPACING3
~

~
~

20

-1

30
~

Z-200
0

O
1~

%r
_

3S
~
~

1||5=

16
15.
~ ~

3m
~
~

A~ ~ ~ RFLCTO
<
~~~~~~MN.LADSACN

t
5

16.
Wrt-aeRelciosv

_ _
_____200
L

Worst-Case Reflections vs Win Load Spacing for

.ns Inp.It Rise Time

Wos-Cs Reletin
3ns Inu Ris Time

-
z|
3

sI
7
Z
.
s

IN. LOAD SPACIN*G

MIN. LOAD SPACING

Worst-Case Reflections vs Min Load Spacing for

S ns Input Rise Time

Lzo25

MIN

ieTm
:0

LOA
6MNLA

SAINGn

vs
:n

Mi
WnLadSain

|
f_
r
________

Spcnio
Loa
9
o

d~~~~~~~~~~~

PCN

Authorized licensed use limited to: UNIVERSIDAD TUCUMAN. Downloaded on August 3, 2009 at 16:18 from IEEE Xplore. Restrictions apply.
 is -
-t t ----------"- _
ZR~~~~~~~~~~~~~~~~~~,

*,
5~~~~~~~~~~~~C"7
Zo. 50
Z-"25

O ~~ ~
~~3"6"9
MEN LOAD SPACING
19 W-rst-Cse RPflec-tions vs Mi Load Spa-ing for

_
~~~~~~~~~~~~~
It Io
Io
az ~ z

5
-- *Z75

2 6"
-4" l 9" ,
4"0
4 6
3 4
5 ~
~ ~ ~MIN ~
LO.D SPACING ~ ~ ~ ~ ~ DIE 3 5 9 ) n
20. Wcrat-Coso ROflr-t:n-, vs Mi. Load sparing for 2 6 6 6
20ns 1nprt Rise Ti-r
l4 LOADS
I_
_zO.,oo Fig. 23-Waveforms of tapped transmission line
,o"0 . . , _scheme at 25 Mc for case A.

EL F, St.
z~~~~~~~~~~
=------- t 1
! _____ zo . °t
___._

_ __ _ Z. ______ __ _ __

Mi.. LOAD SSPACINGl

21. Worst-Case Reflections vs Mi. Load Spa-ing for
t,40-- 30-s Inp-t Rise Tine
Es

Zo. 00

z- ._.- _Co Z-75 °

25
Fig. 24-Waveforms of tapped transmission line
C - ___________ __________ 6"__ lscheme at 25 Mc for case B.

_2. W.-iot-Ca.s_
10nto Int,at
RI lEirtins vs Mis L
Rlov r :cvf
spa,-ng for

Authorized licensed use limited to: UNIVERSIDAD TUCUMAN. Downloaded on August 3, 2009 at 16:18 from IEEE Xplore. Restrictions apply.
1963 Yao: Signal Transmission in Ultra High Speed Digital Computers 381
V. CONCLUSIONS R + (n - l)Zo
For ultra high speed computers with pulse repetition nR
rates of 10 Mc and above, the interconnecting method nR R-(n 1)Zo R + (n-l)Zo
has a dominant role in the basic logic circuit design as = k
well as the packaging. A radial transmission line scheme L nR nR
should be used if the input impedances of circuits are 2(n - 1) R-Z0o
low, e.g., for diode gating. However, in order to tap the R-[-Zo]
loads onto the line in a way similar to the conven-
tional method used in low speed machines, the high - 1 R-Zo
input impedances are mandatory. For a radial line n R
scheme, (6) is used; for a tapped line scheme, the basic
equations are (9) and (10), or (7) and (8). i
The emitter follower provides a high input impedance. R + (n - 1)Zo
However, one should beware of unwanted oscillations. Vc(t) =+
[ 1 R__+____
E
The use of a receiving end resistor is indispensable. The
sending end resistor might be eliminated, but more re- = F E 1 R___ -Z° r,' 2rL. =

flections, waveform deterioration and longer delay re- n R

sult.
One should also avoid tapping diode-input circuits At the end of nth trip
onto a line. Because this type of circuit requires a n - 1 R -Z
constant dc current drive, a highly prominent reflection Vc(t) = E - - n-IrLn-
is generated. Its magnitude is proportional to fan-out R
and its duration lasts twice the traveling time of the = ___ R -E In 1I(rLrs')
e-tl(2T) ~~~In =

cable length! This, of course, contributes more delay R

and reduces the noise immunity of the circuits. One has - 1 R -
to cut down either the transmission distance or the = E - e-tITI
number of data bits per unit time. R
As mentioned in the beginning, it is difficult to pre- n - 1 R -Z
dict crosstalk. However, one should always check for = F -e
adequate shielding. If the crosstalk is significant, then R
it should be superimposed on the waveform obtained where
by this analysis. length of cable
APPENDIX I speed of traveling wave 2n
THE DERIVATION OF (4) APPENDIX I I
From Fig. 2, we have THE DERIVATION OF (5)
R -Z (ZOn- 1) - zO 2 -n From Appendix I, for a step input
rL= _±Z e 8 (Zo/-1) + zo n Vc(t)nE-(1- R-Re-t)

To =1+ r, r =rS+(n-2)To=
n-2~~~~~~~~~~~
.E-E(1-ke-Ct). =
n
For a ramp input, we have
Let
Vc() =E- F[l - ke-clt]*[be-bt]
2n - 2
=o' (n -
1)(T=1F Ef(t ke-cit)be-b(t-1)dr
-
-

During switching-off, the voltage at C can be expressed Fe-br k l

in the following steps: E- Fbe-bt L + c -b c Jo)
At the end of first trip of signal FF,- b niRZ
~~~+(lZ
nR
n-1R-O_
n R
c-b n R b)j.
At the end of second trip 3J. F. Reintjes, and G. T. Coate, "Principles of Radar,"
Graw-Hill Book Co., Inc., New York, N. Y., p. 157; 1952. Mcq

Authorized licensed use limited to: UNIVERSIDAD TUCUMAN. Downloaded on August 3, 2009 at 16:18 from IEEE Xplore. Restrictions apply.
382 IEEE TRANSACTIONS ON ELECTRONIC COMPUTERS August
APPENDIX I I I APPENDIX IV
THE DERIVATION OF (12) I HE DERIVATION OF (13)

VrTon = EL-' L
-b
b ] VTo" = EL- FLp(p baaon
+-b) (pA+ a)nl

= EUI [~p -a- a)nb +]

b7~~2- Eanb [ - eat] [1 -e-bt
- (p + b)(p + a)n_ Eanb t t
[-a-] [e* ](-l
= -anb 17e e-a7T- dr- e- bt e-(a-b) rn-Id-r
j[E
it! e-btI (n -
=a nE -{at 1)!J -in-1 (n-)n2bea)T11
anbE t (n- 1)E1 a -a a2
=~ E fI[e-b(t-T)Tne-ar]dr(
n! + (n - 1)(n- 2)in-3
anb rt -a

n!b b-a
Lb -(b- a)2 - a-at -__ - - 1)n

1)ttL (n
Li-a (b -ea)2
n-__n
nbE i-a) n*n1 a7_)tfl3A-]
- ebt [(1) j}. A- ebn [(1)(n 2L]4.

Authorized licensed use limited to: UNIVERSIDAD TUCUMAN. Downloaded on August 3, 2009 at 16:18 from IEEE Xplore. Restrictions apply.