Name: __________________________________ Roll No: __________________

Microprocessor Interfacing
Fall 2007 Semester
Final
Total Time: 3 Hours
Total Marks: 120
Course Instructor: Dr. Waseem Ikram, Engr. Umair Ahsan,
Engr. Naveed Ul Mustafa

You are advised to READ these notes:

1. There are eight questions in all

2. The marks for each question are written in brackets [ ]

3. Exam is closed books, closed notes. Please see that the area in your threshold is
clean. You will be charged for any material which can be classified as ‘helping in
the paper’ found near you.

4. Calculator sharing is strictly prohibited.

5. The invigilator present is not supposed to answer any questions. If there is any
missing parameter, write down your assumption and continue.

1 2 3 4 5 6 7 8 Total
10 15 13 17 15 15 15 20 120

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Q.1. An 8284 clock generator chip is used to generate clock signal for a 10 MHz 8088
microprocessor. A crystal of appropriate frequency is used to generate the clock
pulses. The 8284 chip and it functional diagram are shown in fig 1.

Figure 1

a. What is the frequency of the Crystal used? ______30 MHz________ [2]

b. The Crystal is connected across pins _X1 & X2 or 17 & 16 [2]
c. F/C* pin is connected to logic (L/H) _______L_____________ [2]
d. The duration of high clock time period at CLK output is __33.33 nsec_ [2]
e. How should pins RDY1, AEN1*, RDY2, AEN2* pins be connected to allow the
8088 to work with no Wait States? RDY1 (H/L) __H__ AEN1* (H/L) __L_
RDY2 (H/L) __H__ AEN2* ___L_ [2]
(RDY1 or RDY2 has to be connected to logic H)

Q.2. Latches (74LS373) are used for buffering and de-multiplexing the 8088 processor
address-data bus. The 373 chip and the pin function table are shown in fig 2.

Microprocessor Interfacing Fall 07 Page 2 of 12

 Figure 2
The 373 is used to buffer the A8 to A15 8088 address bus.
a. OE* is connected to __________L____________ [2]
b. LE is connected to __________H____________ [2]

c. D0 to D7 pins are connected to _processor A8 to A15 lines [2]

d. Q0 to Q7 pins are connected to external address bus A8 – A15 [1]

The 373 is used to de-multiplex the A16 to A19 address bits from the S3 to S6 status
bits.
e. OE* is connected to __________L____________ [2]
f. LE is connected to __________ALE_________ [2]

g. D0 to D7 pins are connected to _processor A16S3 to A19S6__ [2]

h. Q0 to Q7 pins are connected to external address bus A16 – A19 [2]

Q.3. The data sheet of 8088 specifies the following

for 5 MHz 8088 processor TCLAV(min) = 10 nsec and TCLAV(max) = 110 nsec
for 8 MHz 8088 processor TCLAV(min) = 10 nsec and TCLAV(max) = 60 nsec

The 8 Mhz processor is connected to a RAM which is accessed by the processor

through read/write cycle extended by 1 wait state.

a. What is meant by wait state? [3]

A normal read/write bus cycle requires 4 clocks to complete. The processor can
not complete the read/write operation in 4 clocks if the access time of the memory
connected to the processor is long. The read/write cycle is extended by adding
extra clocks. The extra clocks added to extend the read/write cycle are known as
the wait states.
b. What is the access time of the RAM chip? [5]
Access time = 3T + W – TCLAV – Tsetup (Tsetup not given Tsetup = 0 assumed)
= 3(125) + 125 – 60 – 0 = 440 nsec

An 8 MHz processor with a single Wait state supports a memory with access time
of 440 nsec.
c. The 8 Mhz processor is replaced by a slower 5 Mhz processor. Will the processor
be able to access the RAM? Briefly explain with the help of calculations. [5]

Access time = 3T – TCLAV – Tsetup (Tsetup not given Tsetup = 0 assumed)

= 3(200) – 110 – 0 = 490 nsec

Microprocessor Interfacing Fall 07 Page 3 of 12

 A 5 MHz processor without a Wait state can access a RAM with access time 440
nsec.

Q.4. A small 8088 based system is designed to control the operation of a washing
machine. The specifications are as follows.
 The washing machine control program is permanently burned into a 4 KB
ROM chip
 A 2 KB RAM chip is used to support the 1 KB Interrupt Vector table and for
storing variables such as water temperature, wash load, amount of detergent
and some other program variables
 Two PPI chips are also interfaced through which the processor controls the
operation of the washing machine and senses the wash cycle variables
 Future enhancements in the control program have been allowed for by
increasing the size of RAM and ROM chips.

a. What is the difference between Isolated and Memory-mapped I/O? [3]

The 8088/8086 has 1 MB of memory space and a separate 64 KB of IO space

which is used to connect IO devices. The Isolated space is accessed through IN
and OUT instructions, whereas normal instructions are used to access the
Memory space. The IO/M* signal allows the Isolated or Memory space to be
selected.

b. Write down the address decoding table for the four devices. The two PPI’s are
memory mapped. Address decoding allows for doubling the size of RAM and
ROM for future enhancements. [6]

Device A19 – A16 A15 – A12 A11 – A8 A7 – A4 A3 – A0

2 KB RAM 0000 0000 0xxx xxxx xxxx
2 KB RAM (future) 0000 0000 1xxx xxxx xxxx
PIA 1 0000 0001 0000 0000 00xx
PIA 2 0000 0001 0000 0000 01xx
4 KB ROM (future) 1111 1110 xxxx xxxx xxxx
4 KB ROM 1111 1111 xxxx xxxx xxxx
c. Design an Address decoding circuit based on partial address decoding scheme
employing logic gates for the address decoding table above. Only three input
gates are available. Address Decoder should have the lowest gate count. [8]

Microprocessor Interfacing Fall 07 Page 4 of 12

Q.5. Auto-vectored interrupts support devices which are capable of identifying them
selves by issuing an 8-bit ID. A device which is incapable of identifying itself can
be configured to generate a unique 8-bit ID by using a 373 latch [Details of 373
latch are given in Q.2].

a. Draw a circuit which allows such a device to identify itself as ID = 83 H. The

circuit should show the connection with the processor data bus, the INTA*, INTR
and RD* signals. [10]

Mark Distribution

Data lines (device, 373,

microprocessor) [3]
INTR line [1]
RD* line [1]
INTA* line [1]
LE input [1]
373 input [3]

Microprocessor Interfacing Fall 07 Page 5 of 12

 b. If two such devices are connected with ID = 83 H and 85 H. Which of the two
devices has the highest priority? Briefly explain. [5]

The ID of the device doesn’t relate to its priority. Any of the two devices could
have the highest priority. The priority depends on the external hardware priority
circuit which allow the INTA* signal to activate the highest priority device first.

Q.6.
a. Write an assembly language program that sets the rightmost four bits of AX; clears
the leftmost three bits of AX and invert bits 7,8 and 9 of AX. [5]

or ax, 000F h
and ax, 1FFF h
xor ax, 0380 h

b. Embedded Systems Software Engineers always have at their discretion a detailed

instruction set for the processor they are writing software for. Look at the 8086
documentation for service 3Dh of DOS function calls (shown below). Write an
assembly language program that opens a file named “mydata.dat”. If the file exists
the handle for the file is saved in a two bytes variable called fPointer. If an error
occurs the Carry flag is set. If carry flag is set the error code should be saved in a
two byte variable called errCode. [10]

INT 21h / AH= 3Dh - open existing file.

Entry: AL = access and sharing modes:

mov al, 0 ; read
mov al, 1 ; write
mov al, 2 ; read/write
DS:DX -> ASCIZ filename.

Return: CF clear if successful, AX = file handle.

CF set on error, AX = error code.

note 1: file pointer is set to start of file.

note 2: file must exist.

Microprocessor Interfacing Fall 07 Page 6 of 12

 .data
file db ‘mydata.dat’ [1]
fpointer dw ? [1]
errcode dw ? [1]

.code
mov dx, offset file [1]

mov al, 0
mov ah, 3d h [1]
int 21 h [1]
jc error [1]
mov fpointer, ax [1]
jmp exit [1]
error: mov errcode, ax [1]
exit:

Q.7. 82C55 is the common PPI IC used when interfacing devices with 8086. Assume a
device attached to 8086 via 82C55 in bidirectional bus mode. Programming and
hardware details of the 82C55 are given below.

Microprocessor Interfacing Fall 07 Page 7 of 12

Microprocessor Interfacing Fall 07 Page 8 of 12
 a. Write assembly code which configures the 82C55 in the appropriate mode. [5]

mov controlport, 11000100 b ; Port A mode2, Port B Mode 1 O/P

mov controlport, 00001100 b ; INTRA disabled for output
mov controlport, 00001000 b ; INTRA disabled for input

b. Write assembly code that reads data from the device, adds FFH and transmits the
data back to the device. The processor uses the programmed IO method to access
the device and transfer data. [10]

again1:mov al, PortC ; read status (also IN al, PortC)

test al, 20 h ; check if input buffer full
jz again1 ; if not check again [4]
mov al, PortA ; read data from Port A buffer (IN al, PortA)
mov value, al ; store value temporarily in variable value
add value, 0FF h ; add FF [2]
again2: mov al, PortC ; read status (IN al, PortC)
test al, 80 h ; check if output buffer full
jz again2 ; if not check again
mov al, value
mov PortA, al ; write data to Port A (OUT PortA, al) [4]

Q.8. Two remotely placed 8051 microcontrollers are connected to each other through a
serial link. A hex keypad connected to one 8051 is used to key in a number which

Microprocessor Interfacing Fall 07 Page 9 of 12

 is transmitted to the remote 8051. The second 8051 is connected to a single digit
7-segment display which displays the number sent by the first 8051.

a. Draw a block diagram showing the connections of the first 8051 to the hex
keypad and the second 8051 to the 7-segment display. Ports should be clearly
mentioned and the correct number of bits used for connecting the devices should
be clearly drawn and labeled. [8]

b. Write 8051 assembly code which initializes the 8051 to transmit and receive at
9600 baud. FD is the count value for 9600 bauds. Timer 1 is used as a baud rate
generator. [6]

mov tmod, #20 h

mov th1, #0FD h
mov scon, #50 h
setb tr1

Microprocessor Interfacing Fall 07 Page 10 of 12

 c. Write 8051 assembly code which reads one character from the keypad and
transmits it to the remote 8051. [6]

Assuming that multiple keys are not pressed

mov R4, #4 ; four iterations to enable one column line once

mov A, #01 ; enable first column line
again: mov R1, A ; save column line
mov P0, A ; activate column line
mov A, P0 ; read row lines
cpl A ; complement A
andl A, #F0 h ; isolate row lines
jnz found ; key pressed
mov A, R1 ; no key pressed, prepare for enabling next column
RL A ; rotate left A
DJNZ R4, again ; scan next column
sjmp exit
found: orl A, R4 ; get unique key code
mov sbuf, A ; write to Transmit buffer
here: jnb T1, here ; check if transmitter ready
clr T1 ; clear transmitter flag
exit:

Format of TMOD Register.

Gate C/T M1 M2 Gate C/T M1 M2

Timer1 Timer0

M1 M2 C/T: Counter/Timer clock source

0 0 13-bit timer mode C/T = 0 Crystal frequency is Timer clock source
0 1 16-bit timer mode C/T = 1 external clock applied through Port 3 pins
1 0 8-bit Auto Reload

Microprocessor Interfacing Fall 07 Page 11 of 12

 1 1 Split Timer Mode Gate: Timer can be stopped and started

Gate = 0 through software instructions

Gate = 1 through hardware signals

Format of SCON Register

SM0 SM1 SM2 REN TB8 RB8 TI RI

 Used to program the start bit, stop bit and data bits
 SM0 & SM1 Serial Mode bits set to 01
o Serial Mode 1, 8-bit data, 1 Start bit, 1 Stop bit
 SM2 Enables multiprocessor capability SM2 = 0
 REN Receive Enable set to 1 to enable receiving of data
 TI, Transmit Interrupt raised to 1 to indicate it is ready to transmit more data
 RI, Receive Interrupt raised to 1 to indicate byte received

Microprocessor Interfacing Fall 07 Page 12 of 12