Spectre &

Virtuoso Custom Design Platform

Silicon That’s Right, On Time

K. C. Lu / Technical Leader
Cadence Taiwan

1 CADENCE DESIGN SYSTEMS, INC. CADENCE CONFIDENTIAL

Increasing Complexity
Requires a fast methodology

1993 2003
Single-chip design Disk drive controller Networking IC

Analog transistors <10K, <12 blocks >100K, >30 blocks

Digital transistors 1M w/memory >100M w/memory

Dynamic range <50dB @ <100MHz >70dB @ >100MHz

I/O 66MHz 3.125GHz

Process 0.5 micron 0.13 micron

Power 5V, single supply 3.3/1.8/1.5/1.2V

Package Standard, <$silicon Custom, >$silicon

Operating modes 1 mode ~20 distinct modes

Debug On-silicon probing On-chip test bus

Everything must be faster

2 CADENCE CONFIDENTIAL
Increasing Physical Effects
Requires silicon-accurate methodology

§ I/O density
§ IR-drop § Power density
§ Current density § Frequency
§ Electromigration § Package parasitics
§ Localized hot spots § Thermal effects
Package
Power grid § Dishing & erosion
§ Slotting, dummy metal
Interconnect § Wire distortion
§ Noise coupling
Devices
§ Glitch coupling
§ Short channel modeling Substrate § Electromigration
§ Intra-die variation § Inductance
§ Parasitic modeling
§ Sub-threshold modeling
§ Substrate parasitics
§ Multi-Vt operation
§ Noise coupling
§ Reliability modeling
§ Thermal effects

Everything must be more accurate

3 CADENCE CONFIDENTIAL
 Virtuoso Custom Platform
Fast, silicon-accurate

Spec-driven environment

Multi-mode Accelerated Silicon

World’s
Process simulation layout OpenAccess
leading design
design kits universal
foundries chain
data hub
Silicon
analysis
Advanced Developing direct
device modeling Full-chip integration link to mfg.

Silicon

4 CADENCE CONFIDENTIAL
Industry Firsts
Virtuoso custom design platform

• 1st comprehensive custom platform for 0.13µ & beyond

• 1st mixed-mode simulation with common syntax, models, & equations
• 1st mixed-mode simulation master licensing
• 1st comprehensive transistor-level silicon analysis
• 1st accelerated layout with integrated rectilinear floorplanning
• 1st full deployment of the OpenAccess database for custom design
• 1st advanced custom design methodology with baseline reference flows

5 CADENCE CONFIDENTIAL
INVENTION DESIGN STEP

Silicon Specification
Aptivia

Silicon Capture IP
Calibration Composer/Vituoso Sharing

Pro

Open Access

AMS Designer
Suite
Measurement
Analog Design Environment
Process
Design
Kits Analysis
Spectre UltraSim RF

6 CADENCE CONFIDENTIAL
AMS/DMS Designer Architecture / Flow
Incisive-SPW Incisive / System C

AMS Simulator
Spectre Circuit Incisive (NCSIM) UltraSim FastSPICE
Solver Digital Solver Solver

SimVision Debugger, Controller and Waveform Window

AMS Environment
AMSDirect Hierarchy Editor

Analog Design Assura RCX-PL DCM Aptivia

Environment Extraction Modelwriter (Future)
(Schematic) Library

7 CADENCE CONFIDENTIAL
Design Landscape + Tools
# of transistors/elements

Memory Post Layout

’s

im
SoC

Sim AM

raS
SD
Asic

esi

Ult
gne
Ultra
r Analog Blocks

al
ign
Spectre

dS
xe
Cell Spectre Mi
Characterization SpectreRF
RF

Digital Analog

8 CADENCE CONFIDENTIAL
High Level Simulation Roadmap

Q1 03 Q2 03 Q3 03 Q4 03 1H 04

HSPICE Compatibility Program

Performance Program

Foundry Program

Mixed- Mode Simulation

OA

9 CADENCE CONFIDENTIAL
Multi-mode Simulation
A new standard in speed & accuracy

Scalable simulation performance Specification-driven

environment
– Full mixed-language & level support
– 3x at full SPICE accuracy

FastSPICE
– 1000x FastSPICE within 3% accuracy

Multi-mode
simulation

SPICE
AMS
HSPICE compatibility: unplug & play

RF
Advanced Common
§ syntax
device § models
modeling § equations

10 CADENCE CONFIDENTIAL
Multi-mode Simulation
Master licensing: one investment, any
simulator

token Master license with 6 tokens Specification-driven

token – SPICE = 1 token environment
token
– RF = 2 tokens
token
– AMS = 3 tokens

FastSPICE
token

Multi-mode
simulation

SPICE
token – FastSPICE = 6 tokens

AMS

RF
Why buy standalone simulators?

Advanced Common
§ syntax
device § models
modeling § equations

11 CADENCE CONFIDENTIAL
ELECTRONIC DESIGN FOR
MANUFACTURING
Tools to solve everyday design problems

Analog Design Environment

Electronic Design for Manufacturing

Optimization Tool Monte Carlo

• Establish the initial design • Detect problem areas
Parametric Plotting Circuit Surfer Tool (as of 5.0)
Corners Analysis • Design Centering
• Explore the design space • Yield Optimization

Spectre and SpectreRF Circuit Simulator

Foundry Models Cadence PDK PDF Modeling Services

12 CADENCE CONFIDENTIAL
IC 5.0 Changes
ADE, AMS, Spectre and SpectreRF

•Analog Design Environment and AMS Designer changes

– Leapfrog (VHDL-D) support is officially ended as LDV 3.1 was last
release of Leapfrog.
– AMS Environment GUI changes may require data re-entry from
early IC 4.4.6 release
• Spectre and SpectreRF changes
– SpectreRF PDisto analysis renamed QPSS
– IC 5.0 slight modification to BSIM3v3 diode model equation
– IC 5.0 “spectre +spp” now becomes “spectrespp” to support new
MDL functionality

13 CADENCE CONFIDENTIAL
Linux Support
Product Availability

•32-bit Platform Support (RedHat 7.X)

– Chip Assembly Router (CCAR) - Q2 2002
– Spectre and Wavescan – Q4 2002
– Composer, ADE, VLE, VXL, AMS Designer, SpectreRF, NeoCell,
DIVA – Q1 2003

14 CADENCE CONFIDENTIAL
Spectre --- Memory Reduction Projects

•Optimized Resistor and Capacitor Data Structure

– Less memory, higher performance

•Reduce Inline Subcircuit Memory

– Resolve a number of issues related to excessive memory usage

•More Efficient Memory Allocation

15 CADENCE CONFIDENTIAL
Spectre --- Performance Projects (1)

•Time Step Control

– Spectre calculates a given time point 2x faster than traditional
SPICE simulator
– Default settings cause 4x the time points!
– Solution:
– Provide Better Default Settings and Circuit Specific Guidelines

•Improved Breakpoint Handling

16 CADENCE CONFIDENTIAL
Spectre --- Performance Projects (2)
• Continuous Performance Measurement
– Instrumentation and Nightly Monitoring

• Device Evaluation Multi-Threading

– 1.5x speed up for 2-Thread, up to 2.5x speed up for 4-Thread

• MOSFET Table Models

– Up to 2-4x speed up

• Optimizations
– Compiler Optimizations for Solaris, Linux, P3/P4
– Specific Code Optimization for all platforms
– Platform Specific Optimized Libraries

17 CADENCE CONFIDENTIAL
Multi-Threaded Device Evaluation

•Theoretical Max is 2.5x on 4 processors

•Assuming 80% CPU time spent on device evaluation

– 1-Thread: 20% + 80% = 100%
– 2-Thread: 20% + 40% = 60% 1.67x speedup
– 3-Thread: 20% + 27% = 47% 2.10x speedup
– 4-Thread: 20% + 20% = 40% 2.50x speedup

•80% of the simulation time is typical for BSIM3v3 and BSIM4

18 CADENCE CONFIDENTIAL
Status of Multi-Threading Project

Performance v. Thread Count

(Solaris)

3.00

2.50
Relative Performance

2.00

Theoretical
1.50 Average
Typical

1.00

0.50

0.00
1 2 3 4

Number of Threads

19 CADENCE CONFIDENTIAL
Table Models

•Conversion of MOS models to Table Lookup

– “Normal” MOS model code is compute intensive

•Table models can provide up to 2-4x performance boost

– Table Models are “characterized on-the-fly… ”
– Once calculated, the answer is stored and can be reused

20 CADENCE CONFIDENTIAL
OpenAccess
Efficient multi-domain design

System • 3x capacity versus CDBA

design • 5x faster data transfer

Embedded
Digital & D/MS Analog & A/MS RF & RF/digital Custom digital
software
OpenAccess
universal
Chip integration data hub

System
verification

Maintained existing DFII, SKILL, & ITK interfaces

§ Mixed-signal IC: 6 libraries & PDKs translated in <3 hours, no SKILL changes
§ Processor: 10 out of 150,000 lines of SKILL required changes
§ Graphics IC: third-party tool SKILL interface plugged-and-played

21 CADENCE CONFIDENTIAL
OpenAccess Benefits To
Cadence Customers

•High-performance, high-capacity for current and future large IC’s

•Highly integrated tools for Digital and Mixed-Signal IC’s
– All tools use the same database
– Eliminates GDSII and LEF/DEF between tools
•Better integration of customer and 3rd party tools
– Removes barriers of proprietary databases
•5.0.2 in Q1 2003 “Limited Release”

22 CADENCE CONFIDENTIAL
Virtuoso Custom Platform
Delivers next-generation capabilities

Great new technology…

ü Advanced device modeling
ü FastSPICE simulation … that makes business sense
ü 3x SPICE performance • Integrated into a platform
ü Specification-driven environment
• Extends your investment
ü >10x layout performance
ü Design-rule-driven layout • Available on Linux & UNIX
ü Rectilinear floorplanning • Includes compelling packaging
ü Transistor-level silicon analysis
• Delivered with baseline flows
ü Full-chip integration
ü OpenAccess database
ü…

23 CADENCE CONFIDENTIAL
謝謝 CIC 的協助
以及各位 老師 和 同學 的參與 !!