• https://spectrum.ieee.

org/semiconductors/devices/intel-
finds-moores-laws-next-step-at-10-nanometers

• https://www.edn.com/design/integrated-circuit-
design/4429282/Gate-level-simulations--verification-flow-
and-challenges

• https://www.edn.com/design/test-and-
measurement/4458672/Modified-clock-filters-improve-at-
speed-test

• http://www.newelectronics.co.uk/electronics-news/design-
challenges-for-7nm/157380/
• http://ece-
research.unm.edu/jimp/vlsi_test/slides/
• http://coreel.com/coreel-irsi-6/

• https://www.altencalsoftlabs.com/contact-us/

• https://moschip.com/contact-us/
 Module-1 Fault Modelling
• Importance of Testing –
• Testing during the VLSI Lifecycle –
• Challenges in the VLSI Testing: Test Generation –
• Fault Models –
• Levels of Abstraction in VLSI Testing –
• Historical Review of VLSI Test Technology –
• Functional Versus Structural Testing –
• Levels of Fault Models –
• Fault Equivalence –
• Fault Dominance –
• Fault Collapsing –
• Check point Theorem –
• Delay Fault.
DESIGN FOR TESTING
Fundamentals on Testing
and Design for Testability

Chap1.
 Design Verification, Testing
and Diagnosis
• Design Verification: Ascertain the design
perform its specified behavior
• Testing: Exercise the system and analyze
the response to ascertain whether it
behaves correctly
• Diagnosis: To locate the cause of
misbehavior after the incorrect behavior is
detected

Chap1.
 Some Real Defects in Chips
• Processing Faults
– missing contact windows
– parasitic transistors
– oxide breakdown
• Material Defects
– bulk defects (cracks, crystal imperfections)
– surface impurities (ion migration)
• Time-Dependent Failures
– dielectric breakdown
– electromigration
• Packaging Failures
– contact degradation
– seal leaks

Chap1.
 Scenario for Manufacture
Test
TEST VECTORS

MANUFACTURED
CIRCUIT

CIRCUIT RESPONSE
CORRECT
RESPONSES
COMPARATOR PASS/FAIL

Chap1.
 Purpose of Manufacture
Testing
• Verify Manufacture of Circuit
– Improve System Reliability
– Diminish System Cost
• Cost of repair goes up by an order of
magnitude each step away from fab line
1000

500
100

Cost
per 50
10
fault
(Dollars)
5
1

0.5
IC Board System Warranty
Test Test Test Repair

B. Davis, The Economics of Automatic Testing , McGRAW-HILL, 1982.

Chap1.
 Testing and Quality

Shipped Parts
ASIC Testing
Fabrication Yield: Quality:
Fraction of Defective parts
good parts per million (DPM)
Rejects

* Quality of shipped part is a function of

yield Y and the test (fault) coverage T.

Chap1.
 Fault Coverage

* Fault coverage T is the measure of the

ability of a set of tests to detect a given
class of faults that may occur on the
device under test.

T= # of detected faults
# of possible faults

Chap1.
 Defect Level

* Defect Level, DL is the fraction of the

shipped parts that are defective.

DL = 1 - Y (1-T )
Y: yield
T: fault coverage

Chap1.
Relating Defect Level to Fault Coverage

1
Y=.01
.9 DL = 1 -Y(1-T)
.8 Y = Yield
Y=.10
.7

.6 Y=.25
.5

.4 Y=.50
.3
Y=.75
.2
Y=.90
.1 Y=.99
0
0 10 20 30 40 50 60 70 80 90 100
Fault Coverage, T (%)

Chap1.
Defect Level, Yield and Fault Coverage

Yield Fault Coverage DPM

50% 90% 67,000
75% 90% 28,000
90% 90% 10,000
95% 90% 5,000
99% 90% 1,000

90% 90% 10,000

90% 95% 5,000
90% 99% 1,000
90% 99.9% 100

Chap1.
 ASIC

• What is ASIC: Application Specific

Integrated Circuits
– Why we need ASICs
• Microelectronic economics
– Volume
– Time to market
– Quality

Chap1.
 ASICs' Demand

* While ASIC density and complexity have

exploded, global market pressures have
increased the demand for both Quality
and Quick Turnaround .

Chap1.
Test Development Time vs. Testability
40

35

30

25

20

15

10
Measured development times
5 Extrapolated curve

0 20 40 60 80 100

Controllability and observability as a percentage of circuit covered

Chap1.
 Time-to-Market Model

Growth Stagnation Decline

Lost revenue
due to delay

Delay in Time
reaching market

* 1/8 delay of the product

lifetime reduces 1/3 revenue.

Chap1.
 Why Testing is Difficult ?

• Test application time can be exploded for

exhaustive testing of VLSI
– For a combinational circuit with 50 inputs, we need
250 = 1.126x1015 test patterns. Assume one test per
10-7sec, it takes 1.125x108sec = 3.57yrs. to test such
a circuit.
– Test generation of sequential circuits are even more
difficult.
» Lack of Controllability and Observability of
Flip-Flops (Latches)
• Functional testing may not be able to
detect the physical faults

Chap1.
 How To Do Test
• Fault Modeling
– Identify target faults
– Limit the scope of test generation
– Make analysis possible
• Test Generation
– Automatical or Manual
• Fault Simulation
– Assess completeness of tests
• Testability Analysis
– Analyze a circuit for potential problem on test
generation
• Design For Testability
– Design a circuit for guaranteed test generation
– Introduce both area overhead and performance
degradation Chap1.
The New Challenges for VLSI Testing

• Chip, Board, Module & System for high

– Performance
– Density
– Integration
– Reliability

Chap1.
Reference:

• 《Digital Systems testing and testable design》

ISBN：0－7167－8179－4 Author：Breuer
mELVIN a. etc
• 《VLSI Testing digital and mixed
analogure/digital techinques》 ISBN：085296
901 5 Author：Stanley Lhurst

Chap1.
DEC Alpha Chip (1994)

* 64-bit RISC
* 200 MHz
* 400 MIPS
* 200 Mflops
* 16.813.9-mm die
* 1.68 million Txs
* 431-pin package
* 3.3-V
* 30W power consumption.

Chap1.
 Multi-Chip Module (MCM)

* IBM Enterprise System/9000* Type 9121

Model 320
* Air-Cooled Processor Technology
* Integration of bipolar chips, CMOS SRAM
chips, and ECL & DCS logic circuitry in a TCM
(thermal conduction module)

(Ref: IBM J. RES. DEVELOP., May 1991)

Chap1.
Wafer Scale Integration (WSI)

* ELSA (European Large SIMD Array),

a wafer-scale two-dimensional array
of single-bit processors

* MUSE (Matrix Update Systolic Experiment),

MIT Lincoln Laboratory

Chap1.
 Traditional Design Flow

• Conduct testing after design

Too Large No Yes Design

Design Design Testability Testability
or for
Spec. Analysis Improvement?
Too Slow? Testability

Yes No

Done

Chap1.
The Infamous Design/Test Wall
30 years of experience proves that
test after design does not work!

Oh no!
What does
Functionally correct! this chip do?!
We're done!

Design Engineering Test Engineering

Chap1.
 New Design Mission

• Design circuit to optimally satisfy or

trade-off their design constraints in terms
of area, performance and testability.

TESTABILITY

PERFORMANCE AREA

Chap1.
 New VLSI Design Flow

No
Yes
Design Function/ Structure Logic Satisfied
Spec. Behavior Synthesis ?

Test Testable
plan Design Circuit ATPG
Rules Synthesis

TESTS
Testability Placement/
Analysis Routing

MASK

Chap1.
Introduction to VLSI Testing

李昆忠 Kuen-Jong Lee

Dept. of Electrical Engineering

National Cheng-Kung University
Tainan, Taiwan

VLSI Testing Class

 Problems to Think

How are you going to test

• A 32 bit adder

• A 32 bit counter

• A 32Mb cache memory

• A 107-transistor CPU

• A 109-transistor SOC

VLSI Testing Introduction.42 NCKUEE-KJLEE

 OUTLINE
• Introduction
• Fault modeling
• Fault simulation
• Test generation
• Automatic test pattern generation
(ATPG)
• Design for testability
• Built-in self test
• Synthesis for testability
• An example

VLSI Testing Introduction.43 NCKUEE-KJLEE

 Basic Concept of Testing
Testing: To tell whether a circuit is good or bad
VDD

0 0
0
0 0 0/1

Related fields
Verification: To verify the correctness of a
design
Diagnosis: To tell the faulty site
Reliability: To tell whether a good system will work
correctly or not after some time.
Debug: To find the faulty site and try to eliminate the fault
VLSI Testing Introduction.44 NCKUEE-KJLEE
 Why Studying Testing?
• Economics!
 Reduce test cost (enhance profit)
 Automatic test equipment (ATE) is extremely
expensive
 Shorten time-to-market
 Market dominating or sharing
 Guarantee IC quality and reliability
Defects detected in Cost
Rule of Ten: Wafer 0.01 – 0.1
Cost to detect faulty Packaged chip 0.1 – 1
IC increases by an Board 1 – 10
order of magnitude System 10 – 100
Field 100 – 1000
VLSI Testing Introduction.45 NCKUEE-KJLEE
 Principle of Testing
Input Patterns Output Response
-1011 Circuit 1-001
11-00 under 0011-
-0-1- -1101
01--0 Test 1001-
0-101 (CUT) 01-11

Stored
Correct Comparator
Response
Test Result
• Testing typically consists of
 Applying set of test stimuli (input patterns, test vectors)
to inputs of circuit under test (CUT), and
 Analyzing output responses
• The quality of the tested circuits will depend upon
the thoroughness of the test vectors
VLSI Testing Introduction.46 NCKUEE-KJLEE
 Importance of testing

N = # transistors in a chip
p = prob. (a transistor is faulty)
Pf = prob. (the chip is faulty)

Pf = 1- (1- p) N

If p = 10-6
N = 106

Pf = 63.2%

VLSI Testing Introduction.47 NCKUEE-KJLEE

 Introduction
• Integrated Circuits (ICs) have
grown in size and complexity
since the late 1950’s
 Small Scale Integration (SSI)
 Medium Scale Integration (MSI)
 Large Scale Integration (LSI)
 Very Large Scale Integration
(VLSI)
VLSI
• Moore’s Law: scale of ICs
doubles every 18 months S
M LSI
S S
 Growing size and complexity I I
poses many and new testing
challenges

VLSI Testing Introduction.48 NCKUEE-KJLEE

 Importance of Testing
• Moore’s Law results from decreasing feature
size (dimensions)
 from 10s of m to 10s of nm for transistors and
interconnecting wires
• Operating frequencies have increased from
100KHz to several GHz
• Decreasing feature size increases probability
of defects during manufacturing process
 A single faulty transistor or wire results in faulty IC
 Testing required to guarantee fault-free products

VLSI Testing Introduction.49 NCKUEE-KJLEE

 Difficulties in Testing
• Fault may occur anytime
- Design
- Process
- Package
- Field
• Fault may occur at any place
Vdd

Vss

• VLSI circuit are large

- Most problems encountered in testing are NP-complete
• I/O access is limited

VLSI Testing Introduction.50 NCKUEE-KJLEE

 How to do testing

From designer’s point of view:

• Circuit modeling Modeling
• Fault modeling

• Logic simulation
• Fault simulation ATPG
• Test generation

• Design for test Testable design

• Built-in self test

• Synthesis for testability

VLSI Testing Introduction.51 NCKUEE-KJLEE
 Circuit Modeling
• Functional model--- logic function
- f(x1,x2,...)=...
- Truth table

• Behavioral model--- functional + timing

- f(x1,x2,...)=... , Delay = 10

• Structural model--- collection of

interconnected components or elements
A E
B 1
0
G
1
C 0
D F
0

VLSI Testing Introduction.52 NCKUEE-KJLEE

 Levels of Structural Description

• Circuit level • Switch level

VDD VDD VDD
C

C C
4 1
B
C3 C2

• Gate level
A E • Higher/ System level
B
G

C
D F

VLSI Testing Introduction.53 NCKUEE-KJLEE

 Fault Modeling
• The effects of physical defects
• Most commonly used fault model: Single stuck-at
fault

A E
A s-a-1 B s-a-1 C s-a-1 D s-a-1
B A s-a-0 B s-a-0 C s-a-0 D s-a-0
G
E s-a-1 F s-a-1 G s-a-1
C E s-a-0 F s-a-0 G s-a-0
D F
14 faults
• Other fault models:
- Break faults, Bridging faults, Transistor stuck-open faults,
Transistor stuck-on faults, Delay faults

VLSI Testing Introduction.54 NCKUEE-KJLEE

 Fault Coverage (FC)
# faults detected
FC =
# faults in fault list
Example:
a 1
0
c1 6 stuck-at faults
0 ( a0,a1,b0,b1,c0,c1 )
b 1
0

Test faults detected FC

{(0,0)} c1 16.67%
{(0,1)} a1,c1 33.33%
{(1,1)} a0,b0,c0 50.00%
{(0,0),(1,1)} a0,b0,c0,c1 66.67%
{(1,0),(0,1),(1,1)} all 100.00%

VLSI Testing Introduction.55 NCKUEE-KJLEE

 Wafer Yield (Chip Yield, Yield)
Good Chip

Faulty Chip

Defects

Wafer

Wafer yield = 12/22 = 0.55 Wafer yield = 17/22 = 0.77

VLSI Testing Introduction.56 NCKUEE-KJLEE

 Testing and Quality

Shipped Parts
IC
Testing
Fabrication
Yield: Quality:
Fraction of Defective parts
good parts per million (DPM)
Rejects

• Quality of shipped parts is a function of yield

Y and the test (fault) coverage T
• Defect level (DL, reject rate in textbook):
fraction of shipped parts that are defective

VLSI Testing Introduction.57 NCKUEE-KJLEE

 Defect Level, Yield & Fault Coverage
DL: defect level
DL ～
= 1 - Y (1-T) Y: yield
T: fault coverage

Yield (Y) Fault Coverage (T) DPM (DL)

50% 90% 67,000
75% 90% 28,000
90% 90% 10,000
95% 90% 5,000
99% 90% 1,000
90% 90% 10,000
90% 95% 5,000
90% 99% 1,000
90% 99.9% 100

VLSI Testing Introduction.58 NCKUEE-KJLEE

 Logic simulation
• To determine how a good circuit should work

• Given input vectors, determine the normal

circuit response

A I C

A D B C
CC

CC
IR

1
2
B F
G
B RB
F IF
E CD C
C E E
JE

H
D E

VLSI Testing Introduction.59 NCKUEE-KJLEE

 Fault simulation

• To determine the behavior of faulty circuits

E s.a.0
A 1
0 1/0
1
B 1/0
1
G
0
C F
1
0
D

• Given a test vector, determine all faults that

are detected by this test vector.
Example:
1 Test vector (1 1) detects
A 0
C { a0 , b0 , c 1 }
B 1

VLSI Testing Introduction.60 NCKUEE-KJLEE

 Test generation
• Given a fault, identify a test to detect this fault
Example: A
1
0 1/0
D
1 1/0
B F
1
C E
0
To detect D s-a-0, D must be set to 1.
Thus A=B=1.
To propagate fault effect to the primary output
E must be 1. Thus C must be 0.
Test vector: A=1, B=1, C=0

VLSI Testing Introduction.61 NCKUEE-KJLEE

 Automatic Test Pattern Generation
 ATPG: Given a circuit, identify a set of test vectors
to detect all faults under consideration.
Input circuit

Form fault list

No
More faults? Exit

Yes
Select a fault
Fault
dropping
Test generation

Fault simulation

VLSI Testing Introduction.62 NCKUEE-KJLEE

 Difficulties in Test Generation

1. Reconvergent fanout

A 0/1 Cannot detect the fault

0 s-a-1
D 1
B 1 0 F
0/1
1 1 Fault detected
C 0E

VLSI Testing Introduction.63 NCKUEE-KJLEE

 Difficulties in Test Generation (cont.)

2. Sequential test generation

Combinational part
PIs POs

Y J
K
Y CK clk

VLSI Testing Introduction.64 NCKUEE-KJLEE

 Testable Design
• Design for testability (DFT)
• ad hoc techniques
• Scan design
• Boundary Scan

• Built-In Self Test (BIST)

• Random number generator (RNG)
• Signature Analyzer (SA)

• Synthesis for Testability

VLSI Testing Introduction.65 NCKUEE-KJLEE

 Example of ad hoc Techniques

Insert test points

MUX

T/N

VLSI Testing Introduction.66 NCKUEE-KJLEE

 Scan Design
Original design Modified design

PIs POs PIs POs

Combinational Combinational
logic logic

SO
FF SFF

FF SFF

FF SFF
T/N
VLSI Testing Introduction.67 SI NCKUEE-KJLEE
 Scan Cell Design

Q DI Q,SO
DI D Q D Q
SI
CK CK
N/T
(SE)

Q Q,SO
DI DI
F
F
SI

F FT F + FT
Most cell libraries now have scan cells!

VLSI Testing Introduction.68 NCKUEE-KJLEE

 Scan Register

Combinational
Circuits

Q D Q D Q D Q D

SO SI SI SI SI

SE
CLK

VLSI Testing Introduction.69 NCKUEE-KJLEE

 Boundary Scan
I/O Pad Boundary scan cell Boundary scan path

TRST*

TDI APPLICATION LOGIC

Sout
Misc. registers
TMS
Instruction register
T
TCK A BIST register
P Bypass register
M Scan register
TDO U Sin
X
TRST*:Test rest (Optional)
TDI: Test data input
TD0: Test data output
TCK: Test clock
TMS: Test mode select

VLSI Testing Introduction.70 NCKUEE-KJLEE

 Boundary Scan (Cont.)

TRST* TRST*

TDI Sout APPLICATION LOGIC TDI Sout APPLICATION LOGIC

Misc. registers Misc. registers

TMS TMS
Instruction register Instruction register
T T
A A
BIST register BIST register
P P
TCK Bypass register TCK Bypass register
Scan register Scan register
M M
U Sin U Sin
TDO X TDO X

TRST* TRST*

TDI APPLICATION LOGIC TDI Sout APPLICATION LOGIC

Sout
Misc. registers Misc. registers
TMS TMS
Instruction register Instruction register
T T
A A BIST register
BIST register P
P Bypass register
TCK Bypass register TCK
Scan register M
Scan register
M
U Sin U Sin
X TDO X
TDO

VLSI Testing Introduction.71 NCKUEE-KJLEE

 Built-In-Self Test (BIST)

 Places the job of device testing inside the device

itself
 Generates its own stimulus and analyzes its own
response

from system circuit to system

mux
under test

Response
generator

Analyzer
pattern

BIST good/fail
Controller

biston bistdone
VLSI Testing Introduction.72 NCKUEE-KJLEE
 Built-In-Self Test (BIST) (Cont.)

• Two major tasks

- Test pattern generation
- Test result compaction
• Usually implemented by linear feedback
shift register

F/F F/F F/F

VLSI Testing Introduction.73 NCKUEE-KJLEE

 Random Number Generator (RNG)

0001 0110 1111

1000 1011 0111
0100 0101 0011
F/F  F/F  F/F  F/F 
0010 1010 0001
1001 1101 (repeat)
1100 1110

1. Generate “pseudo” random patterns

2. Period is 2n - 1

VLSI Testing Introduction.74 NCKUEE-KJLEE

 Signature Analyzer (SA)

Input sequence 10101111 (8 bits) 1 2 3 4 5

+ + + Z
Gx   1  x 2  x 4  x 5  x 6  x 7 P x   1  x 2  x 4  x 5
Time Input stream Register contents Output stream
0 10101111 00000 Initial state
1 1010111 10000
. . .
. . .
5 101 01111
6 10 00010 1
7 1 00001 01
8 00101 101

Remainder Quotient

R x   x 2  x 4 1 x2
VLSI Testing Introduction.75 NCKUEE-KJLEE
 Signature Analyzer (SA) (cont.)
• A LFSR performs polynomial division
Px  : x 5  x 4  x 2  1
 Q x  : x 2  1
x7  x6  x 4  x 2  x5  x 4  x 2  1
 x7  x6  x5  1

Px Qx   Rx   x 7  x 6  x 5  x 4  x 2  1  Gx 

• Probability of aliasing error = 1/2n (n: # of FFs)

VLSI Testing Introduction.76 NCKUEE-KJLEE

 Memory BIST Architecture

Before After

sys_di
sys_addr data
di
sys_wen
clk
data hold_l Memory q
addr Memory
Module rst_l Module
test_h
wen si so
se

VLSI Testing Introduction.77 NCKUEE-KJLEE

 Memory BIST Architecture (Cont.)

sys_addr

Pattern Generator
Algorithm-Based
di
sys_d addr Memory data
isys_wen wen
Module
rst_l

Compressor
clk q
compress_h clk
hold_l
rst
test_h si so
se

BIST Circuitry

VLSI Testing Introduction.78 NCKUEE-KJLEE

 CPU Test Control Architecture
Scan_i
Scan_o
Scan path
Scan_en

logic

rst_l
clk
Bist Memory
hold_l
control
test_h

bist_se
compressor bist_so TDO
bist
decoder
int_scan mbist
scan
decoder
decoder
TDI

TCK IR
TAP Controller
TMS

VLSI Testing Introduction.79 NCKUEE-KJLEE

 Problems re-thinking

• A 32-bit adder --- ATPG

• A 32-bit counter --- Design for testability + ATPG

• A 32MB Cache memory --- BIST

• A 107-transistor CPU --- All test techniques

• An SOC

VLSI Testing Introduction.80 NCKUEE-KJLEE

 Conclusions
• Testing is becoming a major factor in design optimization
• Conventionally, the designer often optimize one of the three
attributes: speed, area, and power.
• At present, a fourth attribute is considered: Testability.
• Two major fields in testing
 ATPG
--- Fault simulation
--- Test generation
 Testable design
--- Design for testability
--- Built-in self-test
--- Synthesis for testability

VLSI Testing Introduction.81 NCKUEE-KJLEE

 Chapter 1

Introduction

117
 What is this chapter about?
• Introduce fundamental concepts and various
aspects of VLSI testing
• Focus on
– Importance of testing in the design and manufacturing
processes
– Challenges in test generation and fault modeling
– Levels of abstraction in VLSI testing

• Provide overview of VLSI test technology

118
 Introduction to VLSI Testing

• Introduction
• Testing During VLSI Life Cycle
• Test Generation
• Fault Models
• Levels of Abstraction
• Overview of Test Technology
• Concluding Remarks

119
 Introduction
• Integrated Circuits (ICs) have
grown in size and complexity 1.E+09
since the late 1950’s 1.E+08
– Small Scale Integration (SSI) 1.E+07

Number of Transistors
– Medium Scale Integration (MSI) 1.E+06
– Large Scale Integration (LSI) 1.E+05
– Very Large Scale Integration (VLSI) 1.E+04
• Moore’s Law: scale of ICs 1.E+03 VLSI
doubles every 18 months 1.E+02
M LSI
– Growing size and complexity poses 1.E+01
S
S S
many and new testing challenges I I
1.E+00
1960s 1970s 1980s 1990s 2000s

120
 Importance of Testing
• Moore’s Law results from decreasing feature size
(dimensions)
– from 10s of m to 10s of nm for transistors and
interconnecting wires
• Operating frequencies have increased from
100KHz to several GHz
• Decreasing feature size increases probability of
defects during manufacturing process
– A single faulty transistor or wire results in faulty IC
– Testing required to guarantee fault-free products

121
 Importance of Testing
• Rule of Ten: cost to detect faulty IC increases by
an order of magnitude as we move from:
– device  PCB  system  field operation
• Testing performed at all of these levels
• Testing also used during
– Manufacturing to improve yield
• Failure mode analysis (FMA)
– Field operation to ensure fault-free system operation
• Initiate repairs when faults are detected

122
 Testing During VLSI Life Cycle
• Testing typically consists of
– Applying set of test stimuli to
– Inputs of circuit under test (CUT), and
– Analyzing output responses
• If incorrect (fail), CUT assumed to be faulty
• If correct (pass), CUT assumed to be fault-free

Input1 Output1
Input Circuit Output
Test Under Test Response Pass/Fail
Inputn Outputm
Stimuli (CUT) Analysis

123
 Testing During VLSI Development
• Design verification
targets design errors Design Specification
– Corrections made prior
to fabrication Design Design Verification
• Remaining tests target
Fabrication Wafer Test
manufacturing defects
– A defect is a flaw or
Packaging Package Test
physical imperfection
that can lead to a fault
Quality Assurance Final Testing

124
 Design Verification
• Different levels of abstraction
during design Design Specification
– CAD tools used to synthesize
design from RTL to physical level Behavioral (Architecture) Level
• Simulation used at various
level to test for Register-Transfer Level

– Design errors in behavioral or

RTL Logical (Gate) Level

– Design meeting system timing

requirements after synthesis Physical (Transistor) Level

125
 Yield and Reject Rate
• We expect faulty chips due to manufacturing
defects
number of acceptable parts
– Called yield yield 
total number of parts fabricated
• 2 types of yield loss
– Catastrophic – due to random defects
– Parametric – due to process variations
• Undesirable results during testing
– Faulty chip appears to be good (passes test)
number of faulty parts passing final test
• Called reject rate reject rate 
total number of parts passing final test
– Good chip appears to be faulty (fails test)
• Due to poorly designed tests or lack of DFT
126
 Electronic System Manufacturing
• A system consists of
– PCBs that consist of
• VLSI devices PCB Fabrication Bare Board Test

• PCB fabrication similar to

PCB Assembly Board Test
VLSI fabrication
– Susceptible to defects Unit Assembly Unit Test

• Assembly steps also

System Assembly System Test
susceptible to defects
– Testing performed at all
stages of manufacturing
127
 System-Level Operation
S Normal system operation
1

• Faults occur 0t t1 t2 t3 t4 t
0

during system operation failures

• Exponential failure law

– Interval of normal system operation is random
number exponentially distributed
• Reliability
– Probability that system will operate normally
 t
until time t P (Tn  t )  e
– Failure rate, , is sum of individual componentk
   i
failure rates, i i 0
128
 System-Level Operation
• Mean Time Between Failures (MTBF) 
1
0
 t
• Repair time (R) also assumed to obeyMTBF  e dt 

exponential distribution
–  is repair rate P( R  t )  e  t

• Mean Time To Repair (MTTR) MTTR 

1

• Fraction of time that system is operating
normally called system availability
MTBF
– High reliability systems have availability 
system
system
MTBF  MTTR
availabilities greater than 0.9999
• Referred to as “four 9s”

129
 System-Level Testing
• Testing required to ensure system availability
• Types of system-level testing
– On-line testing – concurrent with system operation
– Off-line testing – while system (or portion of) is taken
out of service
• Performed periodically during low-demand periods
• Used for diagnosis (identification and location) of faulty
replaceable components to improve repair time

130
 Test Generation
• A test is a sequence of test patterns, called test
vectors, applied to the CUT whose outputs are
monitored and analyzed for the correct
response
– Exhaustive testing – applying all possible test
patterns to CUT
– Functional testing – testing every truth table entry
for a combinational logic CUT
• Neither of these are practical for large CUTs
• Fault coverage is a quantitative measure of
quality of a set of test vectors
131
 Test Generation
• Fault coverage for a given set of test vectors
number of detected faults
• 100% fault coverage may
fault cove  impossible due
ragebe
total number of faults
to undetectable faults

number of detected faults

fault detection efficiency 
• Reject rate =total 1 –numb
yield (1 – fault coverage)
er of faults  number of undetectable faults
– A PCB with 40 chips, each with 90% fault
coverage and 90% yield, has a reject rate of
41.9%
• Or 419,000 defective parts per million (PPM)

132
 Test Generation
• Goal: find efficient set of test vectors with
maximum fault coverage
• Fault simulation used to determine fault
coverage
– Requires fault models to emulate behavior of
defects
• A good fault model:
– Is computationally efficient for simulation
– Accurately reflects behavior of defects
• No single fault model works for all possible
defects
133
•
Fault Models
A given fault model has k types of faults
– k = 2 for most fault models
• A given circuit has n possible fault sites
• Multiple fault model –circuit can have multiple faults
(including single faults
– Number of multiple fault = (k+1)n-1
• Each fault site can have 1-of-k fault types or be fault-free
• The “-1” represents the fault-free circuit
– Impractical for anything but very small circuits
• Single fault model – circuit has only 1 fault
– Number of single faults = k×n
– Good single fault coverage generally implies good multiple
fault coverage
134
 Fault Models
• Equivalent faults
– One or more single faults that have identical
behavior for all possible input patterns
– Only one fault from a set of equivalent faults
needs to be simulated
• Fault collapsing
– Removing equivalent faults
• Except for one to be simulated
– Reduces total number of faults
• Reduces fault simulation time
• Reduces test pattern generation time
135
 Stuck-at Faults
Truth table for fault-free behavior
 Any line can be and behavior of all possible stuck-at faults
x1x2x3 000 001 010 011 100 101 110 111
 Stuck-at-0 (SA0) y 0 1 0 0 0 1 1 1
a SA0 0 1 0 0 0 1 0 0
 Stuck-at-1 (SA1) a SA1 0 1 1 1 0 1 1 1
b SA0 0 1 0 1 0 1 0 1
# fault types: k=2 b SA1 0 0 0 0 1 1 1 1
c SA0 0 0 0 0 0 0 1 1
 Example circuit: c SA1 1 1 0 0 1 1 1 1

 # fault sites: n=9

d SA0 0 1 0 0 0 1 0 0
d SA1 0 1 0 0 1 1 1 1

 # single faults =2×9=18 e

e
SA0
SA1
0
0
1
0
0
0
1
0
0
0
1
0
1
1
1
1
f SA0 0 0 0 0 0 0 1 1
x1 a f SA1 0 1 0 1 0 1 1 1
d g SA0 0 1 0 0 0 1 0 0
x2 b g g SA1 1 1 1 1 1 1 1 1
i y h SA0 0 0 0 0 0 0 1 1
h SA1 1 1 1 1 1 1 1 1
e f h i SA0 0 0 0 0 0 0 0 0
x3 c i SA1 1 1 1 1 1 1 1 1
136
 Stuck-at Faults
Truth table for fault-free behavior
 Valid test vectors and behavior of all possible stuck-at faults
 Faulty circuit differs from x1x2x3
y
000 001 010
0 1 0
011
0
100 101
0 1
110
1
111
1
good circuit a SA0 0 1 0 0 0 1 0 0
a SA1 0 1 1 1 0 1 1 1
 Necessary vectors: b SA0 0 1 0 1 0 1 0 1
b SA1 0 0 0 0 1 1 1 1
011 detects f SA1, e SA0 c SA0 0 0 0 0 0 0 1 1
100 detects d SA1 c
d
SA1
SA0
1
0
1
1
0
0
0
0
1
0
1
1
1
0
1
0
– Detect total of 10 faults d SA1 0 1 0 0 1 1 1 1
e SA0 0 1 0 1 0 1 1 1
– 001 and 110 detect e SA1 0 0 0 0 0 0 1 1
remaining 8 faults f SA0 0 0 0 0 0 0 1 1
x1 a f SA1 0 1 0 1 0 1 1 1
d g SA0 0 1 0 0 0 1 0 0
x2 b g g SA1 1 1 1 1 1 1 1 1
i y h SA0 0 0 0 0 0 0 1 1
h SA1 1 1 1 1 1 1 1 1
e f h i SA0 0 0 0 0 0 0 0 0
x3 c i SA1 1 1 1 1 1 1 1 1
137
 Stuck-at Faults
Truth table for fault-free behavior
4 sets of equivalent and behavior of all possible stuck-at faults
faults x1x2x3
y
000 001 010
0 1 0
011
0
100 101
0 1
110
1
111
1

 # collapsed faults = a
a
SA0
SA1
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
2×(PO+FO)+GI-NI b
b
SA0
SA1
0
0
1
0
0
0
1
0
0
1
1
1
0
1
1
1
 PO= # primary outputs c
c
SA0
SA1
0
1
0
1
0
0
0
0
0
1
0
1
1
1
1
1
 FO= # fanout stems d SA0 0 1 0 0 0 1 0 0
d SA1 0 1 0 0 1 1 1 1
 GI= # gate inputs e SA0 0 1 0 1 0 1 1 1
e SA1 0 0 0 0 0 0 1 1
 NI= # inverters f SA0 0 0 0 0 0 0 1 1
x1 a f SA1 0 1 0 1 0 1 1 1
d g SA0 0 1 0 0 0 1 0 0
x2 b g g SA1 1 1 1 1 1 1 1 1
i y h SA0 0 0 0 0 0 0 1 1
h SA1 1 1 1 1 1 1 1 1
e f h i SA0 0 0 0 0 0 0 0 0
x3 c i SA1 1 1 1 1 1 1 1 1
138
 Stuck-at Faults
• # collapsed faults = 2×(PO+FO)+GI-NI
– PO= number of primary outputs
– FO= number of fanout stems
– GI= total number of gate inputs
for all gates including inverters
– NI= total number of inverters
• For example circuit, # collapsed faults = 10
– PO= 1, FO= 1, GI= 7, and NI= 1
• Fault collapsing typically reduces number of
stuck-at faults by 50% - 60%
139
 VDD
Transistor Faults A P1
2-input
• Any transistor can be CMOS
B P2
Z
NOR
– Stuck-short gate N N
• Also known as stuck-short 1 2

– Stuck-open VSS
Truth table for fault-free circuit
• Also known as stuck-open and all possible transistor faults
AB 00 01 10 11
# fault types: k=2 Z 1 0 0 0

• Example circuit
N1 stuck-open 1 0 last Z 0
N1 stuck-short IDDQ 0 0 0

– # fault sites: n=4 N2 stuck-open

N2 stuck-short
1 last Z 0
IDDQ 0 0
0
0
– # single faults =2×4=8 P1 stuck-open last Z 0 0 0
P1 stuck-short 1 0 IDDQ 0
P2 stuck-open last Z 0 0 0
P2 stuck-short 1 IDDQ 0 0
140
 VDD
Transistor Faults A P1
• Stuck-short faults cause 2-input B P2
CMOS
conducting path from VDD to NOR
Z

VSS gate N N

– Can be detect by monitoring 1 2

VSS
steady-state power supply Truth table for fault-free circuit
current IDDQ and all possible transistor faults
AB 00 01 10 11
• Stuck-open faults cause Z 1 0 0 0

output node to store last N1 stuck-open

N1 stuck-short
1
IDDQ 0
0 last Z 0
0 0
voltage level N2 stuck-open 1 last Z 0 0
N2 stuck-short IDDQ 0 0 0
– Requires sequence of 2 vectors P1 stuck-open last Z 0 0 0
for detection P1 stuck-short 1 0 IDDQ 0
P2 stuck-open last Z 0 0 0
• 0010 detects N1 stuck-open P2 stuck-short 1 IDDQ 0 0
141
 Transistor Faults
• # collapsed faults = 2×T -TS+GS -TP+GP
– T = number of transistors
– TS= number of series transistors
– GS= number of groups of series transistors
– TP= number of parallel transistors
– GP= number of groups of parallel transistors
• For example circuit, # collapsed faults = 6
– T=4, TS= 2, GS= 1, TP= 2, & GP= 1
• Fault collapsing typically reduces number of
transistor faults by 25% to 35%
142
 Shorts and Opens
• Wires can be
– Open
• Opens in wires interconnecting transistors to form
gates behave like transistor stuck-open faults
• Opens in wires interconnecting gates to form circuit
behave like stuck-at faults
• Opens are detected by vectors detecting transistor and
stuck-at faults
– Short to an adjacent wire
• Also known as a bridging fault

143
 Bridging Faults AS
source
A
destination
D
• Three different models BS B
– Wired-AND/OR AS
bridging fault
D
AD AS AD
– Dominant
– Dominant-AND/OR BS BD BS BD

• Detectable by IDDQ testing Wired-AND

AS AD
Wired-OR
AS AD

AS BS 0 0 0 1 1 0 1 1 BS BD BS BD
AD BD 0 0 0 1 1 0 1 1 A dominates B B dominates A
Wired-AND 0 0 0 0 0 0 1 1 AS A AS A
Wired-OR 0 0 1 1 1 1 1 1 D D
A dominates B 0 0 0 0 1 1 1 1 BS BD BS BD
B dominates A 0 0 1 1 0 0 1 1 A dominant-AND A dominant-OR B
A dominant-AND B 0 0 0 0 1 0 1 1 AS B A AS A
B dominant-AND A 0 0 0 1 0 0 1 1 D D
A dominant-OR B 0 0 0 1 1 1 1 1 BS BD BS BD
B dominant-OR A 0 0 1 1 1 0 1 1 B dominant-AND B dominant-OR A
144 A
 Delay Faults and Crosstalk
• Path-delay fault model considers cumulative
propagation delay through CUT
– 2 test vectors create transition along path
– Faulty circuit has excessive delay
• Delays and glitches can be caused by crosstalk
between interconnect
– due to inductance and capacitive coupling
0 0 x1
0 1 x2 3

t=0 t=7 y
2
v2 v1 t=2
2
3
1 1 x3
145
Pattern Sensitivity and Coupling Faults
• Common in high density RAMs
• Pattern sensitivity fault
– Contents of memory cell is affected by
contents of neighboring cells
• Coupling fault
– Transition in contents of one memory cell
causes change in contents of another cell

146
 Pattern Sensitivity and Coupling Faults
• Common in memory cells of high density RAMs
• Pattern sensitivity fault
– Contents of cell affected by contents of neighboring cells
• Coupling fault
– Transition in one cell causes change in another cell
• Detected with specific memory test algorithms
– Background Data Sequence (BDS) used for word-oriented
memories

Notation: Test Algorithm March Test Sequence

w0 = write 0 (or all 0’s)
r1 = read 1 (or all 1’s)
↑= address up
↓= address down
↨ = address either way
147
March LR ↨(w0); ↓(r0, w1); ↑(r1, w0, r0, r0, w1);
w/o BDS ↑(r1, w0); ↑(r0, w1, r1, r1, w0); ↑(r0)
↨(w00); ↓(r00, w11); ↑(r11, w00, r00, r00, w11);
March LR ↑(r11, w00); ↑(r00, w11, r11, r11, w00);
with BDS ↑(r00, w01, w10, r10); ↑(r10, w01, r01); ↑(r01)
 Analog Fault Models
• Catastrophic faults
– Shorts and opens
• Parametric faults
– Parametric variations in passive and active
components cause components to be out of
tolerance range
• Active components can sustain defects that
affect DC and/or AC operation

148
 Levels of Abstraction
• High levels have few implementation details
needed for effective test generation
– Fault models based on gate & physical levels
• Example: two circuits for same specification
– Ckt B test vectors do not detect 4 faults in Ckt A
a SA1
f(a,b,c)=m(1,7)+d(3) = abc + abc + Xabc b
c
ab SA1 f
c 0 0 1 1 f = abc + abc
00 11 1X 0 SA1 Circuit A
Circuit A Test Vectors
1 1 {111,110,101,011,010,00
SA1
ab 0} a
c 0 0 1 1
11 1X 0 f = ab + bc b Circuit B
00
Circuit B Test Vectors f
1 1
{111,101,010,000}
149 c
 Overview of VLSI Test Technology
• Automatic Test Equipment (ATE) consists of
– Computer – for central control and flexible test
& measurement for different products
– Pin electronics & fixtures – to apply test
patterns to pins & sample responses
– Test program – controls timing of test patterns
& compares response to known good
responses

150
 Overview of VLSI Test Technology
• Automatic Test Pattern Generation (ATPG)
– Algorithms generating sequence of test vectors for a
given circuit based on specific fault models
• Fault simulation
– Emulates fault models in CUT and applies test
vectors to determine fault coverage
– Simulation time (significant due to large number of
faults to emulate) can be reduced by
• Parallel, deductive, and concurrent fault simulation

151
 Overview of VLSI Test Technology
• Design for Testability (DFT)
– Generally incorporated in design
– Goal: improve controllability and/or
observability of internal nodes of a chip or
PCB
• Three basic approaches
– Ad-hoc techniques
– Scan design
• Boundary Scan
– Built-In Self-Test (BIST)
152
 Design of Testability
• Ad-hoc DFT techniques
– Add internal test points (usually multiplexers) for
• Controllability
• Observability
– Added on a case-by-case basis
• Primarily targets “hard to test” portions of chip

Normal system Normal system

data 0 data 0
Internal Primary
Test data input node to be Internal node to output
1 be observed 1
controlled
Test mode select Test mode select
controllability test point observability test point
153
 Design for Testability
Primary Primary
Combinational Outputs
• Scan design Inputs
Logic

– Transforms flip-flops of chip

into a shift register FFs

– Scan mode facilitates 1

Di
Di Qi 0 Qi
• Shifting in test vectors FF
Qi-1
1 FF
2
• Shifting out responses Clk Scan Clk
Mode
• Good CAD tool support 3
Primary Primary
– Transforming flip-flops to Inputs Combinational Outputs
Logic
shift register Scan
– ATPG Data
Out
FFs
154
Scan Data In
 Design for Testability
• Boundary Scan – scan design applied to I/O
buffers of chip
– Used for testing interconnect on PCB
• Provides access to internal DFT capabilities
– IEEE standard 4-wire Test Access Port (TAP)
TAP pin I/O Function
tri-state control Control
BS Cell TCK input Test clock
Scan Out from IC TMS input Test Mode Select
Input Output BS Cell TDI input Test Data In
0 Output TDO output Test Data Out
0
capture update 1
Scan 1 Pad
In FF FF
Shift
Capture Update input data Input
to IC BS Cell
155
 Design for Testability
• Built-In Self-Test (BIST)
– Incorporates test pattern generator (TPG) and
output response analyzer (ORA) internal to
design
• Chip can test itself
– Can be used at all levels of testing
• Device  PCB  system  field operation
Primary Inputs
0 Circuit Primary Outputs
Under
TPG 1 Test
Pass
BIST Mode ORA
Fail
156
 Concluding Remarks
• Many new testing challenges
presented by
– Increasing size and complexity of
VLSI devices
– Decreasing feature size
• This chapter presented
introduction to VLSI testing
• Remaining chapters present more
details as well as solutions to
these challenges
157
 Fault Equivalence

• A test t distinguishes between faults a

and b if Za t   Zb t  1

• Two faults, a & b are said to be equivalent

in a circuit , iff the function under a is
equal to the function under b for any input
combination (sequence) of the circuit.
– Za t   Zb t  for all t
– No test can distinguish between a and b
– Any test which detects one of them detects all of
them

Chap1.
 Fault Equivalence

• AND gate: all s-a-0 faults are equivalent

• OR gate: all s-a-1 faults are equivalent
• NAND gate: all the input s-a-0 faults and the
output
s-a-1 faults are equivalent
• NOR gate: all input s-a-1 faults and the output
s-a-0 faults are equivalent
• Inverter: input s-a-1 and output s-a-0 are
equivalent
input s-a-0 and output s-a-1 are
equivalent

Chap1.
Equivalence Fault Collapsing

• n+2 instead of 2n+2 faults need to be

considered for n-input gates

s-a-1 s-a-1 s-a-0 s-a-1

s-a-0 s-a-0
s-a-1 s-a-0

s-a-1 s-a-1 s-a-0 s-a-1

s-a-0 s-a-0
s-a-1 s-a-0

Chap1.
 Equivalence
in a Wire

A B

* Fault equivalence:
A sao <---> B sao
A sa1 <---> B sa1

* B-sa0 and B-sa1 need not to be

considered.

Chap1.
 Fault Equivalence

• Two equivalent faults are detected by

exactly the same tests
s-a-0 s-a-1
x
x

s-a-1
x

– three faults shown are equivalent

Chap1.
Chap1.
Chap1.
Chap1.
Chap1.
Chap1.
Chap1.
 Fault Dominance

• A fault b is said to dominate another fault

a in an irredundant circuit, iff every test
(sequence) for a is also a test (sequence)
for b.
– No need to consider fault b for fault detection

Chap1.
 Fault Dominance

• AND gate: Output s-a-1 dominates any input s-

a-1
• NAND gate: Output s-a-0 dominates any input
s-a-1
• OR gate: Output s-a-0 dominates any input s-
a-0
• NOR gate: Output s-a-1 dominates any input s-
a-0
• Dominance fault collapsing: The reduction of
the set of faults to be analyzed based on
dominance relation

Chap1.
 Fault Dominance
D
x
A
C x

B
x
E

• Detect A sa1:
zt   z f t  CD CE D  CE  D  CD  1
 C  0, D  1
• Detect C sa1:
zt  z f t  CD CE D  E  1
 C  0, D  1 or C  0, E  1
C sa1 --> A sa1
• Similarly C sa1 --> B sa1
C sa0 --> A sa0
C sa0 --> B sa0
Chap1.
Equivalence & Dominance
in a Single-Gate
A B C A B C
A B C sa1 sa1 sa1sa0 sa0 sa0
A
C 00 0 1
B 01 0 1 1
10 0 1 1
11 1 0 0 0

* Fault equivalence:A sa0 <---> B sa0 <---> C sa0

* Fault dominance:C sa1 ---> A sa1
C sa1 ---> B sa1

* A-sa0 , B-sa0, and C-sa1 need not

to be considered.

Chap1.
 Fault Collapsing

• For each n-input gate, we only need to

consider n+1 faults

Chap1.
 Prime Fault

• a is a prime fault if every fault that is

dominated by a is also equivalent to a
• Representative Set of Prime Fault (RSPF)
– A set that consists of exactly one prime fault
from each equivalence class of prime faults
– True minimal RSPF is difficult to find

Chap1.
 Why Fault Collapsing?
* Memory & CPU-Time saving
===> To ease the burden for test generation
and fault simulation in testing

# of # of # of
total faultsequivalent faultsprime faults

1 60% 40%

Chap1.
 Fault Collapsing for
a Combinational Circuit

* 30 total faults ==> 12 prime faults

Chap1.
 Checkpoint Theorem

• Primary-input & Fanout-Branches

==> a sufficient and necessary set of
checkpoints in irredundant combinational
circuits

– In fanout-free combinational circuits, primary inputs

are the set of checkpoints
• Any test set which detects all signal
(multiple) stuck faults on check points will
detect all signal (multiple) stuck faults

Chap1.
 Fault Collapsing

• The set of checkpoint faults can be

further collapsed by using equivalence
and dominance relation
• Example
a
d
f
b h
e g
c

– 10 checkpoint faults
– a s-a-0 <-> d s-a-0 , c s-a-0 <-> e s-a-0
b s-a-0 -> d -> 0 , b s-a-1 -> d -> 1
– 6 tests are enough
Chap1.
Problem

1.1 If the yield of good dice is 90%, and we want a defect level not to exceed 0.1%,
what level of testing in terms of fault coverage must be achieved?

1.2 Given the market entry time verse revenue curves as shown in the figure, fill in
the following formula
1a. Lost Revenue = Total Expected Revenue * [ ];
The answer should be in term of d and w.
d is the delay entry, 2w is the product life.
The two market growth rates are the same.
1b. Given a product with total expected revenue $100M, product life is 20 months,
What is the revenue loss due to the one month late to the market?
$ Revenue

Revenue
M
Curve for ark
On Time h et
wt De
Market ro cli
Entry etG ne
ark
M

Revnue Curve for Delayed Markey Entry

TIME
Delay = d
Market Window = w

Product Life = 2w

Chap1.
1.3 For state transition fault model, explain why there are M(N-1) faults for a
M-transition N-state machine.
Similarly explain why there are NM-1 multiple state transition faults.

1.4 For PLA, there are missing crosspoints and extra crosspoints faults in both
AND-plane and OR-plane.
Can missing crosspoints be modeled as equivalent stuck-at faults? Why?
Can extra crosspoints be modeled as equivalent stuck-at faults? Why?

Chap1.
1.5 For the PLA design shown in Figure 1, construct the Karnaugh maps for Y1,Y2
and Y3 for each of the following situation.
(a) The original PLA;
(b) A shrinkage fault caused by an extra connection between bit line b2 and
product line P4;
(c) An appearance fault caused by an extra connection between P3 and Y1;
(d) A growth fault caused by the missing connection between bit line b4 and P3;
(e) A disappearance fault caused by the missing connection between P1 and Y3;
AND Plane OR Plane
b1 b2 b3 b4 b5 b6

P1=X1X2
P2=X2X3
P3=X2X3
P4=X2X3

Y3=P1+P4
Y2=P3+P4
X1 X2 X3 Y1=P1+P2
Figure 1. A PLA example
Chap1.
1.6 Prove that for combinational circuits faults dominance is a transitive relation,
i.e. if f dominates g and g dominates h, then f dominates h.

1.7 In the following circuit,

a. How many single stuck-at faults needed to be considered initially?
b. Applying the check point theorem, how many check point faults needed to be
considered?
c. Using fault dominance and fault equivalence relations to further reduce the number
of stuck-at faults? How many remaining faults needed to be considered?

a f j
b
g
m
c
h
d i
e k

Chap1.
1.8 In the circuit if any of the following tests detect the fault x1 s-a-0 ?
a. (0,1,1,1)
b. (1,0,1,1)
c. (1,1,0,1)
d. (1,0,1,0)

x1

z
x2
x3
x4

Chap1.
 Sensitization
• A test t that detects a fault f
 Activates f (or generate a fault effect) by creating
different v and vf values at the site of the fault
 Propagates the error to a primary output w by making
all the lines along at least one path between the fault
site and w have different v and vf values
• A line whose value in the test changes in the
presence of the fault f is said to be sensitized to
the fault f by the test
• A path composed of sensitized lines is called a
sensitized path

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 Detectability
• A fault f is said to be detectable if there exists a
test t that detects f ; otherwise, f is an
undetectable fault
• For an undetectable fault f, for all input x
z f  x  z x

 No test can simultaneously activate f and

create a sensitized path to a primary output

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 Undetectable Fault
1
a
G1 1/0
1

s-a-0
b 0 x
z
0
0

???
c
1
• G1 output stuck-at-0 fault is undetectable
 Undetectable faults do not change the function of
circuit
 The related circuit can be deleted to simplify the
circuit
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 Undetectable Fault
• The presence of an undetectable fault f may
prevent the detection of another fault g, even
when there exists a test which detects the fault g.
• Example:
 A detectable fault a s-a-0 becomes undetectable under
the presence of a undetectable fault c s-a-1.

a s.a.0 In fact, Z = AB + ABC = AB

A Thus the circuit can be simplified.
B
Z In general, identifying undetectable
faults can lead to simplication of
CUT
C
c s.a.1

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 Test Set

• Complete detection test set: A set of tests that

detect any detectable faults in a class
of faults
• The quality of a test set is measured by fault
coverage
• Fault coverage: Fraction of faults that are
detected by a test set
• The fault coverage can be determined by fault
simulation
 >95% is typically required for single stuck-at fault
model
in a complex system such as a CPU

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 Fault collapsing

• Fault equivalence
• Fault dominance
• Checkpoint theory

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 Fault Equivalence

• A test t distinguishes between faults a and b if

za t  zb t

• Two faults, a & b are said to be equivalent

in a circuit , iff the function under a is equal to
the function under b for any input combination
(sequence) of the circuit.
 za t  zb t  for all t
 No test can distinguish between a and b
 Any test which detects one of them detects both faults

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 Fault Equivalence

• AND gate: all s-a-0 faults are equivalent

• OR gate: all s-a-1 faults are equivalent
• NAND gate: all the input s-a-0 faults and the
output
s-a-1 faults are equivalent
• NOR gate: all input s-a-1 faults and the output
s-a-0 faults are equivalent
• Inverter: input s-a-1 and output s-a-0 are
equivalent
s.a.0
s.a.1 are
input s-a-0 and output s-a-1
Example: Three faults shown
equivalent
are equivalent s.a.1

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 Equivalence Fault Collapsing

• n+2 instead of 2n+2 faults need to be

considered for an n-input gate.

s-a-1 s-a-1 s-a-0 s-a-1

s-a-0 s-a-0
s-a-1 s-a-0

s-a-1 s-a-1 s-a-0 s-a-1

s-a-0 s-a-0
s-a-1 s-a-0

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 Fault Dominance

• A fault b is said to dominate another fault

a in an irredundant circuit, iff every test
(sequence) for a is also a test (sequence) for b.
• Notation: b  a
 No need to consider fault b for fault detection
• When two faults f1 and f2 dominate each other,
then they are equivalent
D • Detect A sa1:
sa1 zt   z f t   CD  CE  D  CE   1  C  0, D  1
sa1 A • Detect C sa1:
C z zt   z f t   CD  CE  D  E   1  C  0, D  1 or C  0, E  1
• Similarly, C sa1  A sa1, C sa1  B sa1, C sa0 
A sa0, C sa0  B sa0
E
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 Fault Dominance

• AND gate: Output s-a-1 dominates any input s-

a-1
• NAND gate: Output s-a-0 dominates any input
s-a-1
• OR gate: Output s-a-0 dominates any input s-
a-0
• NOR gate: Output s-a-1 dominates any input
s-a-0
• Dominance fault collapsing: The reduction of
the set of faults to be analyzed based on
dominance relation
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 Fault Dominance
D
x
A
C x

B
x
E

• Detect A sa1: z t   z f t   CD CE D CE  D CD 1

 C  0, D  1

• Detect C sa1: z t   z f t   CD CE D E  1

 C  0, D  1 or C  0, E  1

• Similarly C sa1 --> A sa1

C sa1 --> B sa1
C sa0 --> A sa0
C sa0 --> B sa0
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 Fault Collapsing

• For each n-input gate, we only need to consider

n+1 faults

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 Prime Faults

 a is a prime fault if every fault that is dominated

by a is also equivalent to a
• Representative Set of Prime Faults (RSPF)
 A set that consists of exactly one prime fault
from each equivalence class of prime faults
 True minimal RSPF is difficult to find

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 Why Fault Collapsing?

• Memory & CPU-Time saving

To ease the burden for test generation

and fault simulation in testing

# of # of # of
total faultsequivalent faultsprime faults

1 60% 40%

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 Fault Collapsing for
Combinational Circuit

• 30 total faults 12 prime faults

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 Checkpoint Theorem

• Primary-input & Fanout-Branches

a sufficient and necessary set of checkpoints in
irredundant combinational circuits

 In fanout-free combinational circuits, primary inputs

are the set of checkpoints
• Any test set which detects all signal (multiple)
stuck faults on check points will detect all signal
(multiple) stuck faults

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 Fault Collapsing
• The set of checkpoint faults can be further
collapsed by using equivalence and
dominance relation
• Example a
d
f
b h
e g
c

 10 checkpoint faults
 a s-a-0 d s-a-0 , c s-a-0 e s-a-0
b s-a-0 d s-a-0 , b s-a-1 d s-a-1
 6 faults are enough

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