Maheshpicarmavr 130912012611 Phpapp01

Relevance of Microcontrollers
A white paper by Sun Microsystems claims that by the

end of the decade, an average home will contain between
50 to 100 microcontrollers controlling digital phones,
microwave ovens, VCRs, televisions sets and television
remotes, dishwashers, home security systems, PDAs etc
An average car has about 15 processors

processors;; the 1999
Mercedes S-class car has 63 microprocessors,
microprocessors, while the
1999 BMW has 65 processors !
Except perhaps the human body, microprocessors and

microcontrollers have gotten into everything around us.
us.
16-05-2013 Mahesh J. vadhavaniya 1

Objectives…
Introduction
PIC Microcontroller
Development
Architecture
PIC18
PIC 18 Architecture
Features & Peripherals
ARM Microcontroller
Introduction to ARM Ltd
Programmers Model
RCT (Reverse Conducting Thyristor)
Thyristor)..

Introduction
The microcontrollers played revolutionary role in

embedded industry after the invention of Intel 8051.
8051.
The steady and progressive research in this field gave the

industry more efficient, high-
high-performance and low-low-power
consumption microcontrollers
microcontrollers..
The AVR, PIC and ARM are the prime examples

examples..
The new age microcontrollers are getting smarter and

richer by including latest communication protocols like USB,
I2C, SPI, Ethernet, CAN etc
etc..

Introduction
How Many Microcontrollers !!! ???

Who are ???
•Atmel
•NEC
•ARM
•Motorola
•Intel
•8-bit
•8-bit
•68HC05
•8XC42
•68HC08
•MCS48
•68HC11
•MCS51
•16-bit
•8xC251
•68HC12
•16-bit
•68HC16
•MCS96
•32-bit
•MXS296
•683xx
•National Semiconductor
•Texas Instruments
•COP8
•TMS370
•Microchip
•MSP430
•12-bit instruction PIC
•Zilog
•Z8
•PIC16F84
•Z86E02
PIC Chip

PIC microcontrollers
History
The PIC microcontroller was developed by General
Instruments in 1975
1975..
The PIC was developed when Microelectronics Division of

General Instruments was testing its 16
16--bit CPU CP
CP1600
1600..
Although the CP
CP1600
1600 was a good CPU but it had low I/O
performance..
performance
The PIC controller was used to offload the I/O the tasks
from CPU to improve the overall performance of the system.
system.
In 1985,
1985, General Instruments converted their
Microelectronics Division to Microchip Technology
Technology..
PIC stands for Peripheral Interface Controller.
Controller.
The General Instruments used the acronyms

Programmable Interface Controller and Programmable
Intelligent Computer for the initial PICs (PIC1640
(PIC1640 and
PIC1650
PIC1650)).
In 1993,
1993, Microchip Technology launched the 8-bit
PIC16
PIC16C
C84 with EEPROM which could be programmed using
serial programming method
method..
The improved version of PIC

PIC16
16C
C84 with flash memory
(PIC18
(PIC18F
F84 and PIC18
PIC18F
F84A)
84A) hit the market in 1998
1998..
Development
Since 1998,
1998, Microchip Technology continuously developed
new high performance microcontrollers with new complex
architecture and enhanced in-
in-built peripherals
peripherals..
PIC microcontroller is based on Harvard architecture
architecture..
At present PIC microcontrollers are widely used for
industrial purpose due to its high performance ability at low
power consumption
consumption..
It is also very famous among hobbyists due to moderate

cost and easy availability of its supporting software and
hardware tools like compilers, simulators, debuggers etc.
etc.

Development
The 8-bit PIC microcontroller is divided into following four
categories on the basis of internal architecture
architecture::
1. Base Line PIC
2. Mid-
Mid-Range PIC
3. Enhanced Mid
Mid--Range PIC
4. PIC18
PIC18
1. Base Line PIC
Base Line PICs are the least complex PIC microcontrollers.
microcontrollers.
These microcontrollers work on 12 12--bit instruction
architecture which means that the word size of instruction
sets are of 12 bits for these controllers.
controllers.

Development
1. Base Line PIC…
PIC…cntd
These are smallest and cheapest PICs, available with 6 to

40 pin packaging
packaging..
The small size and low cost of Base Line PIC replaced the
traditional ICs like 555
555,, logic gates etc.
etc. in industries.
industries.
2. Mid - Range PIC
Mid-Range PICs are based on 14

Mid- 14--bit instruction
architecture and are able to work up to 20 MHz speed
speed..
These controllers are available with 8 to 64 pin packaging

packaging..

Development
2. Mid - Range PIC…
PIC… cntd
These microcontrollers are available with different peripherals
like ADC, PWM, Op-
Op-Amps and different communication protocols
like USART, SPI, I2C (TWI), etc.
etc. which make them widely usable
microcontrollers not only for industry but for hobbyists as well.
well.
3. Enhanced Mid - Range PIC

These controllers are enhanced version of Mid
Mid--Range core.
core.
This range of controllers provides additional performance,
greater flash memory and high speed at very low power
consumption..
consumption
This range of PIC also includes multiple peripherals and supports
protocols like USART, SPI, I2C and so on
on..
Development
4. PIC 18
PIC18 range is based on 16
PIC18 16--bit instruction architecture
incorporating advanced RISC architecture which makes it
highest performer among the all 8-bit PIC families.
families.
The PIC18
PIC18 range is integrated with new age
communication protocols like USB, CAN, LIN, Ethernet
(TCP/IP protocol) to communicate with local and/or internet
based networks.
networks.
This range also supports the connectivity of Human

Interface Devices like touch panels etc.
etc.

Enhanced Mid-
Base Line Mid-Range PIC18
Range
No. of Pins 6-40 8-64 8-64 18-100
Program
Up to 3 KB Up to 14 KB Up to 28 KB Up to 128 KB
Memory
Data Memory Up to 134 Bytes Up to 368 Bytes Up to 1.5 KB Up to 4 KB
Instruction
12-bit 14-bit 14-bit 16-bit
Length
No. of
33 35 49 83
instruction set
Speed 5 MIPS* 5 MIPS 8 MIPS Up to 16 MIPS

In addition of In addition of
baseline In addition of Mid- Enhanced Mid-
• Comparator · SPI range range
• 8-bit ADC · I2C · High Performance • CAN
Feature
• Data Memory · UART · Multiple • LIN
•Internal Oscillator · PWM communication • USB
· 10-bit ADC peripherals • Ethernet
· OP-Amps • 12-bit ADC
PIC12F1XXX,
Families PIC10,PIC12, PIC16 PIC12, PIC16 PIC18
PIC16F1XXX
*MIPS stand for Millions of Instructions per Second

Development
Besides 8-bit microcontrollers, Microchip also
manufactures 1616--bit and 32
32--bit microcontrollers
microcontrollers.. Recently
Microchip developed XLP (Extreme Low Power) series
microcontrollers which are based on NanoWatt technology.
technology.
These controllers draw current in order of nanoamperes
nanoamperes((nAnA)).
Memory variations
The PIC microcontrollers are available with different

memory options which are mask ROM, EPROM and flash
memory..
memory
They are denoted with different symbols as given in the

following table
table::
Development
Memory variations
Symbol Memory Type Example
C EPROM PIC16Cxxx
CR Mask ROM PIC16CRxxx

F Flash memory PIC16Fxxx
PIC microcontrollers are also available with extended

voltage ranges which reduce the frequency range.
range.
The operating voltage range of these PICs is 2.0-6.0 volts.
volts.
The letter ‘L’ is included in controller’s name to denote
extended voltage range controllers.
controllers. For example, PIC16
PIC16LFxxx
LFxxx
(Operating voltage 2.0-6.0 volts).
volts).
Architecture
PIC microcontrollers are based on advanced RISC
architecture..
architecture
RISC stands for Reduced Instruction Set Computing.
Computing.
In this architecture, the instruction set of hardware gets
reduced which increases the execution rate (speed) of system
system..
PIC microcontrollers follow Harvard architecture for
internal data transfer.
transfer.
In Harvard architecture there are two separate memories
for program and data.
data.
These two memories are accessed through different buses
for data communication between memories and CPU core
core..
Architecture
This architecture improves the speed of system over Von
Neumann architecture in which program and data are
fetched from the same memory using the same bus.
bus.
PIC18
PIC18 series controllers are based on 16
16--bit instruction set
set..
The question may arise that if PIC18
PIC18 are called 8-bit
microcontrollers, then what about them being based on 16
16--bit
instructions set
set..
‘PIC18 is an 8-bit microcontroller’ this statement means

‘PIC18
that the CPU core can receive/transmit or process a
maximum of 8-bit data at a time.
time.

Architecture
On the other hand the statement ‘PIC ‘PIC18
18 microcontrollers
are based on 1616--bit instruction set’ means that the assembly
instruction sets are of 16
16--bit.
bit.
The data memory is interfaced with 8-bit bus and program
memory is interfaced with 16 16--bit bus as depicted in the
following figure
figure..

Architecture
Von Neumann Architecture:

Architecture:
• Fetches instructions and data
from a single memory space
• Limits operating bandwidth
Harvard Architecture
Architecture::
• Uses two separate memory
spaces for program instructions
and data
• Improved operating bandwidth
• Allows for different bus widths

PIC18
PIC18 Harvard Architecture
PIC microcontroller contains an 8-bit ALU (Arithmetic

Logic Unit) and an 8-bit Working Register (Accumulator).
(Accumulator).
There are different GPRs (General Purpose Registers) and

SFRs (Special Function Registers) in a PIC microcontroller.
microcontroller.
The overall system performs 8-bit arithmetic and logic
functions.. These functions usually need one or two operands
functions operands..
One of the operands is stored in WREG (Accumulator) and
the other one is stored in GPR/SFR
GPR/SFR..
The two data is processed by ALU and stored in WREG or
other registers

PIC18

PIC18
The process occurs in a single machine cycle.
cycle.
In PIC microcontroller, a single machine cycle consists of 4
oscillation periods
periods..
Thus an instruction needs 4 clock periods to be executed
executed..
This makes it faster than other 8051 microcontrollers
microcontrollers..
This makes it faster than other 8051 microcontrollers
microcontrollers..
Pipelining
Early processors and controllers could fetch or execute a
single instruction in a unit of time
time..
The PIC microcontrollers are able to fetch and execute the
instructions in the same unit of time thus increasing their
instruction throughput
throughput..
PIC18
Pipelining
This technique is known as instruction pipelining where the
processing of instructions is split into a number of
independent steps.
steps.

Features
C Compiler Optimized Architecture with Optional Extended
Instruction Set
100,,000 Erase/Write Cycle Enhanced Flash
100
Program Memory Typical
1,000
000,,000 Erase/Write Cycle Data EEPROM Memory
Typical
Flexible oscillator option
Four Crystal modes, including High
High--Precision PLL for USB
Two External Clock modes, Up to 48 MHz
Internal Oscillator:
Oscillator: 8 user
user--selectable frequencies, from 31 kHz
to 8 MHz
Dual Oscillator Options allow Microcontroller and USB
module to Run at different Clock Speeds
Peripherals
I/O Ports :
PIC18F
PIC18 F4550 have 5 (Port A, Port B, Port C, Port D and Port
E) 8-bit input
input--output ports
ports..
PortB & PortD have 8 I/O pins each
each..
Although other three ports are 8-bit ports but they do not
have eight I/O pins
pins..
Although the 8-bit input and output are given to these
ports, but the pins which do not exist, are masked internally
internally..
Memory :
PIC18
PIC18F
F4550 consists of three different memory sections
sections..
Peripherals
1. Flash Memory:
Memory:
Flash memory is used to store the program downloaded by
a user on to the microcontroller.
microcontroller.
Flash memory is non
non--volatile, i.e., it retains the program
even after the power is cut
cut--off
off..
PIC18
PIC18F
F4550 has 32
32KB
KB of Flash Memory.
Memory.
2. EEPROM:
EEPROM:
This is also a nonvolatile memory which is used to store
data like values of certain variables.
variables.
PIC18
PIC18F
F4550 has 256 Bytes of EEPROM.
EEPROM.
Peripherals
3. SRAM:
SRAM:
Static Random Access Memory is the volatile memory of the
microcontroller, i.e., it loses its data as soon as the power is
cut off
PIC18
PIC18F
F4550 is equipped with 2 KB of internal SRAM
SRAM.. .
Oscillator :
The PIC18
PIC18F
F series has flexible clock options.
options.
An external clock of up to 48 MHz can be applied to this
series..
series
These controllers also consist of an internal oscillator which
provides eight selectable frequency options varying from 31
KHz to 8 MHz
MHz..
Peripherals
8 x 8 Multiplier :
The PIC18
PIC18F
F4550 includes an 8 x 8 multiplier hardware
hardware..
This hardware performs the multiplications in single
machine cycle
cycle..
This gives higher computational throughput and reduces
operation cycle & code length.
length.
ADC Interface :
PIC18F
PIC18 F4550 is equipped with 13 ADC (Analog to Digital
Converter) channels of 10
10--bits resolution
resolution..

Peripherals
Timers / Counters :
PIC18
PIC18F
F4550 has four timer/counters
timer/counters..
There is one 8-bit timer and the remaining timers have
option to select 8 or 16 bit mode
mode..
Interrupts :
PIC18
PIC18F
F4550 consists of three external interrupts sources
sources..
There are 20 internal interrupts which are associated with

different peripherals like USART, ADC, Timers, and so on
on..

PIN Diagram

PIN Description
Pin
Name Description Alternate Function
No.
Vpp: programming voltage input
1 MCLR/VPP/RE3 Master clear
RE3: I/O pin of PORTE, PIN 3
2 RA0/AN0 AN0: Analog input 0
3 RA1/AN1 AN1: Analog input 1
AN2: Analog input 2

4 RA2/AN2/VREF-/CVREF VREF-: A/D reference voltage (low) input.
CVREF: Analog comparator reference output.
AN3: Analog input3

5 RA3/AN3/VREF+
Port A I/O Pins 1-6 VREF+: A/D reference voltage (high) input
T0CKI: Timer0 external clock input.
6 RA4/T0CKI/C1OUT/RCV C1OUT: Comparator 1 output
RCV: External USB transceiver RCV input.
AN4: Analog input 4
SS: SPI slave select input
7 RA5/AN4/SS/HLVDIN/C2OUT
HLDVIN: High/Low-Voltage Detect input.
C2OUT: Comparator 2 output.
PIN Description
Pin
No.
AN5: Analog input 5

8 RE0/AN5/CK1SPP
CK1SPP: SPP clock 1 output.
AN6: Analog input 6

9 RE1/AN6/CK2SPP Port E I/O Pins 1-3
CK2SPP: SPP clock 2 output
AN6: Analog input 7

10 RE2/AN7/OESPP
OESPP : SPP Enabled output
11 VDD Positive supply
12 Vss Ground
13 OSC1/CLKI Oscillator pin 1 CLKI: External clock source input
CLKO: External clock source output

14 OSC2/CLKO/RA6 Port E I/O Pin 7
OSC2: Oscillator pin 2

PIN Description
Pin
No.
T1OSO :Timer1 oscillator output

15 RC0/T1OSO/T13CKI
T13CKI: Timer1/Timer3 external clock input.
T1OSI: Timer1 oscillator output

CCP2:Capture 2 input/Compare 2 output/PWM2
16 RC1/T1OSI/CCP2/UOE
Port C I/O Pins 1-3 output
UOE: External USB transceiver OE output
CCP1: Capture 1 input/Compare 1 output/PWM1

17 RC2/CCP1/P1A output.
P1A :Enhanced CCP1 PWM output, channel A.
Internal USB 3.3V voltage regulator output, positive supply for the USB
18 VUSB
transceiver.
19 RD0/SPP0
20 RD1/SPP1 SPP0-SPP4
Port D I/O Pins 1-4
21 RD2/SPP2 Streaming Parallel Port data
22 RD3/SPP3
PIN Description
Pin
No.
D-: USB differential minus line (input/output)
23 RC3/D-/VM
VM: External USB transceiver VM input.
Port C I/O Pins 4-5
D+: USB differential plus line (input/output).
24 RC4/D+/VP
VP: External USB transceiver VP input.
TX: EUSART asynchronous transmit.
25 RC6/TX/CK
CK: EUSART synchronous clock (see RX/DT).
Port C I/O Pins 7-8 RX: EUSART asynchronous receive.
26 RC7/RX/DT/SDO DT: EUSART synchronous data (see TX/CK).
SDO: SPI data out.
27 RD4/SPP4 SPP4:Streaming Parallel Port data
SPP5:Streaming Parallel Port data
28 RD5/SPP5/P1B
P1B: Enhanced CCP1 PWM output, channel B
Port D I/O Pins 5-8 SPP6:Streaming Parallel Port data
29 RD6/SPP6/P1C
P1C: Enhanced CCP1 PWM output, channel C
SPP7:Streaming Parallel Port data
30 RD7/SPP7/P1D
P1D: Enhanced CCP1 PWM output, channel D
PIN Description
Pin
No.
31 Vss Ground
32 VDD Positive supply
AN12: Analog input 12.
INT0: External interrupt 0.
RB0/AN12/INT0/FLT0/SDI/S FLT0: Enhanced PWM Fault input (ECCP1
33
DA module).
SDI: SPI data in.
SDA: I2C data I/O.

Port B I/O Pins 1-8 INT1: External interrupt 1.
SCK: Synchronous serial clock input/output for
34 RB1/AN10/INT1/SCK/SCL
SPI mode.
SCL: Synchronous serial clock input/output for
I2C mode.

35 RB2/AN8/INT2/VMO INT2: External interrupt 2.
VMO: External USB transceiver VMO output.

PIN Description
Pin
No.
CCP2: Capture 2 input/Compare 2 output/PWM2
36 RB3/AN9/CCP2/VPO
output.
VPO: External USB transceiver VPO output.

37 RB4/AN11/KBI0/CSSPP KBI0: Interrupt-on-change pin.
CSSPP: SPP chip select control output.
KBI1: Interrupt-on-change pin.

Port B I/O Pins 1-8
38 RB5/KBI1/PGM PGM: Low-Voltage ICSP Programming enable
pin.

39 RB6/KBI2/PGC PGC: Low-Voltage ICSP Programming enable
pin.

40 RB7/KBI3/PGD PGD: In-Circuit Debugger and ICSP
programming data pin.

Block Diagram

Arithmetic Logic Unit (ALU)
Instruction decoder
16
16--bit instructions
Microprocessor Unit
Status register that stores flags
5-bits
WREG – working register
8-bit accumulator
Registers
Program Counter (PC)
21
21--bit register that holds the Program Memory address
Bank Select Register (BSR)
4-bit register used in direct addressing the Data Memory
File Select Registers (FSRs)
12
12--bit registers used as memory pointers in indirect
addressing Data Memory
Address bus
21
21--bit address bus for Program Memory
Addressing capacity
capacity:: 2 MB
12 Microprocessor Unit
12--bit address bus for Data Memory
Addressing capacity
capacity:: 4 KB
Data bus
16
16--bit instruction/data bus for Program Memory
8-bit data bus for Data Memory
PIC18
PIC18F
F452/
452/4520 Memory
Program Memory
Memory:: 32 K (Address range
range:: 000000 to 007FFFH)
007FFFH)
Data Memory:
Memory: 4 K (Address range
range:: 000 to FFFH)
Data EEPROM
Not part of the data memory space
Addressed through special function registers
Special Features
Sleep mode
Microprocessor Unit
Power--down mode
Power
Watchdog timer (WDT)

Able to reset the processor if the program is caught
in unknown state (e
(e..g., infinite loop)
Code protection
EEPROM can be protected through SFR
In
In--circuit serial programming
In
In--circuit debugger
PIC18F
PIC18 F4X2
Architecture
Block
Diagram

Embedded System
Microcontroller--based Time and Temperature System
Microcontroller

T H E A R C H I T E C T U R E F O R T H E D I G I T A L W O R
TM
47L D
The ARM Architecture
T H E A R C H I T E C T U R E F O R T H E D I G I T A L W O R
TM
48L D
ARM
The ARM is a 32- 32-bit Reduced

Instruction Set Computer (RISC
RISC))
Instruction Set Architecture (ISA
ISA))
developed by ARM Holdings
Holdings..
It was known as the Advanced RISC

Machine..
Machine

ARM Ltd
Founded in November 1990
1990..
Spun out of Acorn Computers.
Computers.
Designs the ARM range of RISC
processor cores
cores..
Licenses ARM core designs to

semiconductor partners who fabricate and
sell to their customers
customers..
ARM does not fabricate silicon itself
itself..
Also develop technologies to assist with

the design-
design-in of the ARM architecture
Software tools, boards, debug
hardware, application software, bus
architectures, peripherals etc
Licencable Architecture
Companies that are currently or formerly ARM licensees

include :
Alcatel, Apple Inc.

Inc., Atmel, Broadcom, Cirrus Logic, Digital
Equipment Corporation, Freescale
Freescale,, Intel (through DEC),
LG, Marvell Technology Group, NEC, NVIDIA, NXP
(previously Philips), Oki, Qualcomm, Samsung, Sharp, ST
Microelectronics, Symbios Logic, Texas Instruments, VLSI
Technology, Yamaha and ZiiLABS

ARM Partnership Model

Introduction
Leading provider of 32
32--bit embedded RISC
microprocessors, 75
75%% of market.
market.
High performance
Low power consumption
Low system cost
Solutions for
Embedded real
real--time systems for mass storage,
automotive, industrial and networking applications
applications..
Secure applications - smartcards and SIMs
Open platforms running complex operating systems
Low system cost

Introduction
ARMv11
ARMv
First version of ARM processor
26
26--bit addressing, no multiply / coprocessor
ARMv2
ARMv 2
First commercial chip
Included 32
32--bit result multiply instructions/coprocessor
support
ARMv2
ARMv 2a
ARM3 chip with on
ARM3 on--chip cache
Added load and store cache management
ARMv3
ARMv 3
ARM6
ARM6, 32 bit addressing, virtual memory support
support..
Development of the ARM Architecture
Improved
Halfword ARM/Thumb 5TE Jazelle
4
and signed Interworking 5TEJ
1 Java bytecode
halfword / execution
CLZ
byte support
System SA-110 Saturated maths ARM9EJ-S ARM926EJ-S
2 mode
DSP multiply-
SA-1110 ARM7EJ-S ARM1026EJ-S
accumulate
instructions
3
ARM1020E SIMD Instructions
Thumb 4T 6
instruction Multi-processing
set XScale
Early ARM V6 Memory
architectures architecture (VMSA)
ARM7TDMI ARM9TDMI ARM9E-S
Unaligned data
ARM720T ARM940T ARM966E-S support ARM1136EJ-S

ARM Processor Core
Current low
low--end ARM core for applications like digital
mobile phones
phones..
TDMI
T: Thumb, 1616--bit instruction set
D: on
on--chip Debug support, enabling the processor to
halt in response to a debug request
M: enhanced Multiplier, yield a full 64
64--bit result, high
performance
I: Embedded ICE hardware
Von Neumann architecture
3-stage pipeline

ARM Core Diagram

The Registers
ARM has 37 registers all of which are 32
32--bits long
1 dedicated program counter
1 dedicated current program status register
5 dedicated saved program status registers
30 general purpose registers
The current processor mode governs which of several banks
is accessible
accessible.. Each mode can access
a particular set of r0-r12 registers
a particular r13 (the stack pointer, sp) and r14 (the
link register)
the program counter, r15 (pc)
the current program status register, cpsr
Privileged modes (except System) can also access
a particular spsr (saved program status register)
Different States
When the processor is executing in ARM state :
All instructions are 32 bits wide

All instructions must be word aligned
When the processor is executing in Thumb state :

All instructions must be halfword aligned
When the processor is executing in Jazelle state :

Processor performs a word access to read 4 instructions at
once

Thumb
Thumb is a 16
16--bit instruction set
Optimised for code density from C code (~65 (~65%% of ARM
code size)
Improved performance from narrow memory
Subset of the functionality of the ARM instruction set
Core has additional execution state – Thumb
Switch between ARM and Thumb using BX instruction
31 0
ADDS r2,r2,#1 For most instructions generated by compiler :
32-bit ARM Instruction
Conditional execution is not used
Source and destination registers
identical
Only Low registers used
Constants are of limited size
1
5 ADD r2,#1 0 Inline barrel shifter not used
16-bit Thumb Instruction
ARM Interface Signals
mclk A[31:0]
cl ock
control wait
Din[31:0]
eclk
co nfiguration bigend Dout[31:0]
irq D[31:0] me mory

in terrupts ¼q interface
isync bl[3:0]
r /w
in itialization reset mas[1:0]
mreq
enin
enout seq
lock
enouti
abe trans
ale MMU
mode [4:0] interface
bu s ape abort
control dbe
tbe Tbit st ate
busen
highz ARM7TDMI tapsm[3:0]
busdis ir[3:0]
ecapclk core tdoen TAP
tck1 information
dbgrq
tck2
breakpt
screg[3:0]
dbgack
exec drivebs
extern1 ecapclkbs
extern0 icapclkbs
de bug dbgen highz
rangeout0 bo undary
pclkbs scan
rangeout1 rstclkbs
dbgrqi
extension
sdinbs
commrx sdoutbs
commtx shclkbs
opc shclk2bs
co processor cpi
interface cpa TRST
TCK JTAG
cpb
TMS controls
Vdd TDI
po wer
Vss TDO

Clock control
All state change within the processor are controlled by mclk,
mclk,
the memory clock
Internal clock = mclk AND \wait
eclk clock output reflects the clock used by the core
Memory interface
32
32--bit address A[
A[31
31::0], bidirectional data bus D[D[31
31::0],
separate data out Dout
Dout[[31
31::0], data in Din[
Din[31
31::0]
seq indicates that the memory address will be sequential to
that used in the previous cycle
mre q s eq Cy c l e Us e
0 0 N Non-sequential memory access
0 1 S Sequential memory access
1 0 I Internal cycle – bus and memory inactive
1 1 C Coprocessor register transfer – memory inactive

Initialization
\fiq,
fiq, fast interrupt request, higher priority
\irq,
irq, normal interrupt request
isync,, allow the interrupt synchronizer to be passed
isync
Interrupt
\reset, starts the processor from a known state,
executing from address 0000000016
ARM Characteristics
Process 0.35 um Transistors 74,209 M IPS 60
2
M etal layers 3 Core area 2.1 mm Power 87 mW
Vdd 3.3 V Clock 0 to 66 M Hz M IPS/W 690

Memory Access
The ARM is a Von Neumann,
load/store architecture, i.e.,
Only 32 bit data bus for both inst.
inst.
and data.
data.
Only the load/store instinst.. (and
SWP) access memory
Memory is addressed as a 32 bit

address space
Data type can be 8 bit (bytes), 16 bit

(half--words) or 32 bit (words), and may
(half
be seen as a byte line folded into 4-byte
words

Processor Core Vs CPU Core
Processor Core
The engine that fetches instructions and execute them
E.g.: ARM7
ARM7TDMI, ARM9
ARM9TDMI, ARM9 ARM9E-S
CPU Core
virtual address
Consists of the ARM
processor core and some
tightly coupled function MMU
instruction &
data cache
ARM7TDMI
blocks EmbeddedICE
& JTAG
Cache and memory

management blocks
address
physical
instructions & data
E.g.: ARM710
ARM710T,
T, write
buffer CP15
ARM720
ARM 720T,
T, ARM74
ARM74T,
T,
AMBA interface
ARM920
ARM 920T,
T, ARM922
ARM922T,T,
ARM940
ARM 940T,
T, ARM946
ARM946E E-S,
and ARM966
ARM966E E-S AMBA AMBA
address data
ARM710T

ARM Powered Products

Intellectual Property
ARM provides hard and soft views to licencees
RTL and synthesis flows
GDSII layout
Licencees have the right to use hard or soft views of the IP
soft views include gate level netlists
hard views are DSMs
OEMs must use hard views
to protect ARM IP
Data Sizes and Instruction Sets
The ARM is a 32
32--bit architecture
architecture..
When used in relation to the ARM:

ARM:
Byte means 8 bits
Halfword means 16 bits (two bytes)
Word means 32 bits (four bytes)
Most ARM’s implement two instruction sets :
32
32--bit ARM Instruction Set
16
16--bit Thumb Instruction Set
Jazelle cores can also execute Java byte code.

code.
Processor Modes
The ARM has seven basic operating modes :
User : unprivileged mode under which most tasks run
FIQ : entered when a high priority (fast) interrupt is raised
IRQ : entered when a low priority (normal) interrupt is

raised
Supervisor : entered on reset and when a Software

Interrupt instruction is executed
Abort : used to handle memory access violations
Undef : used to handle undefined instructions
System : privileged mode using the same registers as user

mode
The ARM Register Set
Current Visible Registers
r0
Abort
SVC
Undef
IRQ
FIQ
User Mode
Mode
Mode
Mode
Mode
Mode
r1
r2
r3 Banked out Registers
r4
r5
r6 User FIQ IRQ SVC Undef Abort
r7
r8 r8 r8
r9 r9 r9
r10 r10 r10
r11 r11 r11
r12 r12 r12
r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp)
r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr)
r15 (pc)
cpsr
spsr spsr spsr spsr spsr spsr

Register Organization Summary
User FIQ IRQ SVC Undef Abort
r0
r1
User
r2 mode
r3 r0-r7,
r4 r15, User User User User Thumb state
r5 and mode mode mode mode
cpsr r0-r12, r0-r12, r0-r12, r0-r12, Low registers
r6
r15, r15, r15, r15,
r7 and and and and
r8 r8 cpsr cpsr cpsr cpsr
r9 r9
r10 r10 Thumb state
r11 r11 High registers
r12 r12
r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp)
r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr)
r15 (pc)
cpsr
spsr spsr spsr spsr spsr
Note: System mode uses the User mode register set

ARM 7 applications

ARM 9 applications

ARM 11 applications

ARM Cortex M applications
Dell E4300 Latitude Laptop

Laptop..
instant boot
boot--up for users
and access to select
applications, with multi
multi--day
battery lifetimes.
lifetimes.
ARM Cortex A applications

ARM Cortex R

Architectures overview

ARM 7
(ARM7-TDMI-S)

ARM7
TDMI-
TDMI-S
NXP
LPC2148

ARM CortexR

TEXAS INSTRUMENTS
TI MSP430

MSP 430
Mixed--signal microcontroller family
Mixed family..
16
16--bit CPU
CPU..
Low cost, low power consumption
consumption..
Metering
etering,, wireless radio frequency engineering (RF),
battery--powered applications
battery applications..
MSP430
MSP 430x
x1xx - MSP430
MSP430xx5xx Series.
Series.
Von Neumann architecture.
architecture.
16 x 16 bit registers (including PC, SP, SR, constant
generator)..
generator)
Simple instruction set
set..
20 bit address extension
extension..
Peripherals
General--puropose I/O
General
Analog--to-
Analog to-Digital Converter
Brown Out Reset
Comparator A, A+
Digital--to-
Digital to-Analog Converter
Timers
Direct Memory Access Controller
ESP430
ESP 430 (integrated in FE42
FE42xx
xx devices)
LCD/LCD_A/LCD_B
Op Amps
Hardware multiplier
AVR Microcontroller Family

AVR General Features
Enhanced RISC architecture with mostly fixed
fixed--length
instruction, load
load--store memory access and 32 general-
general-
purpose registers
registers..
A two
two--stage instruction pipeline that speeds up execution
execution..
Majority of instructions take one clock cycle.

cycle.
Up to 10
10--MHz clock operation.
operation.
Wide variety of on
on--chip peripherals,
peripherals, including digital I/O,
ADC, EEPROM, Timer, UART, RTC timer, PWM etc
etc..
Internal program and data memory

memory..
AVR General Features
In
In--System programmable (ISP
ISP)).
Available in 8-pin to 64
64--pin size to suit wide variety of
applications..
applications
Up to 12 times performance speedup over conventional

CISC controllers.
controllers.
Wide operating voltage from 2.7 V to 6.0 V.
Simple architecture offers a small learning curve to the

uninitiated..
uninitiated

What does AVR RISC mean ?
The acronym AVR has been reported to stand for

for::
Advanced Virtual RISC and also for the chip's designers
designers::
Alf--Egil Bogen and Vegard Wollan who designed the basic
Alf
architecture at the Norwegian Institute of Technology
Technology..
RISC stands for Reduced Instruction Set Computer.

Computer.
CPU design with a reduced instruction set as well as a

simpler set of instructions (like for example PIC and AVR)

Manufacturers
Intel, Freescale,
Freescale, Microchip (PIC), TI, Zilog.
Zilog.
Atmel AVR :
Many Types, tinyAT,
tinyAT, megaAT,
megaAT, automotive
Lighting, LCD
Share unified platform
Different #s of I/O control
Built--in Pull
Built Pull--up resistors
Ethernet, Serial Data, Auxiliary Power, USB
Analog I/O, Packaging, Interrupts, Math, JTAG
Get the right amount of memory for the job

AVR Growing Family
Tiny AVR family
8 – 32 pin general purpose microcontrollers
microcontrollers..
16 family members.
members.
MEGA AVR family
32 - 100 pin general purpose
microcontrollers..
microcontrollers
23 family members.
members.
ASSP AVRs
USB, CAN and LCD
Motor Control and Lighting
Automotive
Battery Management
8 family members.
members.
AVR Architecture

AVR – A Single Chip Solution

AVR – A Single Chip Solution

High – Level Integration

AVR Mega 8 Features
8-Kbyte self-
self-programming
Flash Program Memory
1-Kbyte SRAM
512 Byte EEPROM
6 or 8 Channel 10
10--bit A/D
A/D--
converter..
converter
Up to 16 MIPS throughput
at 16 Mhz.
Mhz.
2.7 - 5.5 Volt operation.

operation.
AT Mega 8 Pinout

ATMega 16 Features
131 Instructions
32 8-bit GP registers
Throughput up to 16 MIPS
16
16K
K programmable flash (instructions)
512Bytes
512 Bytes EEPROM
1K internal SRAM
Timers, serial and parallel I/O, ADC

AVR CPU
PC : address of next
instruction
IR: pre-
pre-fetched
instruction
ID: current instruction
GPR: R0-
R0-R31
ALU

AVR Memory
Flash: Machine
instructions go here
SRAM: For runtime
data
Note bus
independence for
data and instructions
EEPROM: Secondary
storage
EEPROM and Flash
memories have a
limited lifetime of
erase/write cycles
Flash Memory
Programs reside in word addressable flash storage
Word addresses range from 0000-
0000-1FFF (PC is 13
bits)
Byte addresses range 0000-
0000-3FFF (0x4000=16K)
Harvard Architecture
It is possible to use this storage area for constant
data as well as instructions, violating the true spirit
of this architecture
Instructions are 16 or 32-

32-bits
Most are 16-
16-bits and are executed in a single clock
cycle

SRAM
The ATMega16 has 1K (1024 bytes) of byte addressable

static RAM
This is used for variable storage and stack space

during execution
SRAM addresses start at $0060 and go through

$045F
• The reason for not starting at zero will be

covered later

Clock
All processors are pushed through their fetch execute cycle
by an alternating 0-1 signal, called a clock
The ATMega16
ATMega16 can use an internal or external clock
signal
Clock signals are usually generated by an RC

oscillator or a crystal
• The internal clock is an RC oscillator

programmable to 1, 2, 4, or 8 MHz
• An external clock signal (crystal controlled) can

be more precise for time critical applications
AVR Machine Language
AVR instructions are 16 or 32-
32-bits.
Each instruction contains an opcode

opcode..
Opcodes generally are located in the initial bits of

an instruction.
Some instructions have operands encoded in the

remaining bits.
Opcode and operands are numbers, but their

containers are simply some of the bits in the
instruction.
AVR 8 – bit RISC High Performance
True single cycle execution

Single--clock-
Single clock-cycle-
cycle-per-
per-instruction execution
One MIPS (mega instructions per second) per MHz

Up to 20 MHz clock
32 general purpose registers
provide flexibility and performance when using
high level languages
prevents access to RAM
Harvard architecture
separate bus for program and data memory

AVR 8 – bit RISC Low Power Consumption
1.8 to 5.5V operation
will use all the energy stored in your batteries
A variety of sleep modes
AVR Flash microcontrollers have up to six different

sleep modes
fast wake-
wake-up from sleep modes
Software controlled frequency

AVR 8 – bit RISC Compatibility
AVR® Flash microcontrollers share a single core

architecture
use the same code for all families
1 Kbytes to 256 Kbytes of code
8 to 100 pins
all devices have
Internal oscillators

AVR 8 – bit RISC pico Power Technology
“Pico Power enables AVR to achieve the industry’s

lowest power consumption with 650 nA with a RTC (real
time clock) running and 100nA
100nA in Power Down sleep”
True 1.8V Supply Voltage
Minimized Leakage Current
Ultra Low Power 32 kHz Crystal Oscillator
Digital Input Disable Registers
Power Reduction Register

Code Size and Execution Time
MSP430 and AVR are running a close race.

But max speed on MSP430 is only 8 MHz.
The C51 would have to run at 296 MHz to match the 16 MHz
AVR.
PIC 18 seems fast but requires 3 times as much code space.

Comparison of Code Size

Real Life Applications
Complete Navigation Application

Application..
C bitfields
bitfields..
Car Radio Control
Control..
DES Encryption / Decryption.
Decryption.
Three different modules from analog telephones
telephones..
Reed – Solomon (error correction) encoder / decoder.
decoder.
Pager Protocol.
Protocol.
Refrigerator Control
Control..
Battery Charger.
Charger.
Embedded Web Server.
Server.
Label / Recite printer.
printer.

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Relevance of Microcontrollers

A white paper by Sun Microsystems claims that by the

An average car has about 15 processors

Except perhaps the human body, microprocessors and

16-05-2013 Mahesh J. vadhavaniya 1

16-05-2013 Mahesh J. vadhavaniya 2

The microcontrollers played revolutionary role in

The steady and progressive research in this field gave the

The AVR, PIC and ARM are the prime examples

The new age microcontrollers are getting smarter and

16-05-2013 Mahesh J. vadhavaniya 3

16-05-2013 Mahesh J. vadhavaniya 4

16-05-2013 Mahesh J. vadhavaniya 6

The PIC was developed when Microelectronics Division of

The General Instruments used the acronyms

The improved version of PIC

It is also very famous among hobbyists due to moderate

16-05-2013 Mahesh J. vadhavaniya 9

16-05-2013 Mahesh J. vadhavaniya 10

These are smallest and cheapest PICs, available with 6 to

2. Mid - Range PIC

Mid-Range PICs are based on 14

These controllers are available with 8 to 64 pin packaging

16-05-2013 Mahesh J. vadhavaniya 11

3. Enhanced Mid - Range PIC

This range also supports the connectivity of Human

16-05-2013 Mahesh J. vadhavaniya 13

Data Memory Up to 134 Bytes Up to 368 Bytes Up to 1.5 KB Up to 4 KB

Speed 5 MIPS* 5 MIPS 8 MIPS Up to 16 MIPS

16-05-2013 Mahesh J. vadhavaniya 15

The PIC microcontrollers are available with different

They are denoted with different symbols as given in the

CR Mask ROM PIC16CRxxx

PIC microcontrollers are also available with extended

‘PIC18 is an 8-bit microcontroller’ this statement means

16-05-2013 Mahesh J. vadhavaniya 19

16-05-2013 Mahesh J. vadhavaniya 20

Von Neumann Architecture:

16-05-2013 Mahesh J. vadhavaniya 21

PIC microcontroller contains an 8-bit ALU (Arithmetic

There are different GPRs (General Purpose Registers) and

16-05-2013 Mahesh J. vadhavaniya 22

16-05-2013 Mahesh J. vadhavaniya 23

16-05-2013 Mahesh J. vadhavaniya 25

16-05-2013 Mahesh J. vadhavaniya 30

There are 20 internal interrupts which are associated with

16-05-2013 Mahesh J. vadhavaniya 31

16-05-2013 Mahesh J. vadhavaniya 32

AN2: Analog input 2

AN3: Analog input3

AN5: Analog input 5

AN6: Analog input 6

AN6: Analog input 7

11 VDD Positive supply

13 OSC1/CLKI Oscillator pin 1 CLKI: External clock source input

CLKO: External clock source output

16-05-2013 Mahesh J. vadhavaniya 34

T1OSO :Timer1 oscillator output

T1OSI: Timer1 oscillator output

CCP1: Capture 1 input/Compare 1 output/PWM1

AN10: Analog input 10.

AN8: Analog input 8.

16-05-2013 Mahesh J. vadhavaniya 37