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Designer’s Guide
4N45/6 HCPL-2400/11/30
6N135/6/7/8/9 HCPL-2502/30/31
HCPL-0201/11 HCPL-2601/02/11/12/
HCPL-0452/3 30/31
HCPL-0500/1 HCPL-2730/1 HCPL-314J/315J HCPL-7800/A
HCPL-0600/01/11 HCPL-3700/60 HCPL-316J HCPL-7840
HCPL-0700/1 HCPL-4100/4200 HCPL-7601/11 HCPL-788J
HCPL-2200/01/02/11/ HCPL-4502/03/34/62 HCPL-7710 HSSR-8060/8400
12/19/31/32 HCPL-4661 HCPL-7720/1
HCPL-2300
5,000 5,000
WEAR-OUT REGION WEAR-OUT REGION
4,500 4,500
4,000 4,000
SAFE SAFE
OPERATING OPERATING
3,500 3,500 REGION FOR
REGION FOR
TRANSIENT TRANSIENT
3,000 INPUT-OUTPUT 3,000 INPUT-OUTPUT
VOLTAGE VOLTAGE
2,500 2,500
2,000 2,000
1,500 ENDURANCE VOLTAGE – 800 Vac 1,500 ENDURANCE VOLTAGE – 800 Vac
(NOTE: FOR DC OPERATION, (NOTE: FOR DC OPERATION,
ENDURANCE VOLTAGE IS 1000 Vdc)
1,000 1,000 ENDURANCE VOLTAGE IS 1000 Vdc
500 500
SAFE OPERATING REGION FOR CONTINUOUS SAFE OPERATING REGION FOR CONTINUOUS
INPUT-OUTPUT VOLTAGE INPUT-OUTPUT VOLTAGE
0 0
0.01 0.1 1 10 100 1,000 10,000 100,000 0.01 0.1 1 10 100 1,000 10,000 100,000
Figure 1. Recommended Safe Operating Area for Input-Output Figure 2. Recommended Safe Operating Area for Input-Output
Voltage-Endurance Voltage for Category 1 Optocouplers. Voltage-Endurance Voltage for Category 2 Optocouplers.
Category 3 Optocouplers:
INSULATION
4,000 SAFE
OPERATING
3,500 REGION FOR
TRANSIENT
3,000 INPUT-OUTPUT
VOLTAGE
2,500
2,000
ENDURANCE VOLTAGE – 800 Vac
DETECTOR
1,500
(NOTE: FOR DC OPERATION,
ENDURANCE VOLTAGE IS 1000 Vdc)
1,000
500 EXTERNAL
SAFE OPERATING REGION FOR CONTINUOUS
INPUT-OUTPUT VOLTAGE CLEARANCE
0
0.01 0.1 1 10 100 1,000 10,000 100,000
WARNING: In all cases where regulatory compliance is required, working voltage as defined by the regulatory agency cannot be exceeded.
Common Terms
External Clearance Installation Class Partial Discharge
The shortest distance through air, I Equipment in closed systems Electric discharge that partially
between conductive input and (e.g., telecom) protected bridges the insulation between two
output leads, measured in mm. against overvoltage with de- electrodes. Avago supports partial
Refer to Figure 4. vices such as diverters, filters, discharge measurements per IEC/
capacitors, etc. EN/DIN EN 60747-5-2, a technique
Comparative Tracking Index (CTI) II Energy consuming equipment developed to evaluate the integ-
Outer molding material charac (e.g., appliances) supplied rity of insulating materials. IEC/
terization in the presence of aque- through a fixed installation. EN/DIN EN 60747-5-2 philosophy
ous contaminants. The higher the III Primarily equipment in fixed is that partial discharge testing
CTI value, the more resistant the installations (e.g., fixed indus- offers advantages over Dielectric
material is to electrical arc track- trial equipment). Withstand Voltage testing, which
ing. CTI is often used with creep- IV Primary supply level for indus- might adversely affect the insu-
age by safety agencies to deter- trial factories. lating material, and over through
mine working voltage. insulation distance requirements
Insulation
External Creepage Operational - required for correct which not only increase manufac-
The shortest distance along the equipment operation but not as a turing costs but also do not neces-
outside surface, between input protection against electric shock. sarily result in acceptable insulat-
and output leads, measured in Basic - protects against electric ing capability.
mm. Refer to Figure 4. shock.
Pollution Degree
Supplementary - independently
Dielectric Insulation Voltage Withstand 1 - Nonconductive pollution only.
applied to basic insulation to pro-
Rating 2 - Only occasional, temporary
tect against shock in the event of
conductivity due to condensa-
The ability to withstand without its failure.
tion.
breakdown a 60 second appli Double - composed of both basic
3 - Frequent conductive pollution
cation of a defined dielectric insu- and supplementary. Reinforced
due to condensation.
lation voltage between input and - A single insulation system com-
4 - Persistent conductive pollution
output leads. posed of several layers (e.g., single
due to dust, rain or snow.
and supplementary).
Distance Through Insulation Rated Mains Voltage
Internal Clearance
Distance between the photo Primary power voltage declared
See Distance Through Insulation.
emitter and photodetector inside by manufacturer. Used to catego-
optocoupler cavity (also called in- Internal Creepage rize optocoupler maximum allow-
ternal clearance). Refer to Figure 4. The shortest border distance be- able working voltage.
tween two separate insulating ma-
terials measured between emitter
and detector.
Material Group (see Comparative
Tracking Index)
I 600 < CTI
II 400 < CTI < 600
IIIa 175 < CTI < 400
IIIb 100 < CTI < 175
Introduction
Circuit designers often encounter Avago specifies common-mode prietary, low-cost Faraday shield
the adverse effects of common- rejection as common-mode transient which decouples the optocoupler
mode noise in a design. Once a rejection (CMTR). CMTR describes the input side from the output side.
common-mode problem is identi- maximum tolerable rate-of-rise (or The second method is by unique
fied, there are several ways that it fall) of a common-mode voltage package design which minimizes
can be resolved. However, common- (given in volts per microsecond). The input-to-output capacitance. The
mode interference manifests itself in specification for CMTR also includes importance of these two strengths is
many ways; therefore, it may be hard the amplitude of the common-mode explained as follows.
to determine whether it is the cause voltage (VCM) that can be tolerated.
Figure 5 illustrates a Common-mode
of a circuit’s misbehavior. If a system Common-mode interference that
transient pulse (VCM).
is connected and running but only exceeds the maximum specification
produces erroneous data, common- might result in abnormal voltage Figure 6a and 6b show interfer
mode noise may be the reason. transitions or excessive noise on the ence circuit models for two types
This section describes sources of output signal. (CMTR is slightly dif- of possible common-mode failure
common-mode problems, presents ferent than common-mode rejec- mechanisms for a single-transistor
possible solutions, and highlights tion ratio CMRR, often used for analog optocoupler. The dashed lines are
the technology that Avago Tech- devices and commonly specified in shown to indicate external compo-
nologies' Components Group uses dB as the ratio of the differential- nents added to the optocoupler. VCM
to produce opto-isolators with su- mode gain to the common-mode represents a voltage spike across the
perior Common-Mode Performance. gain.) optocoupler isolation path between
the output-side ground (VG2) and
Common-mode rejection (CMR) is Avago optocouplers rely on two
input-side ground (VG1). VDM repre-
a measure of the ability of a device key technical strengths to achieve
sents a signal voltage applied across
to tolerate common-mode noise. high CMTR. The first is use of a pro-
the input side.
INTERNAL SHIELD
TRANSMIT SIDE RECEIVE SIDE
LED PHOTODIODE
R VDM RL
OPTO-
ISOLATOR RL IP
V
IB
VO
CIS CSB
VG1
INPUT GROUND VCM
iCM
VOLTMETER VG2
VOLTMETER OUTPUT GROUND
+ (VCM) –
NOTE: iCM GETS DIVERTED TO GROUND, VG2, WHEN INPUT IS OFF.
COMMON-MODE TRANSIENT
iCM IS SUPPLIED FROM GROUND, VG2, WHEN OUTPUT IS ON.
Figure 5. Illustration of VCM Common-Mode Pulse. Figure 6a. Interference Circuit Model.
HV +
ISOLATION ISOLATION
GATE GATE
A1 B1
CONTROL DRIVE DRIVE
CIRCUITRY
MOTOR
1 2
GATE GATE
DRIVE B2 A2 DRIVE
HV -
As long as the amplitude VCM and (A1, B1) is attached to the drain of +250 V and ‑250 V in 100 ns creates
value of dVCM /dt are less than the a second set of transistors (A2, B2). a common-mode transient signal
ratings for the optocoupler being When transistor set A turns on, set of 5000 V/µs with an amplitude of
used, VOH will remain above 2 V B turns off. Current flows from the 500 V (see Figure 9). The device that
(maximum TTL VIH) and VOL will positive supply, through transistor carries the control infor mation to
remain below 0.8 V (minimum TTL A1, through the load, and through each MOSFET must be able to with-
VIL). Note that the slight perturba- transistor A2. When set B turns on, stand this level of common-mode
tions in output voltage occur some- set A turns off, and the polarity of interference. Although this example
time after the input pulse which the current through the inductive may seem extreme, it is a fact that
causes them, due to the non-zero re- load is reversed. engineers continue to use faster-
sponse time of the output transistor switching transistors to increase
How does this operation create
to the “perturbation signal.” motor efficiency. Power MOSFETs,
a common-mode problem? The for example, are commonly used in
Common-mode signals can origi- input of each gate drive circuitry power inverter applications because
nate from several different sources. is referenced to the ground of the they are capable of high frequen-
A full bridge power inverter, shown digital control circuitry; the output cy, high power switching. The fast
in Figure 8, is a good example of an common, on the other hand, is float- switching speeds of the transistors,
application that can exhibit large ing and referenced to the source however, can generate common-
amounts of common-mode noise. of its associated power transistor. mode signals with very high rates of
Full-bridge inverters are commonly The floating commons of the upper change (dVCM/dt).
found in motor-speed control and gate drive circuits rapidly switch
switching power supply applica- between the positive and negative The common-mode signal rate
tions. The power inverter is generally power supplies. This rapid switching of rise can also be affected by the
used to produce an ac output from creates a large voltage swing across reverse recovery characteristics of
a dc input. In a full-bridge inverter the input to output of the gate diodes D1 and D2 in the power
application like that shown in Figure drive circuitry. As an example, a half
8, the source of one set of transistors bridge circuit that switches between
+250 V
I Q1
D1 I D2
Q1
MOTOR
V CM
VCM
D2 I D2
Q2
VCM
-250 V
100 ns
inverter shown in Figure 9; these trate what happens when Q1 turns High electrical noise levels can also
diodes are often referred to as “free- back on. As Q1 starts to turn on, the contribute to common-mode prob-
wheeling” diodes. If the inverter is current through D2 begins to de- lems. A significant amount of electri-
driving an inductive load, such as a crease. The current through D2 con- cal noise is found in industrial envi-
motor winding, these diodes may tinues to decrease and actually goes ronments as a result of the starting
become forward biased during the negative for a short time due to the and operating of electric motors.
normal operation of the inverter. For storage of minority carrier charge in When a large motor first turns on,
example, assume that Q1 of Figure its junction. It is when this charge it normally requires a large in-rush
9 is turned on, Q2 is off, and current has been depleted that D2 begins to current to reach operating speed.
is flowing through Q1 and into the turn off and VCM begins to increase. This large current spike can gener-
inductive load. When Q1 turns off, If D2 turns off very quickly, VCM can ate a significant amount of electrical
voltage VCM swings in the negative also rise very quickly, generating noise in its own and nearby systems.
direction until diode D2 becomes a large common-mode transient Even the electric motors in a typical
forward biased and conducts the signal. household environment vary in size
load current. from fractional to low integral horse-
For the particular case of driving the
power units and are often noisy
It is when Q1 turns back on that very gate of an IGBT or power MOSFET
ac-operated or brushed dc-motors.
high rates of rise can be generated. in a power inverter, the HCPL-3120
Other sources of electrical noise
In extreme cases, when Q1 turns IGBT/MOSFET gate drive optical iso-
include microwave ovens, welding
on again, the rate of rise of voltage lator is an effective solution for com-
equipment, and automobile igni-
VCM is determined by how quickly mon-mode problems, providing
tions.
diode D2 recovers from forward protec tion against common-mode
conduction. The voltage and current transients with slew rates as fast as
waveforms shown in Figure 10 illus- 15 kV/µs at VCM as high as 1500 V.
Figure 13. High voltage common mode noise spike hardly causes a ripple in the output of 10MBd digital optocoupler ACPL-M61L.
70%
60%
50%
40%
30%
20% Ave
10% Ave-3Std (worst-case)
0%
0 5 10 15 20 25 30
Field Years
Figure 14a. CTR degradation performance vs field years for AlGaAs (Type 1) LED (operating IF=16mA, 50% duty cycle, TA=80°C)
70%
60%
50%
40%
30%
20% Ave
10% Ave-3Std (worst-case)
0%
0 5 10 15 20 25 30
Field Years
Figure 14b. CTR degradation performance vs field years for AlGaAs (Type 2) LED (operating IF=5mA, 100% duty cycle, TA=80°C)
70%
60%
50%
40%
30%
20% Ave
10% Ave-3Std (worst-case)
0%
0 5 10 15 20 25 30
Field Years
Figure 14c. CTR degradation performance vs field years for GaAsP LED (operating IF=16mA, 50% duty cycle, TA=80°C)
Avago optocouplers are suitable Solvent Cleaning: The solvent tem- electrical disturbances. It is therefore
for automatic printed circuit board perature and immersion time should necessary to have proper shield-
(PCB) assembly operations including not exceed 45°C and three minutes ing and bypassing of the VCC and
surface mount assembly. The follow- respectively. For ultrasonic cleaning, Ground traces. Bypassing closely
ing guidelines are recommended for environmentally safe solvents such to each of the optocouplers VCC-to-
proper operation and long term reli- as ethyl and methyl alcohol are rec- Ground pins with low-inductance
ability of Avago optocouplers. ommended. ceramic capacitor is recommended
as shown in Figure 17.
Solder Reflow Process: Only one sol- ESD Precautions: Standard electro-
dering operation is recommended static discharge precautions should Figure 17 shows an optional PCB
within the thermal profile shown be taken in handling and assem- layout for a high speed digital op-
in Figure 16. With infrared lamp bly of the optocouplers to prevent tocoupler for improving electrical
heating, use precautions to avoid damage or degradation of the noise immunity. The optional VCC
localized temperature rise in the device. and Ground traces between the pin
resin. Also, the resin should not be rows of the optocoupler help shield
Printed Circuit Board Layout: An op-
immersed in the solder. To prevent the output circuitry from electrical
tocoupler performs reliably only in
chloride corrosion of the lead frame, disturbances on the input pins, thus
a correctly designed circuit. In most
halide fluxes should not be used. improving common-mode rejection.
digital optocoup lers the amplifier
Wave Soldering: The maximum at the output is required to operate
solder temperature allowed is 260°C with the very low photocurrent from
for 10 seconds, with the solder 1.6 the photodetector. Consequently
mm below the seating plane. these amplifiers can be sensitive to
250
100 50 sec
Pre Heating Time
150°C, 90±30 sec.
TIGHT
Room TYPICAL
Temperature LOOSE
0
0 50 100 150 200 250
TIME (seconds)
HCPL-2601/11 HCPL-2601/11
ANODE 2 7 VE
0.1µF
CATHODE 3 6 VOUT
OUTPUT
4 5 GND
GND BUS
10 mm MAX
Figure 17. Optional Printed Circuit Board Layout for Improved Electrical Noise Immunity.
Description LED 2
CMOS gates can be easily driven. Figure 2. Split Darlington Transistor Optoisolator
LED 2
INTEGRATED
CURRENT
SOURCE HCPL-7721
HCPL-0721
VDD1 1 8 VDD2
C1
VIN 2 7 C2
LOGIC
GATE INPUT NC* 3 6 VOUT
CMOS
PUSH-PULL
4 5 OUTPUT
SHIELD STAGE
1 2
*PIN 3 IS THE ANODE OF THE INTERNAL LED AND MUST BE LEFT UNCONNECTED FOR
GUARANTEED DATA SHEET PERFORMANCE.
C1, C2 = 0.01 TO 0.1 µF
R IN 1 VCC2 8 VCC2
VCC1
(+5 V)
(+5 V) TTL/
2 7 LSTTL DATA
OUTPUT
DATA TTL/
LSTTL 3 6 0.1 µF
INPUT
GND
4 5
TOTEM
POLE
OUTPUT
GATE 1 2
VCC1 - VF - VOL
RIN =
IF
RECOMMENDED R IN = 1.1 kΩ
R IN 1 8
IF
VIN 74LS05 2 7 RL
IO I IL
3 6 VOUT
8 0.1 VDD2
VDD1 20 pF 1 kΩ µF
RL
7
VIN VO
2 6
RI
3
5
1 2
VDD1 RI RL VDD1
(V) (kΩ) (kΩ) (V)
5 5.11 1 5
10 13.3 2.37 10
15 19.6 3.16 15
VDD1 1 8 VDD2
C1 C2
VIN 2 7
74HCTO4
IO 74HCTO4
NC 3 6 VOUT
LED1
GND1 4 5 GND2
SHIELD
Benefits
• Lower power consumption
• Very simple interface
1 8
1/6 74HCTO4
R1
VIN 2 7 4.7 kΩ
* 1/4 74HC/HCT08
3 6 VOUT
4 5
R 1 = VOH - VF
IF
V IN 0.1 µF 10.0 µF
RL
R1 2 2
74LVU04
1 VOUT
* USE ANY 1
SIGNAL DIODE
1 8 VCC
3.3 kΩ
RS-232C 2 7 RL
INPUT
(± 3 V TO ± 25 V)
1N4150
3 6 VO
CMOS or LSTTL
4 5
R1
R2
RS232
OUTPUT
1 2
DIGITAL
LOGIC
3.3V
HCPL-260L
R4
R3 RS232
INPUT
1 2
Benefits
• Compact design with small out-
line optocouplers
• Prevents common-mode tran-
sients from interfering with the
signal
• Low power dissipation
+5 V +5 V COMMON
ISOLATED
SUPPLY
TERMINATION
DS75176A
DATA IN
RS-485
HCPL-2631 LINE
DR/RX
ENABLE
VCC
DS75176A DATA IN
DATA OUT
HCPL-2601
RS-485
LINE HCPL-2631
DRIVER
GND 1 RECEIVER
ENABLE
TERMINATION
VCC
ISOLATION RS-485 BUS
DATA OUT
HCPL-2601
GND
REGULATOR
+ +
5V 5V
HCPL-0720
1 8 5V 2
TX 2 7
3
0.1 µF
VCC
3 6 TXD
5 V+
1
0.1 µF C4 +
0.01
4 5 7
SHIELD µF CANH 4 CAN+
1 2
3 SHIELD
5V 5V 82C250
HCPL-0720
6
CANL 2 CAN-
8 1
5 VREF
0.1 µF RS REF
8 1 V-
7 2
RXD
GND 4
RX 6 3 2 D1
0.1 µF 30 V
C1 R1
5 4 1M Ω
SHIELD 2 0.01 µF
1
2
2 500 V
2
-ILOOP R3
25Ω
A) RECEIVER
+ILOOP
Vcc
5.5V
R8 2N3904
R2 100kΩ R3
0.001µF 150Ω LM158 10kΩ
HCNR200 Z1 2N3904 +
R1 Vcc LED 5.1V –
Vin 80kΩ 0.1µF HCNR200
– 2N3906 2N3904
+ R6 0.001µF R4 PD 2
HCNR200 LM158 R7 140Ω 10kΩ
PD 1 3.2kΩ
1
R5 -ILOOP
25Ω
B) TRANSMITTER
NOTE: The two OP-AMPS shown are two separate LM158, and NOT two channels in a single DUAL package;
otherwise, the LOOP saide and input sied will not be properly isolated.
39 Ω
39 Ω
1 2 3 6 7 8
YX YX YX YX YX YX
6N138
1 8 +5 v
560 Ω
X 2 7 2.2 kΩ
IF
Y 3 6 VO
4 5
100M
BALANCED
TYPICAL SIGNAL RATE – BAUD
SPLIT PHASE
10M 10% PULSE WIDTH DISTORTION
22 AWG UNSHIELDED TWISTED
PAIR WIRE CABLE (DEARBORN
NO. 862205)
1M
TA = 25 °C
BALANCED
(SINGLE
100K HCPL-2300
NO EX- OR FF)
10K
1 10 100 1000 10,000
HCPL-2631
H RL H
H H
L
DATA
L 0.1 µF RL
RS L
L H
Z
ICM VCM LSTTL EXCLUSIVE–
OR FLIP FLOP
1 2
RS HCPL-4661 8
RL RL 2
1 4
7
5
H L
DATA IN 2 3
4
ENABLE 6 6
(HIGH)
3 1/2 75159
5
8 1
ISO 5 V
ISO 5 V
680 Ω 7 2 REG
0.01 µF
820 Ω
RX 6 3
5 4
SHIELD
HCPL-061N
ISO 5 V
5V
8
ISO 5 V 1 VCC
1 kΩ 1 kΩ R
0.01
1 8
µF 6
680 680 A +
TX Ω Ω 4
2 7 D RT
SN75176
0.01 µF 3 7
3 6 DE B –
TX
ENABLE
4 5 2 1M
SHIELD
RE GND 0.01 µF
5
HCPL-063N
8 1 ISO 5 V
0.01 µF
7 2 REG
RX 6 3
0.01 µF
5 4
SHIELD
1 8 8
1 VCC
R
TX 2 7 0.01 µF
0.01
µF 6
4 A +
3 6 D
0.01 µF
RT
4 5
SHIELD 75ALS176D
3 7
DE B –
ISO 5 V
5V 1 8
2
680 RE
2 7 GND
Ω
0.01 µF 5
1 kΩ
3 1M
6 0.01 µF
TX
ENABLE
4 5
SHIELD
HCPL-061N
56 kΩ
22 MΩ
2 7
-48 V dc 0.1 µF 2N3906
1N4150
3 6
10 kΩ
100 kΩ
R(+) 4 5 VOUT
1 kΩ
ISDN Interface
TELEPHONE LINE
ISOLATION BARRIER
RECEIVE
2-WIRE
ISDN PROTECTION
LINE CIRCUIT
TRANSMIT
1 8
2 7 LINE POLARITY
HCPL-4731
3 6
LINE RESPONSE
4 5
TELEPHONE
LINE
8 INTERFACE
PRIMARY–SECONDARY 2
POWER ISOLATION HCPL-4701 6 CIRCUIT
3 SECONDARY/
BARRIER 5 EMERGENCY
EMERGENCY
POWER POWER
SWITCHED–
MODE
VCC
SECONDARY
PRIMARY P0WER VCC – RETURN
AC VOLTAGE SUPPLY POWER
POWER
SUPPLY
Introduction
HCNR200/1
Optoisolators transfer analog and The HCNR200/1 optoisolator can be used
1 NC 8
digital signals from one circuit as a basic analog isolation building block
LED
section or module to another in the for a wide variety of applications that
2 NC 7
presence of a large potential dif- require good stability, linearity, band-
K1 K2
ference or induced electrical noise width and low cost. The HCNR200/1 is
3 6
between the ground or common very flexible and, by appropriate design
points of these modules. Examples of the application circuit, is capable of
4 PD1 PD2 5
of analog isolation applications operating in many different modes, in-
cluding unipolar, bipolar, ac/dc, invert-
are interfaces to: A/D converters,
ing and non-inverting. Figure 1. HCNR-200/1 High Linearity Analog
sensing circuits such as thermocou-
ples and transducers, patient moni- The HCPL-4562 and HCNW4562 are Isolator
toring equipment, motor speed recommended for very high band-
and position measurement circuits, width (up to 15 MHz) AC analog
audio and video amplifiers, and designs. If the output transistor
power supply feedback. is biased in the active region, the NC 1 8 V CC
current transfer ratio relationship for
Basic Building Blocks for Analog the HCPL-4562 can be represented ANODE 2 7 VB
Isolation as:
CATHODE 3 6 VO
Avago Technologies’ HCNR200/1 and IC = K ( IF / IFQ ) n
HCPL4562 constitute basic optical cou- where IC is the collector current; IF NC 4 5 GND
pling building blocks for high linearity is the LED input current, IFQ is LED
isolation applications. Figures 1 and 2 input current at which K is meas-
show the respective optical coupling Figure 2. HCPL-4562 High Bandwidth Analog
ured; K is the collector current when
mechanisms for these two optoisola- Isolator
IF = IFQ; and n is the slope of IC vs. IF
tors. Both these isolators use high-per-
on logarithmic scale.
formance AlGaAs LEDs and photodiode
combinations with higher speed and The exponent n varies with IF, but
HCPL-4562
linearity compared to conventional op- over some limited range of DIF, n can 80
toisolators. The HCNR200/1 LED illumi- be regarded as a constant. For ac-
70
nates two closely matched photodiodes, signal applications, the HCPL-4562
IPB - BASE PHOTO CURRENT - µA
VCC2 +5 V
VCC1 +5 V
R2 R5 R7
LED
R3 68 kΩ 10 kΩ 470
10 kΩ VOUT
R1 Q2 Q4
68 kΩ 2N3904 2N3904
Q1 Q3
VIN
2N3906 2N3906
R4 R6
PD1 10 Ω PD2 10 Ω
HCNR200/1
1 NC 8
LED
2 NC 7
ISOLATION
BARRIER K1 K2
3 6
4 PD1 PD2 5
D1
VEE1 -15 V LED 1N4150 VEE2 -15 V
HCNR200/1
1 NC 8
LED
ISOLATION 2 NC 7
BARRIER
K1 K2
3 6
4 PD1 PD2 5
C3 10 pF
C1 10 pF
R6 R7
180 kΩ 50 kΩ
R2
180 kΩ D1 R4
– 680 Ω GAIN
OC1 + OC1 OC1 –
R1 PD1 LED PD2 VOUT
VIN 50 kΩ +
BALANCE
OC2 OC2 OC2
PD1 + LED PD2
– R5
R3 D2 680 HCNR200/1
180 kΩ 1 NC 8
LED
C2 10 pF
2 NC 7
ISOLATION K1 K2
BARRIER 3 6
4 PD1 PD2 5
D1 D3 R4
– 680 kΩ
CNR201
+ C3 10 pF
R2 R3
10 kΩ 4.7 kΩ R5 R6
VIN LED 180 kΩ 50 kΩ
D2 +
GAIN
– CONTROL
–
D4 VMAGNITUDE
–
+
+
C2 10 pF
VCC
6N138
+
– R7
10 kΩ R8
2.2 kΩ
VSIGN
IF KPD R5 R7
5.6 kΩ 470 Ω
2 7
VOUT
R1 2 µF
2.2 kΩ 3 6 Q3
2 µF R4
18 kΩ I3
VIN Q2
Q1 4 5
R2
1.8 kΩ R6
D1 R3 Q1 2N3904 82 Ω
1N4150 330 Ω Q3 2N3904
2
1
GAIN 1 • KPD • R4 • R7 1
R3 R6
+HV
3- PHASE
OUTPUT
VOLTAGE
SENSE GATE GATE GATE
DRIVE DRIVE DRIVE
C U- V- W-
B
CURRENT
SENSE
-HV
MICRO-
MOTOR SPEED, POSITION
CONTROLLER
Isolated Current and Voltage Sens- Analog Signal Isolation for Speed perturbations in the LED current
ing and Position Measurement during common mode transients
and becomes the major source of
Avago Technologies provides several Avago Technologies offers a low CMR failures for a shielded optocou-
analog isolation amplifier prod- cost, high accuracy, isolated ampli- pler. The main design objective of a
ucts for isolated precision current fier solution for the measurement high CMR LED drive circuit becomes
and voltage sensing for monitor- of speed and position in a motor. keeping the LED in the proper state
ing motor performance. Avago With the use of Avago Technologies’ (on or off ) during common mode
also offers a digital output isolation HCNR201 and low cost operational transients. The recommended
amplifier for direct connection to amplifiers, circuit designers have
a micro-controller. Compared to the flexibility of designing analog application circuits for Avago’s gate
Hall-Effect sensors, Avago’s isolation isolation amplifiers that have low drive applications can achieve 15
amplifiers have excellent gain and input bias currents, high bandwidth, kV/µs CMR while minimizing com-
offset characteristics, especially very stable gain, and very high linearity. ponent complexity.
low offset drift over a wide tempera- Another cause of CMR failure for a
ture range. In addition, they provide Common Mode Rejection shielded optocoupler is direct cou-
a compact, low-cost, and reliable so- The detector shield in the opto- pling to the optocoupler output
lution for motor drive designers that coupler prevents CMR failure due pins through CLED01 and CLED02 in
need to accurately measure motor to capacitive coupling from the Figure 2. Many factors influence the
voltage and current. Some of the key input side of the optocoupler, effect and magnitude of the direct
performance features include: through the package, to the detec- coupling including: the use of an
• 12-bit linearity (HCPL-7860) tor IC. However, this shield does not internal or external output pull-up
• over current detection (HCPL- eliminate the capacitive coupling resistor, the position of the LED
788J) between the LED and the optocou- current setting resistor, the connec-
• ±200 mV input range pler output pins and output ground tion of the unused input package
• -40°C to +85°C operating tem- as shown in Figure 2. This capacitive pins, and the value of the capaci-
perature range coupling causes tor at the optocoupler output (CL).
• 15 kV/µs isolation transient im- The recommended gate drive and
munity IPM interface application circuits for
• Safety Standards Certifications: Avago optocouplers have been op-
UL, CSA, IEC/EN/DIN EN 60747-5- 1 8
timized to reduce the likelihood of
2 CMR failure.
20 kΩ
CLEDP
2 CLED02 7
CLED01
3 6
CLEDN
4 5
SHIELD
Many of Avago’s gate drive and IPM analyzed in the same way) it is im- consideration are typically mounted
interface optocouplers include a portant to know the minimum and in close proximity to each other.
Propagation Delay Difference (PDD) maximum turn-on (tPHL ) and turn- (Specifically, tPLH max and tPHLmin in
specification intended to help de- off (tPLH ) propagation delay specifi- the Figure 3 equations are not the
signers minimize “dead time” in their cations, preferably over the desired same as the tPLH max and tPHL min,
power inverter designs. Dead time is operating temperature range. over the full operating temperature
the time periods during which both range, specified in the data sheet.).
The limiting case of zero dead time
the high and low side power transis-
occurs when the input to Q1 turns This delay is the maximum value
tors (Q1 and Q2) of a power module
off at the same time that the input for the propagation delay differ-
are off. Any overlap in Q1 and Q2 con-
to Q2 turns on. This case determines ence specification that is specified
duction will result in large currents
the minimum delay between LED1 at 450 ns for the HCPL-4506 over
flowing through the power devices
turn-off and LED2 turn-on, which is an operating temperature range of
between the high and low voltage
related to the worst case optocou- -40°C to +100°C. Delaying the LED
motor rails.
pler propagation delay waveforms, signal by the maximum propaga-
To minimize dead time the design- as shown in Figure 3. A minimum tion delay difference ensures that
er must consider the propagation dead time of zero is achieved in the minimum dead time is zero, but
delay characteristics of the optocou- Figure 3 when the signal to turn on it does not tell a designer what the
pler as well as the characteristics of LED2 is delayed by (tPLH max - tPHL min ) maximum dead time will be. The
the IGBT gate drive circuit. Consider- from the LED1 turn off. Note that the maximum dead time occurs in the
ing only the delay characteristics of propagation delays used to calcu- highly unlikely case where one op-
the optocoupler (the characteristics late PDD are taken at equal temper- tocoupler with the fastest tPLH and
of the IGBT gate drive circuit can be atures since the optocouplers under another with the slowest tPHL are in
the same inverter leg. The maximum
ILED1
dead time in this case becomes the
sum of the spread in the tPLH and
tPHL propagation delays as shown in
Q1 OFF
VOUT1
Q1 ON Figure 3.
VOUT2
Q2 OFF
Q2 ON
The maximum dead time is also
equivalent to the difference between
the maximum and minimum propa-
ILED2
tPLH gation delay difference specifica-
MIN. tions. The maximum dead time
tPLH (due to the optocouplers) for the
MAX.
PDD*
HCPL-4506 is 600 ns over an operat-
MAX. tPHL ing temperature range of -40°C to
MIN. +100°C.
tPHL
MAX.
MAX.
DEAD TIME
D1H
A14P
1,000 V
VDESAT(H)
HV+
HIGH GATE-DRIVE 1k DUAL IGBT
DDSH
C2H RDESATH
HCPL-316J RTONH C3H A14P
1 16 1.2 µF
VIN+ VE 10 0.1 µF 1,000 V
2 15 (20%)
VIN– VLED2+ N/C
3 14
VCC1 DESAT
4 13 DZLH
GND1 VCC2 VC(H)
5 12 18 V
RESET VC
6 11 VO(H)
FAULT VOUT M1 DFBHI
7 10
VLED1+ VEE RGH (DSE130-12A,
8 9
VLED1– VEE 12.5 IXYS)
RBIASDH
20K
VE(H)
AC
DZ2H C4H MOTOR
12 V 250 nF
VEE(H)
R1L 15nF
D2H 47K C1L
A14P R2L
1,000 V 20
LOW GATE-DRIVE
HCPL-316J 1K
1 16 DDSL
VIN+ VE RDESATL
2 15 HV DIODE
VIN– VLED2+
3 14 (LOW GATE-DRIVE CIRCUIT IS
VCC1 DESAT
4 13 M2
GND1 VCC2 IDENTICAL TO HIGH DFBLO
5 12 RGL
RESET VC GATE-DRIVE CIRCUIT) (DSE130-12A,
6 11 12.5
FAULT VOUT IXYS)
7 10
VLED1+ VEE
8 9
VLED1– VEE
HV–
Low Cost Two Terminal Resistor Selection Guide (Supplier: Dale Electronics, Tel: 402-564-3131)
Shunt Resistor Shunt Price Tolerance Temp. Max. RMS Motor Power Range
Part Number Resistance Range Coefficient Current 120 Vac - 440 Vac
(mΩ) (US$) ( % ) (ppm/°C) (A) (hp) (kW)
LV-5.005 5 $0.40 - 1.00 1 <300 28.3 8 - 28 6 - 21
LVR-3.01 10 $0.38 - 0.76 1 <300 14.1 4 - 14 3 - 10
LVR-3.02 20 $0.38 - 0.76 1 <300 7 2 - 7 1.4 - 5
LVR-3.05 50 $0.38 - 0.76 1 <300 2.8 0.8 - 3 0.6 - 2
WSC-2.02* 20 $0.38 - 0.76 1 <300 7.1 2 - 7 1.4 - 5
* Surface Mount
High Performance Four-Terminal Shunt Resistor Selection Guide (Supplier: Isotek, Tel: 508-673-2900)
Shunt Resistor Shunt Unit Price Tolerance Temp. Max. RMS Motor Power Range
Part Number Resistance @ 2500 Qty. Coefficient Current 120 Vac - 440 Vac
(mΩ) (US$) ( % ) (ppm/°C) (A) (hp) (kW)
PBV-R050-0.5 50 $3.74 0.5 <30 3 0.8 - 3 0.6 - 2
PBV-R020-0.5 20 $3.74 0.5 <30 7 2 - 7 1.4 - 5
PBV-R010-0.5 10 $3.74 0.5 <30 14 4 - 14 3 - 10
PBV-R005-0.5 5 $4.09 0.5 <30 25 [28] 7-25 [8-28] 5-19 [6-21]
PBV-R002-0.5 2 $4.09 0.5 <30 39 [71] 11 - 39 8 - 29
[19 - 71] [14 - 53]
Note: Values in brackets are with a heatsink for the shunt.
+5 V HCPL-3120
1 8 +HVDC
270 Ω + Vcc*
0.1 µF –
Rg
2 7
CONTROL
INPUT Q1
A 3-PHASE
3 6
– VEE* AC
+ OPTIONAL
74XXX
OPEN
4 5
COLLECTOR
Q2 –HVDC
*RECOMMENDED SUPPLY VOLTAGES
SINGLE SUPPLY Vcc = +18V VEE = 0V
DUAL SUPPLY Vcc = +15V VEE = -5V
Isolated Gate Drive for IGBT/MOSFET with Integrated Desaturation Protection and Fault Feedback
VCC2
RESET 18 V
(INPUT)
DRIVE
HCPL-316J
SIGNAL 74ACT04 0.1 µF
(INPUT) 1 16 20k
VIN+ VE VCC2
2 15 HV DIODE
VIN– VLED2+ 0.1 µF -5 V 1k
MICRO-CONTROLLER 3 14
VCC1 DESAT
4 13
VCC1 GND1 VCC2 RDESATH
0.1 µF 5 12
5V 3.3 k RESET VC 20k
6 11
FAULT VOUT
7 10
VLED1+ VEE 0.1 µF RGATEH
300 pF 8 9
VLED1– VEE
DESAT
FAULT
(OUTPUT)
3-PHASE
OUTPUT
HCPL-4506
HCPL-4506
HCPL-4506
1 8 VCC1 HCPL-4506
0.1 µF HCPL-4506
20 KΩ
ILED1 20 KΩ
+5 V 2 7
+HV
310 Ω
VOUT1
3 6
CMOS
Q1
4 5 M
SHIELD
Q2
HCPL-4506
VCC2
1 8 –HV
20 kΩ 0.1 µF 20 KΩ
+5 V ILED2
2 7
310 Ω
3 6
VOUT2
CMOS IPM
4 5
SHIELD
HCPL-4506
150 pF
+SUPPLY
10.0 kΩ
+5 V +15 V
78L05
+5 V 0.1 µF
IN OUT
HCPL-7840
0.1 µF
1 8 0.1 µF
0.1 µF 8
2 7 2.00 kΩ 6 –
0.01 7
39 Ω 5 VOUT
µF 3 6 + MC34082A
+ – 4 5 2.00 kΩ
M 4
0.1 µF
RSENSE
150 pF 10.0 kΩ
-15 V
HV–
GATE DRIVE
CIRCUIT
R1
CCLK VDD
D1 C1
0.1 µF CLAT CHAN
5.1 V
R2 39 Ω VDD1 VDD2 CDAT SCLK
VIN+ MCLK MCLK1 SDAT
Low Cost Isolated Phase Current Sensing with Analog Output and Over Current Detection
HV +
FLOATING
GATE DRIVE POSITIVE
CIRCUIT SUPPLY
R4
C1
D1 0.1 µF
5.1 V 5 HCPL-788J GND2 16
VDD1
C6
0.1 µF
1 VIN+ VDD2 15 µC
R2 C2 R3 4.7 kΩ
39 Ω 0.1 µF 2 FAULT 14
MOTOR VIN– TO OTHER
+ R1 + PHASE
8 GND1 ABSVAL 13 OUTPUTS
RSENSE
7 VDD1 VOUT 12 A/D
3 CH VREF 11 VREF
4 CL VDD2 10 C8 C4 C7 C5
6 VLED+ GND2 9
GND
HV +
C5 = C7 = C8 = 470 pF
+5 V C4 = 0.1 µF
150 pF
R1
+SUPPLY
10.0 kΩ
+5 V +15 V
78L05
+5 V
IN OUT
HCPL-7840
0.1 µF
1 8 0.1 µF
0.1 µF 8
2 7 2.00 kΩ 6 –
0.1 7
39 5 VOUT
R2 µF 3 6 +
MC34082A
4 5 2.00 kΩ
4
0.1 µF
-15 V
HV+ VCC
VI
U1 U3
R1 HCPL-4562 HCPL-4562
8 8
R3
2 2
R4 R5
6 6
VO
3 5 5 3
R2
HV–
+ U2
ISOLATION
BARRIER –
VO R2
C1
VI R1
Low Cost Isolation Amplifier for Motor Speed and Position Measurement
VCC2 +5 V
VCC1 +5 V
R5 R7
R2 10 kΩ 470
+ LED 68 kΩ
0-10 V R3
– VOUT
10 kΩ
R1 Q2 2N3904 Q4 2N3904
68 kΩ
VIN Q1 2N3906 Q3 2N3906
M
R4 R6
10 Ω 10 Ω
PD1 PD2
HCNR200/1
A 4-20 mA
ISOLATION
BARRIER
2 DC+ 7 RL
UP TO
800 Vac
3 DC- VO 6 VOUT HCPL-3700/60 SCHEMATIC
1 AC VCC 8 3 5
4 AC GND 5
DC INPUT CONFIGURATION
HCPL-0708/HCPL-0738
HIGH VOLTAGE
DC SUPPLY
ISOLATION
BOUNDARY
AC
RECTIFIER POWER OUTPUT
LOAD
SWITCH FILTER
MAINS
PWM
CONTROLLER
ISO-AMP WITH +
CNR200/1 GAIN SYSTEM
OPTOCOUPLER — REFERENCE
POWER-OFF
AND
UNDER-VOLTAGE SENSE DIGITAL INTERRUPT MICRO-
OPTOCOUPLER PROCESSOR
HCPL-0708
D1 R3
C1 R4
5V R9 R13
+
CATHODE
SUS* R7
ANODE
D4
HCPL-2200
R1
D5 PWM CHIP
L
C8
AC L1
POWER
+
R10
C2 ISOLATED
N C6 C7
D2 DC
R2 HCPL-2200 OUTPUT
C3
R8 +
R12
5V R11
C4 R5
* SUS = SILICON UNILATERAL SWITCH
D3 R6
Isolation Boundary
DC Input Synchronous
Power Switch Rectifier/ Load
Output Filter
Isolated
Bias Supply
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2014 Avago Technologies. All rights reserved. Obsoletes 5989-0802EN
AV02-4387EN - January 3, 2014