TUTORIAL 3

EET107/3 DIGITAL ELECTRONICS 1

TUTORIAL 3

1. Draw the output waveform of Q for a negative edge-triggered JK flip-flop with active LOW,
CLR’ and PRE’ by using the input waveforms in Figure 1.

Figure 1

2. Based on Figure 3, draw the output waveforms, Q and Q’ for the given inputs in Figure 3.1.

Figure 2

Figure 2.1
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3. Based on Table 1, design a counter with JK flip-flops.

Table 1
Present State Next State
Q2 Q1 Q0 Q2 Q1 Q0
0 0 0 0 1 0

0 1 0 1 0 0

1 0 0 1 0 1
1 0 1 1 1 1
1 1 1 0 0 0

4. The circuit of Figure 3 contains a JK flip-flop and a D flip-flop. Complete the timing diagram
of Figure 3.1 by drawing the waveforms of signals Q1, Q2 and Q 2 . Assume that all the output
values are initially at 0.

x Q Q1 D Q Q2
J

C Q2
Q C Q
K

Clock

CLR CLR  1
Figure 3

Clock

CLR

Figure 3.1

5. Show how an asynchronous counter can be implemented having a modulus-13 with a

straight binary sequence from 0000 through 1100.
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6. Design a counter with the irregular binary count sequence shown in the state diagram of
Figure 4. Use J-K flip-flops.

Figure 4

7. Design a counter with the irregular binary count sequence shown in the state diagram of
Figure 5. Use positive edge-triggered J-K flip-flops.

Figure 5
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8. Based on Figure 6, develop the state table. Use D flip-flop.

Figure 6

9. Based on the circuit that given in Figure 7, determine Boolean equation for each flip-flop.

Figure 7
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Question 10 (from final exam Q6, 2011/12)

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Question 11 (from final exam Q6, 2010/11)

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Question 12 (from final exam Q3 2012/13)