Enhanced PWM Circuit

Signature and Grading Sheet

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Signature
Section 4.3(c): .

Grading
 Section 4.1(a): VHDL code (30 points): .
Attach code printout
 Section 4.1 (b) diagram (20 points): .
Attach one-page block diagram
 Section 4.2(c): Simulation (20 points): .
Attach simulation timing diagram printout.
 Section 4.3(b): VHDL code (10 points): .
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 Section 4.3 (c): demo signature (20 points): .

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 Experiment
Enhanced PWM Circuit

1 Purpose
To design an enhanced PWM (Pulse Width Modulation) circuit
2 Reading
Chapter 5 of FPGA Prototyping by VHDL Examples 2nd edition.
3 Project specification
A PWM circuit has an output pulse whose duty cycle (i.e. fraction of a period that is "high")
is specified by a control signal. In the enhanced version, we want to control the exact time of the
on and off intervals. The inputs and output of this circuit are specified as follows:
 clk: input clock signal. The period of clk is Tc.
 d: a 4-bit input signal. It is interpreted as an unsigned number and used to specify the
“off-interval” of the pulse signal.
 w: a 4-bit input signal. It is interpreted as an unsigned number and used to specify the
“on-interval” of the pulse signal.
 pulse: a 1-bit output.

The waveform of the pulse signal is shown below. Note that it can be considered as a squared
wave with a period of (d+w)*Tc and with the w*Tc portion asserted.

The design must synchronous or 50% will be deducted.

4 Design Procedures
4.1 VHDL design
The entity declaration of this design is shown below:
entity epwm is
port(
clk: in std_logic;
reset: in std_logic;
d, w: in std_logic_vector(3 downto 0);
pulse: out std_logic
);
end epwm;
(a) Derive VHDL code.
(b) Draw the top-level conceptual diagram (up to 10 blocks) of your code.
4.2 Simulation
(a) Perform simulation to verify the operation of the circuit. The simulation should include the
following values (normal and corner conditions):
d=4, w=4; d=1, w=15; d=15, w=1; d=0, w=1; d=1, w=0
(b) The following testbench code can be used.
library ieee; 
use ieee.std_logic_1164.all; 
 
entity epwm_tb is 
end epwm_tb; 
 
architecture arch of epwm_tb is 
   constant T   : time    := 10 ns; ‐‐ clk period 
   signal clk   : std_logic; 
   signal reset : std_logic; 
   signal d, w  : std_logic_vector(3 downto 0); 
   signal pulse : std_logic; 
begin 
   ‐‐***************************************************************** 
   ‐‐ instantiation 
   ‐‐***************************************************************** 
   ‐‐ instantiatie ddfs 
   epwm_unit : entity work.epwm 
      port map( 
         clk       => clk, 
         reset     => reset, 
         d      => d, 
         w      => w, 
         pulse  => pulse 
      ); 
   ‐‐***************************************************************** 
   ‐‐ clock 
   ‐‐***************************************************************** 
   ‐‐ 10 ns clock running forever 
   process 
   begin 
      clk <= '0'; 
      wait for T / 2; 
      clk <= '1'; 
      wait for T / 2; 
   end process; 
    
    ‐‐***************************************************************** 
   ‐‐ reset 
   ‐‐***************************************************************** 
   ‐‐ reset asserted for T/2 
   reset <= '1', '0' after T / 2; 
    
   ‐‐***************************************************************** 
   ‐‐ stimulus 
   ‐‐***************************************************************** 
   process 
   begin 
      ‐‐************************************************************** 
      ‐‐ test different patterns  
      ‐‐************************************************************** 
     ‐‐ pattern 1 
      d <= "0100"; 
      w <= "0100"; 
      wait for 8 * 10 * T;    
     ‐‐ pattern 2 
      d <= "0001"; 
      w <= "1111"; 
      wait for 16 * 10 * T;    
     ‐‐ pattern 3 
      d <= "1111"; 
      w <= "0001"; 
      wait for 16 * 10 * T;    
     ‐‐ pattern 4 
      d <= "0000"; 
      w <= "0001"; 
      wait for 50 * T;    
     ‐‐ pattern 5 
      d <= "0001"; 
      w <= "0000"; 
      wait for 50 * T;    
      ‐‐************************************************************** 
      ‐‐ terminate simulation 
      ‐‐************************************************************** 
      assert false 
         report "Simulation Completed" 
         severity failure; 
   end process; 
end arch; 
(c) The correct simulated timing diagram looks like

4.3 Implementation and testing

(a) Use 9 switches for the reset, d and w signals and one LED for the pulse signal.
(b) Derive the top-level wrapping VHDL code.
(c) Synthesize the code, program the FPGA device, and verify the operation of physical circuit.
Demonstrate the circuit to instructor and get signature.