Testable fault detecting Vedic Multiplier core

Saranya B
1BG08EC087

Priti Saigal Sahana R Sharan J M

1BG08EC074 1BG08EC086 1BG08EC093

Batch B10-2012
Project Seminar

Project Guides
Dr Veena S Chakravarthi (Internal) Mr.Chandramohan Umapathy (External)
Professor ECE, BNMIT Cofounder of Pool Systems
Department of Electronics Communication Engineering
BNM Institute of Technology 1
08-05-12
www.bnmit.org
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DEPT OF ECE-2012
Introduction

 Literature survey

 Application scenario

 Functional Specification

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DEPT OF ECE-2012 Data Pre-processor

RTL CODE

TEST BENCH

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DEPT OF ECE-2012 Squarer using Duplex Sutra..
Hardware implementation of duplex sutra
Input number (ab)² = a² + 2ab + b²
32
X = 14 a = 1, b = 4
16 16 16
16 a² = 1 b² = 16.
MAS
2ab = 2 * 1 * 2 = 8.
8 8
8 8 Find the sum X² = 196
8 MAS 8
8 MAS 8

Squarer-8 bit Squarer-8 bit

Squarer-8 bit Squarer-8 bit
LUT LUT
LUT LUT
RTL CODE
Duplex adder_8
Duplex adder_8 33
32 32
Duplex adder_16
FUNCTIONAL
64 MAS-Multiply and shift VERIFICATION
Output number

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Squarer using YVDN Sutra

Hardware implementation of YVDN sutra

RTL CODE FUNCTIONAL

VERIFICATION

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DEPT OF ECE-2012
Multiplier using Nikhilam and Anurupye..

Multiplier

RTL CODE FUNCTIONAL

VERIFICATION

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 Multiplier using Duplex Sutra and Babylonian
BNMIT
DEPT OF ECE-2012
Mathematics
=

RTL CODE

FUNCTIONAL
VERIFICATION

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DEPT OF ECE-2012
Multiplier using Urdhva Tiryagbyham Sutra..
INPUTS
A B
32 32

8 8 8 8 8 8 8 8

A7A6 A5A4 A3A2 A1A0 B7B6 B5B4 B3B2 B1B0

A1A0 A3A2 A1A0 A5A4 A3A2 A1A0 A7A6 A5A4 A3A2 A1A0 A7A6 A5A4 A3A2

B1B0 B3B2 B1B0 B5B4 B3B2 B1B0 B7B6 B5B4 B3B2 B1B0 B7B6 B5B4 B3B2
P1 P2 + P3 P4 + P5 + P6 P7 + P8 + P9 + P10 P11 + P12 + P13
A7A6 A5A4 A3A2 A1A0
A7A6 A5A4 A7A6
B7B6 B5B4 B3B2 B1B0
RTL CODE
B7B6 B5B4 B7B6 P11+P12 P7+P8+ P4+P5
P16 P14+P15 P2+P3 P1
+P13 P9+P10 +P6
P14 + P15 P16 FUNCTIONAL
VERIFICATION
PRODUCT
64
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DEPT OF ECE-2012
Cuber

(ab)³ = a³ + 3a²b + 3ab² + b³

FUNCTIONAL
RTL CODE
VERIFICATION

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DEPT OF ECE-2012
Fault Detector

RTL CODE FUNCTIONAL

VERIFICATION

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DEPT OF ECE-2012
Performance Analysis using Cadence
Performance 32 bit 32 bit Quarter 32 bit Urdhva 32 bit YVDN Improvement
Parameter Conventional Squarer Multiplier Multiplier
Multiplier Multiplier
Cell Area 13,160 14,528 4,748 13,710 63.92%
Timing 20,242ps 15,520ps 12,777ps 12,974ps 36.87%
Power 15,77,624nW 4,00,386nW 3,96,192nW 18,19,291nW 74.88%

Performance 32 bit Conventional 32 bit Duplex 32 bit YVDN Improvement

Parameter Squarer Squarer Squarer
Cell Area 10,044 3943 9060 60.74%
Timing 12,747ps 2390ps 11,756ps 81.25%
Power 6,86,743nW 1,49,404nW 7,86,076nW 78.24%

Performance Parameter 32 bit Conventional Cuber 32 bit Vedic Cuber Improvement

Cell Area 34,780 48,039
Timing 36,558ps 30,386ps 16.88%
Power 48,98,269nW 39,64,048 19.07%

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DEPT OF ECE-2012
Chipscope

 Chipscope is a set of tools made by Xilinx that allows you to easily probe the internal signals of
your design inside an FPGA.

 It has two main parts:

• Embeddable IP cores that capture and store values of signals within the FPGA.
• Software tool that allows one to “read” the captured data and visualize it on a host computer.

 The Xilinx Chipscope tools package has several modules that are added to Verilog design.
They are:
• ICON (Integrated controller)
• VIO (Virtual Input/Output)
• ILA (Integrated Logic Analyser)
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DEPT OF ECE-2012
Chipscope

Incorporating ChipScope Modules into Your Design

1. Generate the ChipScope modules, using the ChipScope Core Generator.
2. Incorporate and instantiate the ChipScope modules into the top-level module in your design.
3. Connect the ChipScope modules to your design.
4. Synthesize, implement, and run the design on the FPGA.

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DEPT OF ECE-2012 Generating the ICON, VIO and UCF files

ICON-1 ICON-2 ICON-3

1. Double-click on ICON.
(a) Component Name: Assign your ICON a name (this is arbitrary).
(b) Select the correct Number of Control Ports.
2. Your ICON will have been created in the directory you specified to store your project.

VIO-1 VIO-2 VIO-3

1. Double-click on VIO.
(a) Component Name: Assign your VIO a name (this is arbitrary).
(b) Enter the bit width for any 2 of the 4 signals: asynchronous inputs, synchronous inputs,
asynchronous outputs and synchronous outputs.
2. Your VIO will have been created in the directory you specified to store your project.

UCF
You will also need a UCF file in the same directory to specify that the design‟s timing should be meet
a clock constraint, and that the system clock is located at a specific pin on the board.

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 Generating Top Module and Starting Chipscope Pro
BNMIT
DEPT OF ECE-2012 analyzer
•Instantiate ICON and VIO in top module.
TOP MODULE
•After generating the top module, implement the process by clicking on “analyze design using
chipscope”.

• After the entire process is successful, the main window of “Chipscope Pro” opens. Make sure that
FPGA board is connected to PC.

•Click on „Initialize JTAG Chain‟ icon located at the top right corner of the window.

•Now select the FPGA device from the JTAG chain, right click and then select „Configure‟ to specify
the configuration bit stream file. CHIPSCOPE PRO

•The required input and output signals are obtained in VIO Console.
Result for Quarter Squarer multiplier is displayed. SNAPSHOT

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DEPT OF ECE-2012
Functional Validation with UART Core

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UART Functional Specification

 UART Data Transmission

UART data transmit and receive

UART Tx byte register

UART Rx byte register

Clock frequency = 66MHz

Baud rate of UART core = 19200 bits/sec

Frame format

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References

 High speed squarer by Chandra Mohan Umapathy.

http://www.magicalmethods.com/FREE/applications_in_sw/Camera_high_speed_paper.pdf

 Vedic Mathematics based 32 Bit High Speed Squarer Circuit using McCMOS Technique for
Low Power VLSI Applications by Arindam Chakraborty ,Hamim Zafar, Jubin Hazra .

 High speed vedic multiplier for digital signal processor by Ramesh pushpangadam, Vineet
Sukumaran, Rino Innocent, Dinesh Sasikumar, Vaisak Sundar.

 Analysis, Verification and FPGA Implementation of Vedic Multiplier with BIST Capability by
Vinay Kumar .

 www.vedicmaths.org

 www.vedicganita.org
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DEPT OF ECE-2012
Cadence Design Contest 2012

Greetings from Cadence!

Congratulations! Your submission below has been shortlisted for the next stage of the Cadence Design Contest 2012.

Title of abstract: Testable fault detecting Vedic Multiplier Core

Category: Bachelor's
Institute: BNM Institute of Technology

Please submit your project report by *Friday, July 20, 2012*. Late submissions will not be accepted.

Format of Paper
Your final submission must be in the following format (IEEE Standard).

On Front Cover:
•Project Name
•Project Submitter‟s Details (name, email address, semester)
•Guide‟s Details (name, email address) – if applicable

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Thank you !!!

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Literature survey..

 Vedic Mathematics was Rediscovered in the early twentieth century by Swami

Sri Bharati Krishna Tirthaji Maharaja.
 The sutras were contained in the Atharva Veda – a branch of mathematics and
engineering.
 It comprises of 16 sutras like Urdhva Tiryagbyham, Nikhilam
Navatascaramama Dasatah and sub sutras derived from the main sutras like
duplex sutra.
 Reduces cumbersome looking calculations to very simple ones resulting in a
more efficient method in terms of speed and implementation

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Application scenario..

CONVOLUTION
C MAC
I
FFT ALU
A
F
CMUL
FIR
MICROPROCESSOR
DSP OPERATIONS

RSA CIRCUITRY

ENCRYPTION

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DEPT OF ECE-2012 Functional specification..

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DEPT OF ECE-2012 Functional verification – Duplex squarer..

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DEPT OF ECE-2012 Functional verification – YVDN squarer..

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BNMIT
DEPT OF ECE-2012 multiplier..

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DEPT OF ECE-2012 Functional verification – Urdhva multiplier..

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 Functional verification – multiplier using Nikhilam
BNMIT
DEPT OF ECE-2012 and Anurupye..

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DEPT OF ECE-2012 Functional verification – Cuber

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DEPT OF ECE-2012 ICON-1

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DEPT OF ECE-2012 ICON-2

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DEPT OF ECE-2012 ICON-3

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DEPT OF ECE-2012 VIO-1

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DEPT OF ECE-2012 VIO-2

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DEPT OF ECE-2012 VIO-3

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DEPT OF ECE-2012 UCF

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DEPT OF ECE-2012 Top Module

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DEPT OF ECE-2012

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DEPT OF ECE-2012 Quarter Squarer multiplier result

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