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Floating Gate Devices:

Operation and Compact Modeling

Paolo Pavan (1) , Luca Larcher (1) and Andrea MarmirolI (2)

(1) Università di Modena e Reggio Emilia, Via Fogliani, 1 – 42100 Reggio Emilia (Italy) - pavan.paolo@unimo.it (2) STMicroelectronics, Central R&D, Via C. Olivetti, 2, 20010 Agrate Brianza (MI), Italy – andrea.marmiroli@st.com

OUTLINE

Motivation and Purposes

Floating Gate (FG) Device model:

FG voltage calculation (DC) Parameter extraction procedure Program/erase current modeling (TRANSIENT)

 

Fowler-Nordheim tunnel current + a new self-consistent model to calculate the electric field within the oxide

Channel Hot Electron (CHE) and Channel Initiated Secondary Electron (CHISEL) currents

Reliability simulations

 

Stress and Radiation Induced Leakage Current

Advantages and Conclusions

MOTIVATIONS AND PURPOSES

FG memory cells are usually replaced with standard MOS in industry circuit simulations: Spice-like models demanded

The standard method to calculate the FG potential uses capacitive coupling coefficients, α i = C i /C T

V

FG

V V V V

CG

CG

D

D

S

S

B

B

Constant capacitive coupling coefficients errors [1]

The optimum model should be: Spice-like, compact, accurate, reliable (both DC and transient)

[1] L. Larcher, et al., IEEE Trans. Elect. Devices, Sept. 2001

The new DC model

G

ate

C PP

CPP

C PP
The new DC model G ate C PP C ontrol F loating G ate VFG Source

C ontrol

Floating Gate

The new DC model G ate C PP C ontrol F loating G ate VFG Source
VFG Source Body Drain P-substrate
VFG
Source
Body
Drain
P-substrate

C PP = interpoly dielectric capacitance V FG = Floating Gate voltage

Elements of the DC model

The new Spice-like model uses lumped circuit elements:

the capacitor, C PP , which takes into account the inter-poly dielectric capacitance

the MOS transistor: can be MOS Model 9 (Philips) or BSIM3v3 (Berkeley), or …

The voltage controlled voltage source, V FG :

It implements the procedure to calculate the FG voltage in a C code routine

It is necessary to overcome problems in simulating a capacitive net in DC conditions

V FG calculation

FG

CG

CG

CG

VFG

B
B

D

S

V F G calculation FG CG V FG B D S Q CPP = C PP

Q CPP = C PP (V FG -V CG )

V FG is calculated by solving the charge neutrality equation at the FG node:

Q MOS + Q CPP = Q W/E

Q W/E = charge injected into the FG during the write/erase (constant in DC conditions)

Q MOS = f(V FG ,V S ,V B ,V D ) calculated by means of the MOS model charge equations ….

Q MOS calculation

MOS Model 9 (Philips) charge equations:

Q

Q

Q

Q

MOS

=− Q + Q + Q + C

B

D

S

[

]

GDO

B

S

D

(

= f C

OX

(

= f V

DS2

(

= f V

DS2

,V ,V ,V ,V

FB

SB

T1

GB

,V

GT3

,C

OX

,δ ,F

2

J

,V

GT3

,C

OX

,δ ,F

2

J

,K

0

)

)

)

V

GD

+ C

GSO

V

GS

+ C

GBO

V

GB

MOS Parameters: K 0 , C OX , V FB MOS electrical internal variables: V T1 , V GT3 , V DS2 , δ 2 , F J

Solution of charge equation

The charge neutrality equation is an implicit equation in

V FG :

F(V FG ) = Q MOS (V FG ) + Q CPP (V FG ) – Q W/E = 0

It has no analytical solution, due to the complex expression of Q MOS ELDO (Spice-like simulator) solves it numerically through suitable convergence algorithms

Note that F is monotonic versus V FG for all the bias combinations (V CG ,V S ,V B ,V D ) in the functionality range of the device, thus guaranteeing the physical meaning of the derived V FG solution

Parameters of the model

Parameters of the equivalent MOS transistor (dummy cell):

they can be extracted by applying the standard MOS parameter procedure to the dummy cell.

Only one additional parameter compared to a standard MOS transistor: the Floating Gate to Control Gate capacitance C PP

derived from the cross section and layout of the cell

No additional costs compared to the standard modeling activity for MOS transistors The model is very easy and simple to use

The new transient model

The DC model of FG memories can be extended to model transient conditions by adding some voltage controlled current sources to include program and erase currents

Write currents of E 2 PROM and Flash are different: hence, number and position of current sources may vary for E 2 PROM and Flash

Each voltage controlled current source models analytically a specific kind of program/erase current: Fowler-Nordheim, CHE, CHISEL

One additional Eldo parameter allows the user to choose the desired Floating Gate memory (Flash or E 2 PROM) model

The new transient E 2 PROM model

Control Gate CPP Floating Gate IW/E VFG Source Drain
Control Gate
CPP
Floating Gate
IW/E
VFG
Source
Drain

P-substrate

CPP Floating Gate IW/E VFG Source Drain P-substrate B o d y For E 2 PROM

Body

For E 2 PROM memories, I W/E models the program/erase Fowler-Nordheim current flowing across the tunnel oxide

The new transient Flash model

C ontrol G ate CPP F loating G ate Iw1 Iw3 VFG Iw2 Source Drain
C ontrol
G
ate
CPP
F loating
G
ate
Iw1
Iw3
VFG
Iw2
Source
Drain
P-substrate
Body

For Flash memories: I W1 and I W2 model the erase FN current; I W3 the CHE+CHISEL program current

Fowler-Nordheim current source

The voltage controlled current source (implemented in ELDO) modeling Fowler/Nordheim currents allows to reproduce program-erase and erase operations of E 2 PROM and Flash memories, respectively.

A

T A FN , B FN

F OX

I

FN

(

F

ox

)

=

A A

T

2

F

FN ox

exp  −

B

FN

F

ox

= area of the tunneling region = Fowler-Nordheim coefficients depending on the Si/SiO 2 barrier = electric field across the oxide, which has been evaluated through ….

F OX calculation

F OX

=

V

FG

V

S,D,B

V

FB

ψ

S

ψ

P

(

)

T OX

V FB = flat-band voltage

ψ S = surface potential drop at Si/SiO 2 interface

ψ P = surface potential drop at poly-Si/SiO 2 interface To correctly evaluate ψ S and ψ P is necessary to take into account poly depletion and charge quantization effects:

for this reason, a self consistent model has been used [2] The so calculated F OX has been incorporated in the FG model through an analytical law, parameterized on the FG and S,D,B dopings, which are additional parameters

[2] L. Larcher et al., “A new model of gate capacitance …”, IEEE Trans. Elect. Devices

CHE-CHISEL current source

CHE-CHISEL gate currents have been modeled analytically and included by means of a voltage controlled current source

This way, actual program operations of modern Flash memories can be reproduced also by circuit simulations

The CHE-CHISEL current model adopts a new approach to model hot carrier phenomena, and particularly, to describe the high energy distribution of carriers involved in impact ionization phenomena

CHISEL current modeling

[3]

The key point of CHISEL [3] current modeling is the accurate calculation of energy distribution of tertiary electrons, that are generated by four physical mechanisms (M)

CHISEL Gate CHE M4 e 1 Source M1 e 3 M2 h 2
CHISEL
Gate
CHE
M4
e 1
Source
M1
e 3
M2
h 2
(M) CHISEL Gate CHE M4 e 1 Source M1 e 3 M2 h 2 Impact Ionization

Impact Ionization

M3

h

M4 e 1 Source M1 e 3 M2 h 2 Impact Ionization M3 h e 1,2
e 1,2 Drain
e
1,2
Drain

2,3

Body

L. Larcher, P.Pavan, “A New Analytical Model of Channel Hot Electron (CHE) and CHannel Initiated Secondary ELectron (CHISEL) …,” MSM 2002, 2002, pp. 738-741.

Reliability Simulations

Leakage currents across the gate oxide (SILC [4] - RILC [5] ) are modeled analytically and included by means of some voltage controlled current sources The model can simulate the reliability degradation of Flash and E 2 PROM memories due to the aging of the gate oxide induced by Program/Erase cycles and also by the exposure to ionizing radiation: read/gate/drain disturb prediction Now, our work is focused to model leakage currents due to Trap-Assisted Tunneling through n-traps including also the phonon contribution (percolation path)

[4]

L. Larcher et al. “A Model of the Stress Induced Leakage Current in Gate Oxides”, IEEE Trans.

[5]

Electr. Devices, Vol.48, N.2, 2001, pp.285-288. L. Larcher et al. “ A model of radiation induced leakage current (RILC) in ultra-thin gate oxides”, IEEE Trans. Nuclear Science, Vol. 46 (6), pp. 1553-1561, 1999.

SILC - RILC modeling

The Stress-Induced Leakage Current (SILC) and the Radiation-Induced Leakage Current are modeled assuming an inelastic Trap-Assisted Tunneling (TAT) as conduction mechanism

cathode SiO 2 E p x T anode t ox
cathode
SiO 2
E p
x T
anode
t ox

Simulation results

Simulation results achieved by this model are excellent in both DC and transient condition, for either Flash and E 2 PROM memories, WITHOUT any free parameter to improve the fitting quality

We tested the simulation capability of this model on both E 2 PROM and Flash memories, in DC and transient conditions.

DC – E 2 PROM: I DS -V CG

A( )

SD

I

10 -5 V = 0V SB 10 -6 C PP = 3 fF W=0.3 µm
10 -5
V = 0V
SB
10 -6
C PP = 3 fF
W=0.3 µm
L=0.75 µm
10 -7
V = 5V
SB
-8
10
simulation
-9
10
(exp) 0
5
step 1V
V SB
10 -10
0
1
2
3
4
5
V
(V)
CG

DC – E 2 PROM: I DS -V DS

)

A(

µ

DS

I

140 simulation V = 5V G 120 V= 0V B V = 4V 100 G
140
simulation
V
= 5V
G
120
V= 0V
B
V
= 4V
100
G
80
V
= 3V
G
60
V
= 2V
G
40
20
V
= 1V
G
0
0
0.5
1
1.5
2
2.5
3
3.5
4
V
(V)
DS

DC – E 2 PROM: I DS -V CG

)A

µ

(I

SD

120

100

80

60

40

20

0

simulation V= 0V B V (exp) 0.8 3.8 step 1V D V = 3.8V D
simulation
V= 0V
B
V
(exp) 0.8
3.8
step 1V
D
V = 3.8V
D
V = 0.8V
D
0
1
2
3
4
5
V
(V)
CG

DC – Flash: I DS -V CG

A( )

SD

I

-4 10 V (exp) 0 2 step 0.5V SB -5 10 -6 10 V =
-4
10
V
(exp) 0
2
step 0.5V
SB
-5
10
-6
10
V = 0V
SB
-7
10
C PP = 0.8 fF
W=0.25 µm
L=0.375 µm
-8
10
V = 2V
SB
-9
10
V = 0.1V
DS
-10
10
simulation
-11
10
2
3
4
5
6
7
V
(V)
CG

DC – Flash: I DS -V DS

A)

µ

(

SD

I

25

20

15

10

5

0

simulation V CG = 4 V V B = 0 V V CG = 3.75
simulation
V CG = 4 V
V B = 0 V
V CG = 3.75 V
V CG = 3.5 V
V CG = 3.25 V
= 3 V
V CG
0
0.3
0.6
0.9
1.2
1.5
1.8
V
(V)
DS

DC – Flash: I DS -V CG

( A)

µ

D

I

60

50

40

30

20

10

0

simulation C PP = 0.4 fF W=0.16 µm L=0.3 µm V (exp) D 0.1 V
simulation
C PP = 0.4 fF
W=0.16 µm
L=0.3 µm
V (exp)
D
0.1
V
0.7
V
1.3
V
1.9
V
2
2.5
3
3.5
4
4.5
5
5.5
6
V
(V)
CG

DC – Flash: I DS -V DS

)

A(

µ

SD

I

25

20

15

10

5

0

V CG = 3.4 V simulation V B = 0 V V CG = 3.2
V CG = 3.4 V
simulation
V B = 0 V
V CG = 3.2 V
C PP = 0.4 fF
W=0.22 µm
L=0.3 µm
= 3 V
V CG
V CG = 2.8 V
V CG = 2.6
0
0.3
0.6
0.9
1.2
1.5
1.8
V
(V)
DS

DC – Flash: I DS -V DS

( A)

µ

D

I

30 simulation 25 V (exp) D 20 0.4 V 0.8 V 15 1.2 V 1.6
30
simulation
25
V (exp)
D
20
0.4
V
0.8
V
15
1.2
V
1.6
V
10
5
0
1.5
2.0
2.5
3.0
3.5
V
(V)
CG

Transient – Flash: V T - time

7 V (exp) -2.7 -4.7 step 1V G0 6 5 V = -4.7 V G0
7
V
(exp) -2.7
-4.7
step 1V
G0
6
5
V
= -4.7 V
G0
4
3
V
= -2.7 V
G0
2
1
simulation
V= V= 8 V
B
S
0
0
0.1
0.2
0.3
0.4
)(VV
T

Time (s)

Erase bias:

D float V S =V B =8 V

V CG V G,MAX V G0
V CG
V G,MAX
V G0
8 V B S 0 0 0.1 0.2 0.3 0.4 )(VV T Time (s) Erase bias:

Time

8 V B S 0 0 0.1 0.2 0.3 0.4 )(VV T Time (s) Erase bias:

Transient – Flash: V T - time

7 dV/dt (exp)= 12.5,20,25,30,35,50,60 V/s 6 simulation 5 4 dV/dt= 12.5V/s 3 2 1 dV/dt=
7
dV/dt (exp)= 12.5,20,25,30,35,50,60 V/s
6
simulation
5
4
dV/dt= 12.5V/s
3
2
1
dV/dt= 60 V/s
0
0
0.1
0.2
0.3
0.4
)(VV
T

Time (s)

Erase E 2 PROM: V T - time

4 Lines: simulations Symbols: measures 3 2 1 0.3 0.4 0.5 0.6 0 T 12V
4
Lines: simulations
Symbols: measures
3
2
1
0.3
0.4
0.5
0.6
0
T
12V
V
CG -ramp
RISE (ms
)
-1
-2
V
D =V B =0V
T
V
S =0V
RIS
E
-3
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
V T (V)

Time (ms)

Program E 2 PROM: V T - time

3 12V V D -ramp 2 V CG =V B =0V T V S floating
3
12V
V
D -ramp
2
V
CG =V B =0V
T
V S floating
RIS
1
E
T
RISE (ms
0.6
0
0.7
)
0.3
0.4
-1
Lines: simulations
Symbols: measures
-2
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
V T (V)

Time (ms)

Program E 2 PROM: V FG and V S

6 Dotted lines: V FG Solid lines: V S 5 4 3 T RISE (ms
6
Dotted lines: V FG
Solid lines: V S
5
4
3
T
RISE (ms
0.6
)
2
0.3
12V
V
D -ramp
1
0
T
RIS
-1
E
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1

Time (ms)

Erase E 2 PROM: Tunnel Current

60 Lines: simulations V D -ramp Symbols: measures Nominal 50 40 Rea T l RIS
60
Lines: simulations
V
D -ramp
Symbols: measures
Nominal
50
40
Rea
T
l
RIS
30
E
20
dV
10
T
I
=−
C
TUN,MEAS
CG
dt
0
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
I TUN (pA)

Time (ms)

Simulation results: Flash program

9 V = 4.2V 8 DS 8 4 7 V pulse (V) CG 0 6
9
V
= 4.2V
8
DS
8
4
7
V
pulse (V)
CG
0
6
0
1
2
3
4
time (µ s)
5
V (exp)
SB
0 V
4
0.6
V
3
1.2
V
(A)
1.5
V
2
0
1
2
3
4
VT (V)

time (µ s)

No free parameter to improve the fitting quality!!

E 2 PROM retention simulations

N C 4.7 10 - 1 - fresh 4.2 2 10 3.7 3 10 4
N C
4.7
10 - 1 - fresh
4.2
2
10
3.7
3
10
4
3.2
10
5
N = 10
C
2.7
0
1
2
3
4
5
6
7
8
9
10
V)(VT

Years

E 2 PROM read path schematic

VPSENSE

VISENSE

Current bias

for sense

amp

Sense

Amplifier

out

VBOOST COL<0> COL<i> COL<n> VCG CG bias CG voltage voltage transfer generator block BL
VBOOST
COL<0>
COL<i>
COL<n>
VCG
CG bias
CG voltage
voltage
transfer
generator
block
BL
COL<i>
WL
Mini array of
virgin cells
CELLS
CG<i>

E 2 PROM read path signals

6 V WL 5 4 3 V SENSEOUT 2 V CG V CELL V 1
6
V WL
5
4
3
V SENSEOUT
2
V CG
V CELL
V
1
REF
V
BL
0
0
100
200
300
400
500
V (V)

Time (nsec)

E 2 PROM read path signals /2

3.0 V SENSE OUT 2.5 2.0 V CELL 1.5 V REF 1.0 V BL 0.5
3.0
V
SENSE OUT
2.5
2.0
V CELL
1.5
V REF
1.0
V BL
0.5
0
310
330
350
370
390
410
V (V)
V (V)

Time (nsec)

3.0 V SENSE OUT 2.5 V CELL 2.0 1.5 V REF 1.0 V BL 0.5
3.0
V SENSE OUT
2.5
V CELL
2.0
1.5
V REF
1.0
V BL
0.5
0
320
340
360
380
400
420

Time (nsec)

Advantages

This model features many advantages compared to others proposed in the literature:

The parameter extraction procedure is the same of a standard MOS transistors

The simulation time is comparable to that of a simple MOS transistor

V FG calculation procedure does NOT use capacitive coupling coefficients:

this means a more accurate V FG calculation (considering the capacitive coupling coefficients as constants introduces errors)

Coupling coefficients: α CG - Flash

αCG VB=-1V 0.72 VS=0V 0.70 0.68 0.66 0.64 0 11.13 0 22. 33.38 44.5 1
αCG
VB=-1V
0.72
VS=0V
0.70
0.68
0.66
0.64
0
11.13
0
22.
33.38
44.5
1
55.63
8
66.75
2
9
3
4
VCG
5
VD
=α V +α V +α V +α V
V FG
CG
CG
D
D
S
S
B
B

Coupling coefficients: α D - Flash

V

FG

Coupling coefficients: α D - Flash V FG αD CG D D S S B B
Coupling coefficients: α D - Flash V FG αD CG D D S S B B
αD CG D D S S B B 0.15 0.13 0.11 . 0.07 0 0.05
αD
CG
D
D
S
S
B
B
0.15
0.13
0.11
.
0.07
0
0.05
10
20
2
30
3
40
4
50
5
60
7
8
9
VB=-1V
VB=-1V
VCG
VS=0V
VS=0V

VD

V V V V

CG

Advantages /2

This is the first compact DC and transient model of a FG memory cell: it can be used for both single device simulations and circuit simulations

Fitting results are excellent WITHOUT any free parameter to improve the fitting quality

This model is easily scalable: scaling rules are taken into account in the MOS model itself, and they do not affect the V FG calculation

This model is easily upgradeable: voltage controlled current sources can be replaced independently on other elements of the model

Conclusions

We developed a new compact Spice-like DC and

transient model of the FG memory cell It overcomes the fixed coupling coefficients approach,

thus improving the FG memory cell modeling It is easily scalable and upgradeable

Its simulation time is not critical

Parameters can be extracted applying the same

procedure used for MOS transistor Simulation results are excellent without any free parameter to improve the fitting quality

It can be used for statistical analysis (effects of statistical fluctuation of critical parameters)

References

Paolo Pavan, Luca Larcher, Andrea Marmiroli, Floating Gate devices: Operation and Compact Modeling, Kluwer Academic Publishers, 2004, 140 pp., ISBN 1-4020-7731-9