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Typical Application
VBAT
VBB BOOT
~FAULT
GH
ECU IN1 A3946 S
IN2
PAD GL
RESET CP1
M
CP2
DT
VREF VREG
LGND PGND
29319.150i
A3946 Half-Bridge Power MOSFET Controller
Selection Guide
Part Number Packing Package
A3946KLPTR-T 4000 pieces/reel 16-pin TSSOP with exposed thermal pad
THERMAL CHARACTERISTICS
Characteristic Symbol Test Conditions* Value Units
Mounted on a 2-layer PCB with 3.8 in . 2-oz copper both sides
2
43 ºC/W
Package Thermal Resistance RθJA
Mounted on a 4-layer PCB based on JEDEC standard 34 ºC/W
*Additional thermal information available on Allegro Web site.
C1
C2 0.47 uF, X7R
0.47 uF, X7R V rated to VBAT
V rated to VBAT
P
L
VREF RGATE
GH
High Side
DT Turn-On Driver P
Delay
RDEAD
IN1
Control
S
L Logic
VREG
L
IN2 GL RGATE
Low Side
Driver
PGND
L
RESET P LGND
L
L P
PAD
Limits
Characteristics Symbol Test Conditions
Min. Typ. Max. Units
RESET = High, Outputs Low – 3 6 mA
VBB Quiescent Current IVBB
RESET = Low – – 10 μA
VREF Output Voltage VREF IREF ≤ 4 mA, CREF = 0.1 μF 4.5 – 5.5 V
Tj = 25C – 4 –
Pullup On Resistance RDSUP
Tj = 135C – 6 8
Tj = 25C – 2 –
Pulldown On Resistance RDSDOWN
Tj = 135C – 3 4
GH Output Voltage VGH tpw < 10 μs, Bootstrap Capacitor fully charged VREG – 1.5 – – V
Timing
Dead Time (Delay from Rdead = 5 kΩ 200 350 500 ns
tDEAD
Turn Off to Turn On) Rdead = 100 kΩ 5 6 7 μs
Propagation Delay tPD Logic input to unloaded GH, GL. DT = VREF – – 150 ns
Limits
Characteristics Symbol Test Conditions Min. Typ. Max. Units
Protection
VREGOFF VREG decreasing 7.8 8.3 8.8 V
VREG Undervoltage
VREGON VREG increasing 8.6 9.1 9.6 V
VBSOFF VBOOT decreasing 7.25 7.8 8.3 V
BOOT Undervoltage
VBSON VBOOT increasing 8 8.75 9.5 V
Thermal Shutdown Temperature TJTSD Temperature increasing – 170 – °C
Logic
Input Current IIN(1) IN1 VIN / IN2 VIN = 2.0 V – 40 100 μA
Functional Description
VREG. A 13 V output from the on-chip charge pump, used possible UVBOOT), FAULT = 0; also the fault latch is cleared
to power the low-side gate drive circuit directly, provides the immediately, and remains cleared. If the power is restored
current to charge the bootstrap capacitors for the high-side gate (no UVREG or UVREF), and if no OVERTEMP fault exists,
drive. then the latched fault remains cleared when the RESET line
returns to high. However, FAULT = 1 may still occur because a
The VREG capacitor, CREG, must supply the instantaneous cur-
UVBOOT fault condition may still exist.
rent to the gate of the low-side MOSFET. A 10 μF, 25 V capaci-
tor should be adequate. This capacitor can be either electrolytic
Charge Pump. The A3946 is designed to accommodate a
or ceramic (X7R).
wide range of power supply voltages. The charge pump output,
VREG, is regulated to 13 V nominal.
Diagnostics and Protection. The fault output pin,
~FAULT, goes low (i.e., FAULT = 1) when the RESET line is In all modes, this regulator is current-limited. When VBB < 8 V,
high and any of the following conditions are present: the charge pump operates as a voltage doubler. When 8 V <
• Undervoltage on VREG (UVREG). Note that the outputs VBB< 15 V, the charge pump operates as a voltage doubler/
become active as soon as VREG comes out of undervoltage, PWM, current-controlled, voltage regulator. When VBB>15 V,
even though the ~FAULT pin is latched until reset. the charge pump operates as a PWM, current-controlled, volt-
• Undervoltage on VREF (UVREF). Note that this condition age regulator. Efficiency shifts, from 80% at VBB= 7 V, to 20%
does NOT latch a fault. at VBB = 50 V.
• A junction temperature > 170°C (OVERTEMP). This condi- CAUTION. Although simple paralleling of VREG supplies
tion sets a latched fault. from several A3946s may appear to work correctly, such a
• An undervoltage on the stored charge of the BOOT capacitor configuration is NOT recommended. There is no assurance that
(UVBOOT). This condition does NOT set a latched fault. one of the regulators will not dominate, taking on all of the load
An overtemperature event signals a latched fault, but does not and back-biasing the other regulators. (For example, this could
disable any output drivers, regulators, or logic inputs. The user occur if a particular regulator has an internal reference voltage
must turn off the A3946 (e.g., force the RESET line low) to that is higher that those of the other regulators, which would
prevent damage. force it to regulate at the highest voltage.)
The power FETs are protected from inadequate gate drive Sleep Mode/Power Up. In Sleep Mode, all circuits are
voltage by undervoltage detectors. Either of the regulator disabled in order to draw minimum current from VBB. When
undervoltage faults (UVREG or UVREF) disable both output powering up and leaving Sleep Mode (the RESET line is high),
drivers until both voltages have been restored. The high-side the gate drive outputs stay disabled and a fault remains asserted
driver is also disabled during a UVBOOT fault condition. until VREF and VREG pass their undervoltage thresholds.
When powering up, before starting the first bootstrap charge
Under many operating conditions, both the high-side (GH) cycle, wait until t = CREG ⁄ 4 (where CREG is in μF, and t is in ns)
and low-side (GL) drivers may be off, allowing the BOOT to allow the charge pump to stabilize.
capacitor to discharge (or never become charged) and create a
When powered-up (not in Sleep Mode), if the RESET line is
UVBOOT fault condition, which in turn inhibits the high-side
low for > 10 μs, the A3946 may start to enter Sleep Mode (VREF
driver and creates a FAULT = 1. This fault is NOT latched. To
< 4 V). In that case, ~FAULT = 1 as long as the RESET line
remove this fault, momentarily turn on GL to charge the BOOT
remains low.
capacitor.
If the RESET line is open, the A3946 should go into Sleep
Latched faults may be cleared by a low pulse, 1 to 10 μs Mode. However, to ensure that this occurs, the RESET line
wide, on the RESET line. Throughout that pulse (despite a must be grounded.
Dead Time. The analog input pin DT sets the delay to turn The dead time circuit can be disabled by tying the DT pin
on the high- or low-side gate outputs. When instructed to to VREF. This disables the turn-on delay and allows direct
turn off, the gate outputs change after an short internal propa- control of each MOSFET gate via two control lines. This is
gation delay (90 ns typical). The dead time controls the time shown in the Control Logic table, on page 2.
between this turn-off and the turn-on of the appropriate gate. Top-Off Charge Pump. An internal charge pump allows
The duration, tDEAD, can be adjusted within the range 350 ns 100% duty cycle operation of the high-side MOSFET. This is
to 6000 ns using the following formula: a low-current trickle charge pump, and is only operated after
tDEAD = 50 + (RDEAD ⁄ 16.7 ) a high-side has been signaled to turn on. A small amount of
bias current is drawn from the BOOT pin to operate the float-
where tDEAD is in ns, and RDEAD is in Ω, and should be in the ing high-side circuit. The top-off charge pump simply pro-
range 5 kΩ < RDEAD < 100 kΩ. vides enough drive to ensure that the gate voltage does not
Do not ground the DT pin. If the DT pin is left open, dead droop due to this bias supply current. The charge required for
time defaults to 12 μs. initial turn-on of the high-side gate must be supplied by boot-
strap capacitor charge cycles. This is described in the section
Control Logic. Two different methods of control are Application Information.
possible with the A3946. When a resistor is connected from
DT to ground, a single-pin PWM scheme is utilized by short- VREF. VREF is used for the internal logic circuitry and
ing IN1 with IN2. If a very slow turn-on is required (greater is not intended as an external power supply. However,
than 6 μs), the two input pins can be hooked-up individually the VREF pin can source up to 4 mA of current. A 0.1 μF
to allow the dead times to be as long as needed. capacitor is needed for decoupling.
Application Information
Bootstrap Capacitor Selection. CBOOT must be cor- At power-up and when the drivers have been disabled for
rectly selected to ensure proper operation of the device. If a long time, the bootstrap capacitor can be completely
too large, time is wasted charging the capacitor, with the discharged. In this case, Delta_v can be considered to be the
result being a limit on the maximum duty cycle and PWM full high-side drive voltage, 12 V. Otherwise, Delta_v is the
frequency. If the capacitor is too small, the voltage drop can amount of voltage dropped during the charge transfer, which
be too large at the time the charge is transferred from the should be 400 mV or less. The capacitor is charged whenever
CBOOT to the MOSFET gate.
the S pin is pulled low, via a GL PWM cycle, and current
To keep the voltage drop small: flows from VREG through the internal bootstrap diode
circuit to CBOOT.
QBOOT >> QGATE
Power Dissipation. For high ambient temperature
where a factor in the range of 10 to 20 is reasonable. Using applications, there may be little margin for on-chip power
20 as the factor:
consumption. Careful attention should be paid to ensure that
QBOOT = CBOOT × VBOOT = QGATE × 20 the operating conditions allow the A3946 to remain in a safe
and range of junction temperature.
CBOOT = QGATE × 20 / VBOOT
The power consumed by the A3946 can be estimated as:
The voltage drop on the BOOT pin, as the MOSFET is being
turned on, can be approximated by: P_total = Pd_bias + Pd_cpump + Pd_switching_loss
For example, given a gate charge, QGATE, of 160 nC, and the Pd_bias = VBB × IVBB , typically 3 mA,
typical BOOT pin voltage of 12 V, the value of the Boot
capacitor, CBOOT, can be determined by: and
+VBAT
C1
C2 0.47 μF
10 μF
P
VREF
VREF Charge VREG
+5 Vref
Pump
0.1 uF CREG
10 ILIM
10 μF
k7 L L P P
Top-Off
Charge Pump
BOOT
~FAULT
Protection
VREG Undervoltage Bootstrap
CBOOT
Overtemperature UVLO
UVLOBOOT 0.47 μF
IRF2807
L
GH RGATE
High Side
DT Turn-On Driver P
33 7
Delay
470
RDEAD k7
15.8 k7
IN1
Control
S
L Logic
VREG
IN Forward IRF2807
L
IN IN2 GL RGATE
Low Side
Brake
Driver
33 7
PGND
L DC
External M
LGND Motor
+5 V RESET P
L
L P
Diagram A. Dependent drivers. Unidirectional motor control with braking and dead time. TDEAD = 1 μs; QTOTAL = 160 nC.
+VBAT
C1
C2 0.47 μF
10 μF
P
VREF
VREF Charge VREG
+5 Vref
Pump
P
0.1 uF CREG
10 ILIM
k7 L L P P 10 μF
Top-Off
Charge Pump
BOOT
~FAULT M
Protection
VREG Undervoltage Bootstrap
CBOOT DC Motor #2
Overtemperature UVLO
UVLOBOOT 0.47 μF
L IRF2807
GH RGATE
High Side
VREF DT Turn-On Driver
33 7
Delay
470
DC Motor #1 k7
Forward IN1
Control
S
Slow Logic
Decay
DC Motor #2 L VREG
IRF2807
Forward IN2
GL RGATE
Slow
Low Side
Decay
Driver
33 7
470
L PGND k7
External
+5 V RESET M
P LGND
L DC Motor #1
L P
Diagram B. Independent drivers. One high-side drive and one low-side drive.
+VBAT
C1
C2 0.47 μF
10 μF
P P
VREF
VREF Charge VREG
+5 Vref
Pump
0.1 uF CREG
10 ILIM
k7 L L P P 10 μF
Top-Off
Charge Pump M M
BOOT
~FAULT
Protection DC Motor DC Motor
VREG Undervoltage Bootstrap #1 #2
Overtemperature UVLO
UVLOBOOT
IRF2807
L
GH RGATE
High Side
VREF DT Turn-On Driver
33 7
Delay
470
DC Motor #1 k7
Forward IN1
Control
S
Slow Logic
Decay
P
VREG
IRF2807
DC Motor #2 L
Forward IN2 GL RGATE
Low Side
Slow
Driver
Decay 33 7
PGND 470
L k7
External
P LGND
+5 V RESET
L
L P
PAD
Pin-out Diagram
LP package
VREG 1 16 VBB
CP2 2 15 VREF
CP1 3 14 DT
GL 5 12 RESET
S 6 11 IN2
GH 7 10 IN1
BOOT 8 9 ~FAULT
CP2 2 Charge pump capacitor, positive side. When not using the charge pump, leave this pin open.
CP1 3 Charge pump capacitor, negative side. When not using the charge pump, leave this pin open.
Low-side gate drive output for external MOSFET driver. External series gate resistor can be used to control
GL 5
slew rate seen at the power driver gate, thereby controlling the di/dt and dv/dt of the S pin output.
Directly connected to the load terminal. The pin is also connected to the negative side of the bootstrap
S 6
capacitor and negative supply connection for the floating high-side drive.
High-side gate drive output for N-channel MOSFET driver. External series gate resistor can be used to
GH 7
control slew rate seen at the power driver gate, thereby controlling the di/dt and dv/dt of the S pin output.
BOOT 8 High-side connection for bootstrap capacitor, positive supply for the high-side gate drive.
RESET 12 Logic control input. When RESET = 0, the chip is in a very low power sleep mode.
Dead Time. Connecting a resistor to GND sets the turn-on delay to prevent shoot-through. Forcing this
DT 14
input high disables the dead time circuit and changes the logic truth table.
0.45
5.00 ±0.10 0.65
4° ±4 16
16
+0.05 1.70
0.15 –0.06
A (1.00)
1 2
3.00
0.25 1 2
0.15 MAX