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B. Baggini, L. Coppero, G. Gazzoli, L. Sforzini *

F. Maloberti, G. Palmisano **

* Italtel Sit, Castelletto di Settimo Milanese, Milano, Italia

** Dipartimento di Elettronica, Universitii di Pavia, Italia


An integrated circuit for the Pan European GSM The integrated circuit (IC) can be applied to both
digital radio systems is described which performs the base and mobile stations, according to G S M
modulation and front-end functions for both base and specifications.
mobile stations. The circuit, fabricated using a 2 pm It is located between the base-band digital signal
CMOS technology, fully meets the GSM requirements. processing section and the RF air interface. The circuit,
shown in Fig. 1, works as follows.
A 270.8 kbit/s input data stream is formatted by the
T D M A burst generator. The input data stream is
differentially encoded by the GMSK digital modulator
INTRODUCTION which generates the in-phase (I) and in-quadrature (Q)
components of the modulated signal phase
The Pan European Group Special Mobile (GSM) trajectories. The I and Q signals are processed through
digital cellular radio system is intended to satisfy the an analog interface formed by two independent analog
increasing demand for mobile communications in branches.
European countries. Each branch is composed of a D / A converter, a
The GSM digital system provides a new standard for switched capacitor lowpass filter and a power
mobile radio communications that overcomes most amplifier.
of the drawbacks of existing analog networks. It makes The IC analog outputs modulate two 900 MHz
several facilities and services available for customers quadrature carriers of the RF section, as illustrated
since it allows both traditional speech communication within the dotted box of Fig. 1.
and data transmission.
The use of digital techniques also guarantees high DIGITAL SECTION
immunity to co-channel interference allowing a more
efficient re-use of frequency carriers and a larger The digital section consists principally of a GMSK
number of subscribers. Moreover, because of the digital modulator, a TDMA burst generator and a
employment of VLSI technologies and very efficient timing and synchronization controller. The
error correcting codes, a communication system with modulator addresses on the basis of 5 successive bits,
high quality performance is achieved. two 256-word ROMs, in which I and Q phase trajectory
The system is based on both the time and the components are stored. Each of the resulting 32 phase
frequency division multiple access technique (TDMA- trajectories is described by means of 8 samples with 10-
FDMA). bit accuracy. The timing and sync controller provides
The assigned radio frequency (RF) bands are in the the requested synchronization signals and timing
range of 890-915 MHz for mobile to base station advance management, using an external 13 MHz
transmission (up-link) and in the range of 935-960 for reference master clock.
reciprocal transmission (down-link). The TDMA burst generator defines frame and time slot
The system uses a Gaussian Minimum Shift Keying data formatting, generates receiving and transmitting
(GMSK) modulation, with. a 0.3 modulation index, windows and turns on the RF power amplifier during
which is characterized by a narrow-band spectrum the burst transmission interval.
unlike traditional Quadrature Phase Shift Keying
(QPSK) modulation.


CH2944-7/91/0000/0496 $1 .OO 0 1991 IEEE

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Master clock
Fig. 1. Block diagram of the overall system.

D/A CONVERTER (2.16 MHz). It is used to reduce the RC smoothing filter

order. The operational amplifier employed
The D / A converter is based on a combination throughout the filter is a folded-cascode structure
resistor-string, capacitor-array approach [l], 121. A
functional diagram is depicted in Fig. 2.
Two half-clock periods are required for a complete
conversion of M+K bits. In the first half-clock period,
01, the M-1 MSBs select, through the switch matrix, two M-1 MSBs
couples of voltages, V I , v 2 and V3, v 4 , from a 2M-1
element resistor-string, which is connected between
the positive full scale voltage, VREF and the analog
ground, VGND. During the second half-clock period,
0 2 , the K LSBS control two binary weighted capacitor-
arrays, CM and CP, connected to the input terminals of --a
a fully differential operational amplifier. During the 4

clock phase ~1 the capacitor bottom plates of CM and

CP are connected to VREF and VGND, respectively, for
discharging and offset sampling operations.
In the next clock phase, @2, the generic capacitor 2i C of
each array is connected to one of the two voltages of
each couple, on the basis of the i-th LSB, bi. In this way
two unipolar voltages ranging from VGND to VREF and
from V G N D to -VREF are available at the amplifier
outputs during ~ 2 Two . sample and hold circuits
sample the differential output voltage according to the
sign bit, bs.
Besides the typical advantages of the mixed approach
Fig. 2. Functional diagram of the D/A converter.
in terms of accuracy and conversion speed, the
proposed arrangement halves the number of tap
resistances, allowing a reduction of die area and TABLE I
improving the absolute linearity. In addition only a
precision voltage reference is required. MEASURED RESULTS OF THE D/A CONVERTER
The key performance of the converter is summarized
in Table I. Resolution 10bit
Differential Linearity Error 0.5 LSB
A schematic diagram of the switched capacitor
lowpass filter is shown in Fig. 3. It was designed from THD at lokHz -68 dB
a third-order passive ladder prototype via signal flow-
graph representation, using approximate LDI design Dynarmc Range 67 dB
technique [31. The filter, clocked at 13 MHZ, has a cutoff
frequency of about 300 kHz and provides 40 dB of SamplingRate 2.16 M H z
attenuation at the sampling rate of the D / A converter

giving 60 dB of dc gain and 50 MHz of gain-bandwidth
The minimum size capacitor was fixed nominally to
0.3 pF in order to guarantee about 65 dB of dynamic
range. Double sampling technique was employed to
relax settling time and slew rate requirements for the
amplifier. Moreover delayed clock phases, as proposed
in 141, were used to reduce charge injection effects
which could increase the total harmonic distortion
(THD) .
A measured frequency response of the filter is shown
in Fig. 4.

Fig. 4. Frequency response of the filter.

stage, two voltage followers and a push-pull output

stage. Two additional common mode feedback
circuits, CMFl and CMF2, stabilize the operating point
both in stationary and dynamic conditions. The input
stage is a folded-cascode scheme providing 60 dB of dc
gain with a non-dominant pole at 100 M H z . The
voltage followers, B1 and 82, drive the input terminals
of the output stage and two nominally equal N-well
resistances, R1 and R2, used for the common mode
feedback circuit.
The output stage was realized with a cross-coupled
pair circuit that exhibits high linearity properties as
demonstrated in [6]. It requires a common mode
feedback circuit, CMFZ, to keep its common mode
output voltage at ground level.
The power amplifier achieves a unity-gain frequency
of 10 MHz and a THD of -70 dB with 4 Vpp differential
swing across a 220 ohm output load.
A measured amplitude spectrum is shown in Fig. 6 .

Fig. 3. Schematic diagram of the third-order

switched capacitor lowpass filter.


The last block of the analog transmission chain

is the power amplifier driving the external RF mixer,
as shown in Fig. 5.
A fully differential structure has been employed in
order to obtain a better rejection to supply noise and a
relatively high gain-bandwidth product. The circuit is Fig. 5. Schematicdiagram of the power amplifier.
similar to the one used previously in [5] for a single
ended design.
The power amplifier consists of a high gain input


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Fig. 6. Amplitude spectrum of the power amplifier.

Fig. 8. Die photo of the integrated circuit.

Experimental results were carried out on
several integrated samples. Some of the main features An integrated circuit for GSM digital mobile
are reported in Table 11. radio system has been presented which performs the
A power spectrum of the RF modulated signal, which GMSK modulation and the analog front-end functions.
shows the overall system linearity and out of band The circuit was fabricated using a 2 wm, double-poly,
noise performance, is depicted in Fig. 7. A die photo of double-metal CMOS process. It dissipates 180 mw with
the integrated circuit is shown in Fig. 8. a single 5 V supply. The die s u e is 6.7 x 5.3 "2.
[l] B. Fotouhi and D. A. Hodges, "High-resolution
State Circuits, vol. SC-14, pp. 920-926, Dec. 1979.
Power Dissipation 180mW
[2] J. W. Yang and K. W. Martin, "High-resolution
Dynamic Range 62 dB low-power CMOS D/A converter", IEEE Int.
Symp. on Circ. and Syst., Helsinki, 1988, vol. 3, pp.
THD at 67kHz -64 dB 2821-2824.
Die Sue 6.7 x 5.3 mm [31 G. M. Jacobs, D. J. allstot, R. W. Brodersen, and P.
R. Gray, "Design techniques for MOS switched-
capacitor ladder filters", IEEE Tran. on Circ. and
Syst., vol. CAS-25, pp. 1014-1021, Dec. 1978.

[4] D. G. Haigh and B. Singh, "A switching scheme for

switched capacitor filters which reduces the effect
of parasitic capacitences associated with switch
control terminals", IEEE Int. Symp. on Circ. and
Syst., Newport, 1983, vol. 2, pp.586-589.

151 J. A. Fisher and R. Koch, "A highly linear CMOS

buffer amplifier", IEEE J. of Solid-state Circuits,
vol. 92-22, pp. 330-334, June, 1987.

[6] E. Seevinck and R. F. Wassenaar, "A versatile

CMOS linear transconductor/square-low function
circuit", IEEE J. of Solid-state Circuits, vol. SC-22,
Fig. 7. RF power spectrum of the modulated signal. pp. 366-377, June, 1987.


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