Documente Academic
Documente Profesional
Documente Cultură
3D IC Integration
Conclusions
2 © 2010 austriamicrosystems
Company milestones
1981 Austria Mikro Systeme (AMS) founded as
joint venture by American Microsystems Inc. (AMI)
and Voest Alpine (Austria)
1993 AMS goes public on Vienna exchange
2000 AMS returns to private status
(major shareholder Permira Private Equity),
becomes austriamicrosystems
2002 New 200 mm (8”) fab goes on-line
2004 IPO on SIX Swiss Exchange in Zurich
2006 New test facility in Asia
2011 Acquisition of Texas Advanced Optoelectronic
Solutions (TAOS)
A leader in high performance analog ICs:
1,100+ employees, 6 design centers,
19 offices worldwide
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Full supply chain under one roof
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Full Service Foundry
- 180nm, 350nm, 800nm - MPW service with cooperation partners - Custom processes
- CMOS, High-Voltage, SiGe, NVM - Benchmark design environment - 3D IC using TSVs
- Automotive and medical certified - Numerous digital & analog IP-cells - RGB & IR Color Coating
- Zero defect program - Standard package assembly service - Extended IP portfolio
- Extended temperature range - In-house mixed-signal test facility - Consultancy: ESD, DFM, DFY, …
- Second source capabilities - Qualification services - Adv. packages: WLCSP, Bumping, …
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austriamicrosystems at a glance
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Our business
Sensors &
Core expertise Power Management Mobile Infotainment
Sensor Interfaces
CONSUMER &
INDUSTRY & MEDICAL AUTOMOTIVE
COMMUNICATIONS
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Corporate responsibility
Total CO2 Emissions (tons eq)
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Worldwide network – design, sales, distribution
• 6 design centers:
Distribution partnerships strengthened
Austria, Switzerland, 2x Italy, Spain, India
Global contracts
• 19 sales offices, over 30 distributors worldwide
with tier 1 players
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Austria – famous for
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But Graz was home of famous scientists too
Johannes
Kepler Leopold
Gottlieb Ernst
Biwald Mach
Ludwig
Boltz-
mann Erwin
Schrödi
Viktor
nger
Franz
Hess
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Let‘s start with Ernst Mach
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Moore‘s Law
1958 (TI)
invention of IC
2011:
Tri-Gate(Intel 22nm):
10 Million Trans./mm²
1947 (Bell Labs) 1 Billion on 100mm².
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austriamicrosystems
Technology portfolio
800nm 350nm 180nm
RF Technologies • RF CMOS
• BiCMOS (SiGe)
HV Technologies • HV CMOS
• Galvanic Isolation
• OTP (Fuse)
Sensor • Hall
technologies • Opto
PFET120M
PFET50T NFETI50M
100
NFET50MH
PFET25M NFETI25M
PFET20T
NFET20MH
10
-160 -120 -80 -40 0 40 80 120 160
BVdss [V]
0.18µm BCD (STM) 0.18µm BCD (Dongbu) 0.25µm BCD (TI) 0.25µm BCD (TSMC) 0.35µm HVCMOS (H35)
0.18µm HVCMOS (XFAB) 0.18µm HVCMOS (H18) one dimensional Silicon limit 0.18µm HVCMOS (TSMC)
Rdson vs. BVdss for HVCMOS (blue closed symbols) and BCD (white open symbols).
AMS 180nm HVCMOS shows largest BVdss range and very low Rdson
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Application Areas of Power Devices
1000 Served by monolithic power ICs
Motor Control
Power Converters/
100
Power Supplies
Current (A)
Lighting Ballast
Automotive
10
Telecommunication
5V CMOS
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Process modularity of 350nm technology
High flexibility through modularity:
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350nm vs. 180nm HV transistor comparison: 20V PMOS
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Process modularity of 180nm technology
High flexibility through modularity:
Non-Volatile
High Voltage
Memory
up to 7 power hi-
metal- 5V OTP
layers of metal (Cu resistive
metal caps transistors (eFuse)
metal and/or Al) polysilicon
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180nm CMOS-HV 20V & 50V
Full modularity with CMOS base process, low mask count
180nm CMOS + HVCMOS
Low-voltage CMOS
52 nm
3.5 nm
12 nm
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Suite of FETs with three gate oxide thicknesses
– Low Voltage (LV) fets for standard 1.8 and 5V CMOS
– LV fets in HV well for high voltage isolation to substrate
– HV asymmetric fets for High Voltage applications
– 3 gate oxide thicknesses, 2 maximum drain bias choices
– HV symmetric fets for specialty applications (transmission gate)
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Floating Logic
Substrate Logic – 350 and 180nm Floating Logic - only in HVCMOS
B S G D D G S B B S G D D G S B PSUB
DPTUB
NTUB
DNTUB
Net +2 additional alignments
PSUB
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CORELIB vs. CORELIB_HV Cell Layout
CORELIB Cell CORELIB_HV Cell
Same Cell Size
SNTUB DNTUB
NTUB
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180nm HVCMOS metal stack options
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HV HSIM_HV Model to Hardware Results
Thin oxide NFET for 50V use Thin oxide PFET for 50V use
8,0E-03 6,0E-03
7,0E-03
5,0E-03
6,0E-03
4,0E-03
5,0E-03
-ID[A]
ID[A]
4,0E-03 3,0E-03
3,0E-03
2,0E-03
2,0E-03
1,0E-03
1,0E-03
0,0E+00 0,0E+00
10
20
25
30
45
50
0
15
35
40
10
15
20
25
30
35
40
45
50
VD[V] -VD[V]
ID(VG=0.45V) ID(VG=0.60V) ID(VG=0.75V) ID(VG=0.90V) ID(VG=1.05V) ID(VG=1.20V)
ID(VG=-0.45V) ID(VG=-0.60V) ID(VG=-0.75V) ID(VG=-0.90V) ID(VG=-1.05V) ID(VG=-1.20V)
ID(VG=1.35V) ID(VG=1.50V) ID(VG=1.65V ID(VG=1.80V)
ID(VG=-1.35V) ID(VG=-1.50V) ID(VG=-1.65V ID(VG=-1.80V)
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Layout for 50V ESD Protection
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More than Moore
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More than Silicon: 3D-IC integration using Through Silicon Vias
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3D technology concept
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3D technology concept
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3D technology concept
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3D technology concept
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3D stacking by means of TSV, BRDL and µbumps 1/3
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3D stacking by means of TSV, BRDL and µbumps 2/3
sensor chips
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3D stacking by means of TSV, BRDL and µbumps 3/3
sensor chips
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3D special integration tools
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Wafer surface
Intrinsic reliability
von Mises
1500
1000
vertical stress
stress (MPa)
0
0.00 50.00 100.00 150.00 200.00 250.00
-500
-1500
tangential stress
270um
64 pixel Photodiode
TSV
NMOS PMOS
Scintillator
PCB
p+ Photodiode
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Summary and Conclusions
The high voltage technologies on the 350nm and 180nm node are ideally suited
for SoC applications
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Some famous last words....
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Benefits
Acknowledgements:
Cathal Cassidy
Heimo Gensinger
Ingrid Jonak
Martin Knaipp
Günter Koppitsch
Jochen Kraft Thank you for your attention!
Franz Schrank
Jörg Siegert
Jordi Teva
Ewald Wachmann
and to FELMI-ZFE
for the excellent co-
operation
47 © 2010 austriamicrosystems