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Set
Sensor
Memory On Off
Alarm
element
Reset
Timing example
A Simple Memory
Element
A B
Stable when
A=1,B=0 or
A=0,B=1
How to get it to
switch states?
A Controlled Memory
Load
Element
A B
Data Output
TG1
TG2
• When Load=1
– Point A gets value of Data
– feedback is disabled
Bistable element
• The simplest sequential circuit
• Two states
– One state variable, say, Q
HIGH LOW
LOW HIGH
Bistable element
• The simplest sequential circuit
• Two states
– One state variable, say, Q
LOW HIGH
HIGH LOW
Analog analysis
• Assume pure CMOS thresholds, 5V rail
• Theoretical threshold center is 2.5 V
Analog analysis
• Assume pure CMOS thresholds, 5V rail
• Theoretical threshold center is 2.5 V
2.5 V 2.5 V
2.5 V 2.5 V
Analog analysis
• Assume pure CMOS thresholds, 5V rail
• Theoretical threshold center is 2.5 V
2.5
4.8
2.51VV 2.5 V
2.0
0.0
2.5 V
2.0
0.0 4.8
5.0
2.5 V
Metastability
• Metastability is inherent in any bistable
circuit
Another look at
metastability
Set-Reset Latch (SR latch)
Q Q
N1 N1
S N2 Q S N2 Q
R
(a) (b)
S
N1 Q
S Q
R Q
N2 Q
R
(c) (d)
S-R (set-reset) Latch
R Truth table
Qa
S R Qa Qb
t1 t2 t3 t4 t5 t6 t7 t8 t9 t 10
1
R
0
1
S
0
1
Qa
0
1
Qb
0
Example
10
• Complete timing diagram R
01 0
Qa
• Assume 1 unit propagation delay
Qb
S 01 0
10
S 1 0
R 1 0
Qa 0 1 0
Qb 0 1 0
NAND SR Latch
S S=0 S=1
S
N1 Q Q
R N2 Q R=0 R=1 Q
R
(a) (b)
S
Q
Q
R
(c)
S Q S Q
R Q R Q
(d) (e)
Set-Reset Latch Timing Diagram
S
R
Q
R
Q
S
Q
Clk
Q
R
Example – Switch Debouncing
• Most mechanical switches will bounce for a short time
(10-20 ms)
• If switch is being used to say, count events, this
leads to erroneous count
VDD
Data
Timing diagram
Example – Switch
Debouncing
• When switch at bottom,
VDD
R=0 and Data=0
• When switch thrown to
R
top, S=0 so Data=1
Single-pole
double-throw S • When switch bounces to
switch Data middle, S=R=1 so Data
retains last value
R S-R latch
VDD
Gated D-Latch
Instead of a
separate set (S)
and reset (R), it is
easier to think of a
latch as storing
some data (D)
• We’ll look at
– D flip-flops
– T flip-flops
– JK flip-flops
Clock Signals for a Latch
Characteristic table
• When Clock=1, master follows the input signal (Qm = D),
slave retains last state
• When Clock goes to 0, master is frozen, slave follows
master (Qs = Qm)
• Thus, Qs takes the value of D when the clock fell ↓
D flip-flop (alternative
design) Positive edge triggered
1 P3
P1
2
5 Q
Clock
P2 6 Q
3
D Q
Clock Q
4 P4
D
Clock Clk Q Qa
Clock
D Q Qb D
Q Qb Qa
Qb
D Q Qc
Q Qc Qc
D Flip-flops with Clear and
Preset
• It is useful to initially force the f/f to a known state
– Clear=0 forces to 0 Preset
– Preset=0 forces to 1 D Q
Q
Preset
Clear
D
Q
Clock
Clear
Master-slave design
Asynchronous vs synchronous
clear and preset
• Asynchronous clear (or preset) – takes effect
immediately
• Synchronous clear (or preset) – takes effect on edge
of clock
Clock Q Q
circuits
Clock
Q
T flip-flop (continued)
• We can design a T f/f out of a D f/f
– If T=0, then make D=Q
– If T=1, then make D=Q’
– So D = TQ’ + T’Q
T flip-flop (continued)
• We can design a T f/f out of a D f/f
– If T=0, then make D=Q
– If T=1, then make D=Q’
– So D = TQ’ + T’Q = T EXOR Q
D Q Q
T
Q Q
Clock
JK flip-flop
J K Q t + 1
0 0 Q t J Q
0 1 0
1 0 1 K Q
1 1 Q t
J
D Q Q
K Q Q
Clock
Flight-Attendant Call Button
Using D Flip-Flop
• D flip-flop will store bit Call
Flight Blue
• Inputs are Call, Cancel, and present
button light
attendant
Cancel call-button
value of D flip-flop, Q button system
8-bit register
D0 D Q Q0
pre
D[7..0]
D1 D Q Q1 Q[7..0]
Clk
clr
Dn-1 D Q Qn-1
Parallel load,
parallel access
Clk
Data[3..0] 0001
serial out
Clock Q Q Q Q
Sample sequence
• Useful for dividing or
multiplying by two
In Q1 Q2 Q3 Q4 = Out
t0 1 0 0 0 0
t1 0 1 0 0 0 • Or for converting serial
t2 1 0 1 0 0 data to parallel
• Unidirection or
t3 1 1 0 1 0
t4 1 1 1 0 1
bidirection
Serial Data Transfer
• Serial mode → Data is transferred one
bit at a time
Shift Register
parallel out
serial in
Q1 Q2 Q3 Q4
In D Q D Q D Q D Q Out
serial out
Clock Q Q Q Q
Sample sequence
Q3 Q2 Q1 Q0
D Q D Q D Q D Q
Q Q Q Q
Serial Clock
input Shift/Load Parallel input
Universal Shift Register
Example Using Registers:
Temperature Display
• Temperature history display
– Sensor outputs temperature as 5-bit binary number
– Timer pulses C every hour
– Record temperature on each pulse, display last three
recorded values
Present 1 hour ago 2 hours ago
Display Display Display
x4 a4 a3 a2 a1 a0 b4 b3 b2 b1 b0 c4 c3 c2 c1 c0
x3
x2
x1 TemperatureHistoryStorage
x0
timer
C
(In practice, we would actually avoid connecting the timer output
C to a clock input, instead only connecting an oscillator output to a clock input.)
Example Using Registers:
Temperature Display
• Use three 5-bit registers
a4 a3 a2 a1 a0 b4 b3 b2 b1 b0 c4 c3 c2 c1 c0
I4 Q4 I4 Q4 I4 Q4
x4
I3 Q3 I3 Q3 I3 Q3
x3
I2 Q2 I2 Q2 I2 Q2
x2
I1 Q1 I1 Q1 I1 Q1
x1
I0 Q0 I0 Q0 I0 Q0
x0
Ra Rb Rc
C
TemperatureHistoryStorage
x4...x0 15 18 20 21 21 22 24 24 24 25 25 26 26 26 27 27 27 27
Ra 0 18 21 24 25 26 27
Rb 0 0 18 21 24 25 26
Rc 0 0 0 18 21 24 25
Counters
• Counts in binary or other codes
• Counters normally count 0 … (2N-1 -1)
– N is the number of bits
• Modulo-N counter
Ripple Counter 3-bit “up”
counter
Also called
1 T Q T Q T Q
“ripple”
Clock Q Q Q counter
Q0 Q1 Q2
Clock
Q0
Q1
Q2
Count 0 1 2 3 4 5 6 7 0
Clk
Alternative Synchronous Counter
1 T Q T Q T Q T Q
Q0 Q1 Q2 Q3
Clock Q Q Q Q
(a) Circuit
Clock
Q0
Q1
Q2
Q3
Count 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1
counter with
1
D0
Q
parallel load
0
D Q Q1
D1 1
0
D Q Q2
D2 1
0
D Q Q3
D3 1
Output
carry
Load
Clock
Cascading Counters
• Example: 8 bit counter
CLK
74x163 74x163
CLK CLK
1 CLR 1 CLR
QA Q0 QA Q4
1 LD 1 LD
QB Q1 QB Q5
1 ENP ENP
1 QC Q2 QC Q6
ENT ENT
QD Q3 QD Q7
A A
RCO RCO
B B
C C
D D
Reset Synchronization
• Counters normally count 0..(2N-1 -1)
• What if you want to count up to some other
limit?
• We can test the current count against the
limit … when it matches, force a reset (or load
zero)
Q2 Q1 Q0
• Example: 0 0 0
– Count from 0..5 on a 3-bit counter 0 0 1
– We’ll check for the value (Q2 Q1 Q0) = (101) 0 1 0
0 1 1
Actually, it is enough to Q2
check for Q2=1, Q0=1 1 0 0
Q1
1 0 1
Q0
Modulo-6
Counter
1 Enable
0 D0 Q0
0 D1 Q1
0 D2 Q2
Load
Clock
Clock
(a) Circuit
Clock
Q0
Q1
Q2
Count 0 1 2 3 4 5 0 1
Load
Clock
Clock
Clear Enable
0 D0 Q0
0 D1 Q1
D2 Q2 BCD 1
0
0 D3 Q3
Load
Clock
Ring Counter
• Generate the sequence of 1-out-of-N words
• Example: 0001, 0010, 0100, 1000, 0001, …
Q0 Q1 Qn ” 1
Start
D Q D Q D Q
Q Q Q
Clock
D Q D Q D Q D Q
Q Q Q Q
Reset
Clock
• Sequence (from reset)?
Johnson
counter
“Twisted ring”
counter
VHDL for Sequential
Circuits
• Storage elements are LIBRARY ieee ;
created using USE ieee.std_logic_1164.all ;
“implied memory” … if
code doesn’t specify ENTITY latch IS
PORT ( D, Clk : IN STD_LOGIC ;
a signal value, then it
Q : OUT STD_LOGIC) ;
keeps its old value END latch ;
is this synchronous
reset or asynchronous
reset?
Changing Register Sizes
• GENERIC statement – define a variable (“compile
time”)
Example – Shift Register
• Can use a hierarchical design
Q3 Q2 Q1 Q0
Shift/load
Serial in D Q D Q D Q D Q Serial
out
D3 D2 D1 D0
D flip-flop with mux
component
Sel
D0 D Q Q
D1
clk
Top level structure
Alternative Design - Shift
Register
what if you
reversed the order
of the assignment
statements?
Counters in VHDL
• Can use arithmetic operators “+”, “-
”
• Need “ieee.std_logic.unsigned.all”
library
Counters – architecture def
Example: 24-bit up/down
counter
LIBRARY ieee ;
USE ieee.std logic 1164.all ; Load L
USE ieee.std logic unsigned.all ; Up/down U 24
Q
ENTITY prob721 IS 24
PORT ( R : IN STD LOGIC VECTOR(23 DOWNTO 0) ; R
Clock, Resetn, L, U : IN STD LOGIC ;
Q : BUFFER STD LOGIC VECTOR(23 DOWNTO 0) ) ; Clock
END prob721 ;
Resetn
ARCHITECTURE Behavior OF prob721 IS
BEGIN
PROCESS ( Clock, Resetn )
BEGIN Parallel load,
IF Resetn = ’0’ THEN
Q <= (OTHERS => ’0’) ; asynch reset
ELSIF Clock’EVENT AND Clock = ’1’ THEN
IF L = ’1’ THEN Q <= R ;
ELSIF U = ’1’ THEN Q <= Q+1 ;
ELSE Q <= Q−1 ;
END IF ;
END IF ;
END PROCESS ;
END Behavior ;
Bus Structures (Sect 7.14.1)
• Bus (a set of wires) common in computers
• Used to transfer data between devices
• Many devices can be attached to the bus
• Only one device can “drive” the bus at a time
• Control signals determine which device can drive
data bus
common
clock
3-state
buffers
control signals