MPC56xx-Power Architeture MCU For Automotive

MPC56xx-
Power Architecture MCU for Automotive

Qian Hua
Automotive System Engineering
TM
Agenda
1. Roadmaps of MPC56xx
2. e200 Core Complex
3. Variable Length Encoding
4. Interrupt Structure of MPC56xx
5. Boot Assistant Module (BAM)
6. Power Arch Ecosystem
TM
Freescale Semiconductor Confidential and Proprietary Information. Freescale™ and the Freescale logo are trademarks
of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. 2
1. Roadmaps of MPC56xx
TM
Cross Family Compatibility
“Monaco” “Pictus” “Bolero” “Spectrum”

(Powertrain) (Steering/Airbag) (Body/Gateway) (Inst Cluster)
System Crossbar Masters Debug System Crossbar Masters Debug System Crossbar Masters Debug System Crossbar Masters Debug
Integration Integration Integration Integration
JTAG JTAG JTAG JTAG
VReg VReg VReg VReg
PowerPCTM
Oscillator e200z3 Oscillator PowerPCTM Oscillator PowerPCTM Oscillator PowerPCTM
Nexus e200z0 Nexus Nexus Nexus
Core FMPLL e200z0 e200z0
FMPLL Core FMPLL FMPLL Display
SIMD DMA Core Core
DMA RTC DMA FlexRay Interface
RTC MMU RTC RTC DMA
Ready
Unit
Interrupt Interrupt Interrupt Interrupt
Controller PIT 4ch 32b
Controller Controller Controller
Cal Bus Interface
MCM
CROSSBAR SWITCH CROSSBAR SWITCH CROSSBAR SWITCH

CROSSBAR SWITCH
Memory Protection Unit (MPU) Memory Protection Unit (MPU)
I/O
I/O 40K I/O I/O Video External
48K Bridge 512Kb 32K 64K
Bridge 1Mb SRAM Bridge Power Sw Bridge RAM Bus
SRAM Flash Boot 512Kb SRAM 1Mb SRAM
Flash Boot Flash Boot Flash (tbd) (208MAPBGA) Boot
Assist
Assist Crossbar Slaves Module Assist Assist
Crossbar Slaves Module (BAM) Crossbar Slaves Module Crossbar Slaves Module
(BAM) (BAM) (BAM)
Communications I/O System
Communications I/O System Communications I/O System Communications I/O System
ADC I/F
Mc PWM
Mc Timer
Mc Timer
Mc Timer
2.5K Code 10 bit 1or2 1 3 eMIOSLite

32 ch 32 ch 2 16 ch 6
sound
eMIOSLite RAM eTPU 2 2 2 650 nsec FlexCAN eSCI DSPI 8ch IO 2 3 4 3 eMIOSLite 2 3 2 40x4
ATD ATD LIN ATD gauge
24ch 12K Data 32 ch. FlexCAN eSCI DSPI 36ch shift I2C FlexCAN LINFlex DSPI 24 ch. CAN DSPI I2C LCD
12bit S&H S&H 12bit Flex 10bit drivers
RAM PWM
mux mux
32
32--bit standard architecture adopted across all product families
Maximum IP reuse
Optimized design and test flow
Consolidated tool chain
Strong Marketing message in compatibility
TM
of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009.
Monaco Up To 1.5M – MPC563xM
Core
• 80 MHz Power Architecture™ e200z3 Core + VLE System
• SPE Module for Floating Point & DSP
Data and Instruction System Debug
integration
• 8 Entry MMU JTAG
Memory
VReg Nexus
• Up To 1.5MB Byte RWW Flash with ECC
• Up To 111kB Total SRAM IEEE
• Up To 94kB on chip static RAM (32kB standby) with ECC Osc/PLL ISTO
e200z3
• 17kB for eTPU (14kB code & 3kB data) 5001-2003
CPU
I/O eDMA SPE
SPE
Interrupt
• Timed I/O Channels 32 channel MMU
Controller
• 32 channel eTPU2 Only quadruple ADC on market,
• 16 channel eMIOS
with built-in filtering system
• 2 x FlexCAN - Compatible with TouCAN, 32/64 Message Buffers
EBI
• 2 x eSCI CROSSBAR SWITCH
allows cost reduction of PCB
• 2 x DSPI 16 bits wide up to 6 chip selects each
• SPI with continuous mode and DMA support development
• Supporting Micro Second Bus, optionally using LVDS &
• 34 channel Dual ADC - up to 12 bit and up to 670ns conversions calibration
• 6 Queues with triggering and DMA support Most precise engine I/O Up To 1.5MB Up To 94kB bus
• Variable Gain Amplifier (X1, X2, X4) Bridge SRAM
• Decimation Filters timers available, control Flash
w/ECC
w/ECC (32kB S/B) Boot Assist
fuel delivery & improve
• Temperature sensor and Absolute voltage reference
Module
System main memory system
• FM-PLL gas mileage SIU (BAM)
• 32 Channel enhanced DMA Controller
• Peripheral Interrupt Timer (PIT) (capable of queue triggering) timed I/O system communications
• System Timer Module (STiM) (for AutoSAR task monitor function)
• Software Watchdog (SWaT) (windowing watchdog)
Temp Sens
3kB 34 ch
1x
SWaT
• Interrupt Controller (plus NMI) Data
STiM
eMIOS eTPU 2x 2x 2x Dual
PIT
• Nexus IEEE-ISTO 5001-2003 Class 2+ (ETPU Class 1) 14kB Dec ADCi
16ch. 32ch. Code FlexCAN eSCI DSPI
• Single 5V Power supply is optional RAM Fil VGA
• EBI for calibration (16/32bit)
• 100, 144 & 176 LQFP/ 208MapBGA(34ADC)
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: MPC563xM products in 208 MAPBGA packaging
TM
Pictus 512K - MPC5604P
Core
System Crossbar Masters Debug up to 64 MHz PowerPC ISA e200 zen0h core
Integration
JTAG
PowerPCTM Memory
VReg e200 512k byte Program Flash with ECC
Core Nexus
4x16k byte Data Flash with ECC
Osc/PLL 40k byte SRAM with ECC
FlexRay I/O
Interrupt eDMA VLE Controller 1 x FlexCAN with 32MB
Controller
1 x Safety port (can be used as additional FlexCAN - 32MB)
1 x FlexRay Dual Channel with 32MB
2 x LinFlex
CROSSBAR SWITCH 4 x DSPI (4 independent chip selects each)
1 x FlexPWM (4x3 channels with 4 Fault Inputs)
1 x eTimer (6 channels incl. quad decode)
1 x eTimer (6 channels for general purpose)
I/O 2 x ADC
64K 2x13 Ch.(4 shared channels), 10bit, conversion time
Bridge 40K
512K DATA <1µsec (2x8ch, 4shared on 100 pin package)
SRAM
Flash Flash •1 x Cross-triggering unit for motor control
Boot Assist
Crossbar Slaves Module (BAM)
System
2 x PLL (one FM-PLL, one for FlexRay)
16Ch eDMA
Communications
Fault Collection Unit
I/O System
16MHz internal RC OSC
eFlexCAN
FlexPWM
4 x DSPI
LINFlex
eTimer
Safety
CTU
Junction Temperature Sensor

ATD
1
2
2
JTAG / Nexus Class 2+

3.3V single supply or 5V supply with external ballast transistor
100 and 144 pins TQFP package
TM
MPC5604/3/2B (Bolero 512k)
System Integration Crossbar Masters Debug
►Family Overview VReg MCM JTAG

PIT 4ch 32b PowerPCTM
►Targeted at mid-range complex control and Power Mgt e200z0
diagnostic applications, such as central body, Oscillator Core Nexus 2+
gateway, and comfort
FMPLL
►FlexCAN module supporting both FIFO and mailbox
data storage, ideal for Controller Area Network Interrupt Controller
(CAN) gateways to manage event driven vs. periodic
bus traffic CROSSBAR SWITCH
►LINFlex module provides a fully automated Local
Memory Protection Unit (MPU)
Interconnect Network (LIN) message management,
reducing CPU load intervention and message
latencies I/O Standby RAM
512K Boot
►eMIOS timer combines multiple counter sources to Bridge
Flash Assist
input capture, output compare and PWM capabilities 32K SRAM
Module
in one very flexible module; PWM function supports 64K Data (BAM)
shifted signal output to improve EMC Flash Crossbar Slaves
►Cross Triggering Unit (CTU) synchronizes PWM
Communications I/O System
output signals with analog-to-digital conversions
►Enables very accurate diagnostic and control
eMIOSLite 36 Ch
capabilities CTU 3
6ch IC/OC ADC
3 4 3 1
FlexCAN FlexCAN LINFlex DSPI I2C
50ch PWM 10bit
Family Differences Note: block diagram represents the MPC5606B
Device Flash SRAM SCI (LINFlex) CAN (FlexCAN) Pins

MPC5604B 512KB 32KB 4 3 64, 100, 144, 208 ( Emul. Only)
MPC5603B 384KB 28KB 4 3 64, 100, 144
MPC5602B 256KB 24KB 3 2 64, 100, 144
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: MPC5604B in 208 BGA package
TM
Key features circled in blue
MPC560xS System Crossbar Debug

Integration Masters
Family Overview VReg
JTAG
►Auto and Industrial Target Applications

Oscillator Power
• Instrument cluster and central display applications Nexus
Architecture
• IDisplay control FMPLL Display
e200z0h
►Display Control Unit RTC
16ch
core Control
DMA
• Enables direct drive of Quarter VGA and Unit RGB / Control
WQVGA. Interrupt
Controller
• Works independently of CPU to fetch, process,
PDI
and display graphics data directly from multiple
sources
CROSSBAR SWITCH
Not just from Graphics RAM
Don’t need huge (expensive) graphics RAM Memory Protection Unit (MPU)
• Can move graphics data from external serial
flash via QuadSPI directly into RAM for DCU Power I/O 160K QuadSPI
too. Mgmt 1 MB 48KB
Bridge Graphics Serial Flash
►SSD is key for cluster Flash SRAM
SRAM Controller
Boot
• Needles calibrate themselves automatically Assist
►Low Power Design 4 x 16EEE Crossbar Slaves
Module
• Designed for dynamic power management of (BAM)
core and peripherals
• Software-controlled clock gating of peripherals Communications I/O System
• Multiple power domains to minimize leakage in
low power modes Stall Detect
36 Ch
eMIOS 2 4 3 2 6 40x4
Because of an order from the United States International Trade Commission, BGA- ADC
24ch FlexCAN LINFlex SPI I2C Gauge LCD
packaged product lines and part numbers indicated here currently are not available 10bit
Drivers
from Freescale for import or sale in the United States prior to September 2010:
MPC560xS products in 208 MAPBGA packages
Family Differences Note: block diagram represents the MPC5606S Launching Q2’10 for auto
Device RAM SRAM TFT Drive LCD Mem Exp Serial Debug Pins
MPC5606S 1 MB 48K SRAM + 160K Display Control Unit (DCU) with 40x4 QuadSPI 2xFexCAN 2xSCI Nexus 176, 144
Graphics RAM Parallel Data Interface (PDI) 3xDSPI 4xIIC
MPC5604S 512 KB 48K SRAM No 64x6 No 2xFexCAN 2xSCI 28KB 144, 100
2xDSPI 2xIIC
TM
MPC5602S 256
Freescale Semiconductor KB and
Confidential 24K SRAM
Proprietary No
Information. Freescale™ and the Freescale logo are trademarks 64x6 No 1xFexCAN 2xSCI 24KB 144, 100
3xDSPI 2xIIC
TM
2. e200 Core Complex
TM
NOMENCLATURE
Power ISA : Power Architecture :

Performance Optimization With Enhanced RISC. A microprocessor
architecture designed by IBM in 1991.
Instruction Set Architecture targeted for Power,

Examples : PowerPC Book E, Book-S , Book VLE
e200, e300(667MHz), e500 (1 GHz), e600 (2GHz), e700 family:

Freescale owned cores, built on Power Architecture technology.
e200 variants in IDC:

e200z0, e200z1, e200z3, e200z4, e200z6 cores intended for low power
and fast interrupt responsive applications.
Freescale MSG SoC :

Spectrum (e200z0), Andorra (e200z4) , Bolero (e200z0), Monaco
(e200z3)
TM
A Brief History of Power Architecture™ Cores
John Cocke
designs IBM 801 MOT designs 85XX
Patterson designs IBM (e500) bookE
RISC I & II designs IBM designs 970
Hennessey IBM & MOT 4XX
designs MIPS design IBM designs cell
603(e300)
1970’s 1980’s 1991 1993 1996 1999 2002 2005 2007

Also:
AMCC,
PA-Semi, …
IBM designs IBM & MOT MOT designs FSL
R/S 6000 design 75X 74XX (e600) designs
IBM & MOT e200 &
Henson:
design 601 e700
e200 was
designed in
2003
RISC means:
• Fixed length instructions “To a very large extent, application program compatibility has
• Load/store instructions been maintained throughout the history of the architecture, with
• Non-destructive the main exception being application exploitation of APUs.”
register-to-register operations (Power ISA™ Version 2.03)
• Large register file
TM
The Evolution of Power ISA
TM
e200z Core Roadmap
10-stage pipeline
Up to 32k cache
Dual Issue /VLE
7-stage pipeline e200z7
Up to 32k cache 5-stage pipeline
266MHz
VLE FPU SIMD
Up to 16k cache
Performance / Features
7-stage pipeline
e200z6 Dual Issue / VLE
200MHz
Up to 32k cache e200z4
FPU SIMD 120MHz
e200z6 FPU SIMD
144MHz
FPU SIMD 4-stage pipeline
VLE
e200z3 4-stage pipeline

80MHz VLE
FPU SIMD 4-stage pipeline
e200z1
80MHz VLE Only
e200z0
80MHz
2004 2005 2006 2007
TM
e200 Overview: Core Diagram (e200z7)
OnCE / Nexus CPU Control SIMD & EFP

Control Logic Logic SPR Units
LR,
CR,
CTR, Integer
GPR
XER
Execution
Unit
Memory
Management
Instruction Bus Interface Unit
Address
Unit Instruction Unit Multiply Unit

32
Instruction Cache Instruction Buffer

Control
Data
External
64
PC Branch SPR Data

Unit Unit Interface
Control
Load / Store Unit

N
Data Cache
Data Bus Interface Unit

32 64 N
Address Data Control
TM
Programming Model: Core Overview (Power Architecture e200zX)
► Single and Dual issue architectures
• Multiple execution units:
Integer Unit: arithmetic, logical, etc. instructions
Instruction Unit: single cycle execution of successful look-ahead branches
Load / Store Unit: pipelined for single cycle execution
► 32 General Purpose Registers (GPRs)

• 32 bits wide
• Computations are performed on GPRs (not memory)
► Special Purpose Registers (SPRs)

• Used for a dedicated special purpose
• Read and writing SPRs is done throught a GPR
► Architectural Extensions via Auxilary Processing Units (APU):

• Signal Processing Engine (SPE): SIMD / DSP instructions
• Single Precision Floating Point: includes int to float, float to int
► Cache and MMU

• Unified/Harvard cache; some can be allocated for fast general purpose SRAM
• MMU protects and partitions code and data space
• MMU can be used to assist calibration
TM
Programming Model: Core Overview (Device Specific)
e200z4 e200z3
e200z7 e200z6 e200z1 e200z0
Feature (Andorra, (MPC5500,
(Mamba) (MPC5500) (MPC5510) (MPC5510)
Leopard) Monaco)
Instructions Two 32-bit Two 32-bit Two 32-bit Two 32-bit One 32-bit One 32-bit
fetched per or or or or or or
clock Four 16-bit Four 16-bit Four 16-bit Four 16-bit Two 16-bit Two 16-bit
Pipeline Size 10 Stage 7 Stage 5 Stage 4 Stage 4 Stage 4 Stage

Unified
Bus (MPC5500)
Harvard Unified Harvard Unified Harvard
Architecture Harvard
(MPC5600)
SPE APU Yes Yes Yes Yes - -
16K Instruction
Cache 16K Data
8K / 32K Unified 4K Instruction - - -
MMU 64 Entry 32 Entry 16 Entry 16 Entry 16 Entry -
TM
Programming Model: User Mode Registers 1 of 2
User level registers can be accessed by all software with either User or Supervisor
privileges. They include :
GPR0 ► Thirty-two 32-Bit GPRs*1 (GPR0–GPR31) serve as data source
GPR1 or destination registers for integer instructions and provide
data for generating addresses.
GPR31
CR ► Condition Register consists of eight 4-bit fields, CR0–CR7, that

reflect results of certain arithmetic operations and provides a
mechanism for testing and branching.
CTR ► CounT Register holds a loop count that can be decremented

during execution of appropriately coded branch instructions. It
also provides the branch target address for the Branch
Conditional to Count Register (bcctr, bcctrl) instructions.
LR ► Link Register provides the branch target address for the Branch
Conditional to Link Register (bclr, bclrl) instructions, and is used
to hold the address of the instruction that follows a branch and
link instruction, typically used for linking to subroutines.
XER ► Integer Exception Register indicates overflow and carries for
integer operations.
*1 – 64-bit Range on e200z7/6/4/3
for SPE
TM
Programming Model: User Mode Registers 2 of 2
Applicable
to e200zX
USPRG0 ► User SPR General register (USPRG0) is accessible in
a read-write fashion by user-level software.
Z SPRG4(ro)
0 SPRG5(ro) ► PowerPC Book E architecture defines SPR General registers
Z
SPRG6(ro) (SPRGx) and a User SPR General register (USPRG0).
3
• SPRG4 through SPRG7 are read only for user-level software.
Z SPRG7(ro)
4 &
TBU(ro) ► The TB is a 64-bit structure provided for maintaining
& Z the time of day and operating interval timers. It is
1 0…..………... divided into two 32-bit registers.
TBL(ro)
Z .31 Time Base Upper (TBU).
•
6 32…………... Time Base Lower (TBL).
•
• TBU and TBL read only in User mode.
..63
&
SPEFSCR ► SPE Status and Control Register
. (read-write) is used
Z
for status and control of both FP or SPE
7 instructions.
L1CFG0(ro) ► L1 Cache Configuration Register (read-only) allows
software to query the configuration of the L1 Cache.
TM
Programming Model: e200z7 Register Overview
e200zX Book E Registers
Supervisor Mode Base Register Set User Programmer’s Model
Hardware Cache Flush
Machine State GPR0 Implementation & Invalidate
SPR General
Register GPR1 Dependent
Registers L1FINV0
Registers
SPRG0 MSR L1FINV1
HID0
Processor Version GPR31 Cache Control
SPRG1
PVR HID1 L1CSR0
LR CR

Processor ID XER CTR System Version L1CSR1
SPRG9 SPEFSCR USPRG0
PIR SVR
Cache Config
Interrupt Vector L1CFG0
Debug Facilities Register Set Interrupt Register Set Offset Registers L1CFG1
Debug Instruction Save & Restore Critical S/R Interrupt Vector IVOR32 BTB Control
Control Addr. Compare Registers Registers Offset Registers

BUSCR

DBCR0-2 IAC1-8 SRR0 CSRR0 IVOR1 IVOR35 MMU Control
Debug Status SRR1 CSRR1
and Status

DBSR MMU Assist MMUCRS0
Data Exception IVOR15
Data Address Compare Machine Check Address MAS0 MMU Config
DAC1 DAC2 S/R Registers
DEAR Interrupt MMUCFG
MCSRR0 Vector Prefix
Data Value Compare Syndrome MAS4 TLBCFG0
DVC1 DVC2 MCSRR1 ESR IVPR MAS6 TLBCFG1
e200zX Specific Registers

Storage Control Register Set Timer Facilities Register Set Debug Counter Debug Control
Process Identification Register Control Decrementer Time Base
DBCNT DBCR3-6
& Status Auto Reload Upper/Lower
PID0 TCR TBL
DEC Debug Save & Restore
TSR DECAR TBU DSRR0 DSRR1
TM
SPR General
Registers L1FINV0
Registers
SPRG0 MSR L1FINV1
HID0
SPRG1
PVR HID1 L1CSR0
LR CR

PIR SVR
Cache Config

BUSCR

and Status

Data Value Compare Not Syndrome MAS4 TLBCFG0
DVC1 DVC2 Available
MCSRR1 ESR IVPR MAS6 TLBCFG1
on e200z6
DBCNT DBCR3
PID0 TCR TBL
TM
SPR General
Registers L1FINV0
Registers
SPRG0 MSR L1FINV1
HID0
SPRG1
PVR HID1 L1CSR0
LR CR

PIR SVR
Cache Config

BUSCR

and Status


DBCNT DBCR3-6
PID0 TCR TBL
TM
SPR General
Registers L1FINV0
Registers
SPRG0 MSR
HID0
Processor Version GPR31 Cache
SPRG1
HID1
ReadControl
Only
PVR LR CR L1CSR0
on e200z3
Processor ID XER CTR System Version
PIR SVR
Cache Config
Debug Facilities Register Set Interrupt Register Set Offset Registers

BUSCR

and Status

MCSRR0
Not Vector Prefix
DVC1 DVC2 Available
MCSRR1 ESR IVPR TLBCFG1
MAS6
on e200z3
DBCNT DBCR3
PID0 TCR TBL
TM
SPR General
Registers L1FINV0
Registers
SPRG0 MSR
HID0
Processor Version GPR31 CacheNot
Control
SPRG1
PVR HID1 L1CSR0

LR CR Available
Processor ID XER CTR System Version on e200z1
PIR SVR
Cache Config

BUSCR

and Status

MCSRR0
Not Vector Prefix
DVC1 DVC2 Available
MCSRR1 ESR IVPR TLBCFG1
MAS6
on e200z1
DBCNT DBCR3
PID0 TCR TBL
TM
SPR General
Registers L1FINV0
Registers
SPRG0 MSR
HID0
SPRG1
PVR HID1 L1CSR0
LR CR

Processor ID XER CTR System Version
PIR SVR
Cache Config

Not BUSCR

IAC1-8
DBCR0-2 SRR0 CSRR0 IVOR1 IVOR34 Available
MMU Control
Debug Status SRR1 CSRR1 on e200z0and Status


Process Identification Register Control Not
Decrementer Time Base
DBCNT DBCR3
& Status Auto
Available Reload Upper/Lower
PID0 TCR TBL
on e200z0
TM
Programming Model: Machine State Register (MSR)
Applicable
to e200zX
MSR Implemented Bit Fields
Bit Name Description Reset
Z
3 14 CE Critical interrupt Enable 0 (Disabled)
& 16 EE External interrupt Enable 0 (Disabled)

Z
Z 1 17 PR Problem state 0 (Supervisor)
4 0: Supervisor mode
& 1: User mode
&
Z 19 ME Machine check Enable 0 (Disabled)
Z 0
6 22 DE Debug interrupt Enable 0 (Disabled)
& 26 IS Instruction address Space (not implemented on z0) 0 (Disabled)
Z 27 DS Data address Space (not implemented on z0) 0 (Disabled)

7
6 SPE Signal Processing Engine Enable 0 (Disabled)
TM
SPR General
Registers L1FINV0
Registers
SPRG0 MSR L1FINV1
HID0
SPRG1
Processor Version
PVR
User Mode
GPR31Registers
HID1
Cache Control
LR CR L1CSR0

PIR SVR
Cache Config

BUSCR

and Status

DVC1 DVC2 Supervisor Mode Registers
MCSRR1 IVPR ESR MAS6 TLBCFG1

DBCNT DBCR3-6
PID0 TCR TBL
TM
Programming Model: Enter/Exit User Mode
Entering and Exiting User Mode
Supervisor Mode User Mode
• Set the Problem State (PR) bit in the Machine State
Register (MSR) to 1
User Mode Supervisor Mode
• Trigger Software Interrupt (in INTC) or System Call Interrupt
(use “se_sc” instruction)
• When Interrupt is taken, MSR is changed automatically to
supervisor mode.
• In ISR, mask PR bit in SRR1 and set to 0 (Supervisor Mode)
• When Interrupt completes (via “rfi” instruction) the core will be
restored to supervisor mode
TM
Programming Model: ABI Register Use 1 of 2
► The Application Binary Interface (ABI) for the e200 is the e500 ABI,
which is based on the Embedded Application Interface (EABI).
► This ABI defines certain registers to have dedicated uses:

• Stack pointer is r1
• Small data area pointers r2 and r13
► If registers need to be saved across a function call:

• Nonvolatile registers must be saved by called function
• Volatile registers must be saved by calling function
TM
Programming Model Reference: ABI Register Use 2 of 2
r0 function linkage volatile acc* SPE accumulator volatile
r1 stack frame dedicated cr0-cr1 condition reg. fields volatile

pointer
r2 small data area 2 dedicated cr2-cr4 condition reg. fields non-

pointer volatile
r3-r4 parameters/return volatile cr5-cr7 condition reg. fields volatile

values
r5-r10 parameters volatile lr link register volatile
r11-r12 function linkage volatile ctr count register volatile
r13 small data area dedicated xer integer exception volatile

pointer reg.
r14-r30 local variables non- spefscr** SPE float limited-

volatile status/control access*
*Bits may be changed only by a called function which has the
r31 local variables / non- documented effect of changing them (per PIM document)
env pointer volatile ** Not implemented on e200z0, e200z1 cores
TM
Programming Model: ABI Stack Frames
High Addresses
► Stack grows from high to low •••
addresses last parameter save area
• Only created when necessary last LR save area
• Size varies as needed last back chain
• 16-byte alignment required 32-bit GPR save area
CR save area (+ pad)
local variable space (+ pad)
parameter save area
LR save area
r1 back chain
Low Addresses
TM
3. Variable Length Encoding
TM
Problem: Cost of Flash Memory Size
►Cost is a key factor in embedded applications

• Memory required to store software code is inherently
system cost
• Historically, RISC machines have been designed for
performance, not optimal code density
• Embedded (integrated) flash memory is required for 2003
MPC5554
many applications, and flash sizes are increasing 34,000,000 Transistors
MCU/DSP/IO Processing
significantly over time System: 2.0MByte Flash
Memory
2000
MPC565
1998 14,000,000 Transistors
1982 1990 MPC555 32 Bit RISC CPU
MC68300 Transistors 1.0MByte Flash Memory
MC6801
Transistors 200,000 Transistors 32 Bit RISC CPU
8-bit CPU 32-bit CPU
2MB
1MB
448KB
TM
of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009. Slide 33
VLE Technology Overview
• VLE is a re-encoding of the PowerPC™ ISA into 16-bit and 32-bit instructions, which may
be freely intermixed
► VLE instructions are 16-bit aligned
• no restrictions on label or subroutine alignment
• no restrictions on cache line occupancy
► VLE/PowerPC code is fully intercallable
• PowerPC extensions remove restrictions on VLE instruction alignment when calling PowerPC from
VLE
• VLE destinations must be 32 bit aligned to be callable from PowerPC via branch or branch-and-link
► PowerPC or VLE execution is determined by MMU entry attribute
Book E Instructions
MMU Entry 1 VLE = 0
CPU
MMU Entry 2 VLE = 1
VLE Instructions
System Memory/Cache
TM
VLE: VLE Encoding Mnemonics
► VLE Instructions have exact or similar semantics to BookE

instructions
► Some 32-bit BookE instructions do not need full 32-bit instruction

size
► 16-bit Power™ VLE instructions encoded with “se_” prefix
► 32-bit Power™ VLE instructions encoded with “e_” prefix
stw // BookE 32-bit instruction (not used on e200z0)

e_stw // 32-bit Power™ VLE instruction
se_stw // 16-bit Power™ VLE instruction
TM
VLE: VLE 32-Bit Instructions
► Equivalents for (nearly) all 32-bit BookE instructions

• Typical VLE 32-bit instruction is 3 operand
• Access to all 32 GPR’s
• Larger literal sizes compared to 16-bit instructions
► 32-bit VLE instruction

• e_add16i (32-bit add immediate) instruction
e_add16i rT, rA, SI
– RT - Destination Register
– RA - Source Register
– SI – 16-bit Integer
OPCODE RT RA SI
0 6 11 16 31
TM
VLE: VLE 16-Bit Instructions
‘se_li’ instruction ‘se_sub’ instruction

7-bit integer limit 4-bit range on GPRs
4-bit range on GPRs
OPCODE RY RX
OPCODE 0b0000111 r4
0 5 7 12 15
0 5 12 15
► ~70 16 bit instructions
► VLE 16-bit encodings have same constraints as other 16-bit ISAs.

• Typical VLE 16 bit instruction is 2-operand, not 3 operand
• Many zero-operand instructions encoded in 16 bits
Breakpoint, rfi, return (branch thru link register),switch (branch thu counter
register)
• Access to just 16 of the 32 GPR’s (4-bit range)
• Limited literal sizes
TM
VLE: VLE Example – Branching
► ‘Branch’ VLE Encoding Example

• Require an instruction which will jump (branch) to an instruction with an
offset of 0x8 from the current instruction
• e_b 0x8 - PowerPC VLE 32-Bit Encoding
24-bit offset
OPCODE 0b000000000000000000001000
0 5 6 7 30 31
• se_b 0x8 - PowerPC VLE 16-bit Encoding

8-bit Offset
OPCODE 0b00001000
0 5 6 7 8 15
TM
VLE: VLE Encoding Example – OR
► ‘OR’ VLE Encoding Example

• or r4,r5,r6 - OR contents of r4 with r6 - Store in r5
• or r4,r5,r6 - PowerPC BookE 32-Bit Encoding
Destination, Source A, Source B Register
OPCODE r4 r5 r6 OPCODE
0 6 11 16 21 30 31
• se_or r4,r5 - PowerPC VLE 16-bit Encoding

Source A, Source B (destination) Register
OPCODE r4 r5
0 5 7 12 15
TM
VLE: Enabling VLE
“What is required to enable VLE?”
1. For existing “C” functions – switch in the compiler call is required
-tPPC5534VES:simple
GHS – Build Options Windriver – Makefile
2. MMU needs to have VLE bit enabled for the memory space with
VLE code
TM
Compiler Results for VLE
Using VLE with Green Hills Compiler

(MULTI v4.0.7 compared to MULTI v4.0.4 non-VLE)
Benchmark Code Size Reduction Notes
Freescale general purpose code 30.4%
EEMBC 32.2% Versions 1.1 and 2.0
SpecINT95 29.2%
Freescale Bench Powertrain Code 29.4%
OEM "X" Powertrain Code 28.6%
Will get smaller when customer
Tier1 "Y" Powertrain Code 25.6 - 28.9% uses all features (additional 5-8%
projected)
For 2008 project, 21.1% smaller
Tier1 "Z" Powertrain Code 30.5% than today's shipping non-PPC
processor
>VLE provides approximately 30% code efficiency gain

> Less than < 5% performance impact
TM
4. Interrupt Structure on MPC56xx
TM
8 Software Interrupts: MPC563x Interrupt Structure
1 Watchdog
1 PIT
1 RTI Machine Check
1 ECC Error Data Storage
34 DMA Instruction Storage
2 PLL External Input
6 IRQ Pins Alignment
16 eMIOS Program
33 eTPU Float. Point Unavailble CPU
31 eQADC System Call Interrupt
10 DSPI AP Unavailable
2 eSCI Decrementer
40 FlexCAN Fixed Interval Timer
Watchdog Timer
Interrupt Request Sources
Data TLB Error
Interrupt Controller Instruction TLB Error Exception Sources
204 Interrupt Request Sources
Debug
CPU Core
SPE Unavailable
SPE Data
SPE Round
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or 43 TM
service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006.
Interrupts: MPC563xM Interrupt Vectors
(Ref.: Book E Table 7-3 & e200z6 Core R.M.)
IVORx Interrupt Type Enables* State Examples

Saved In
IVOR1 Machine Check ME CSRR0:1 Cache parity error
IVOR2 Data Storage - SRR0:1 Incorrect privilege mode for R/W access
IVOR3 Instruction Storage - SRR0:1 Incorrect privilege mode for instruction
IVOR4 External Input EE, src SRR0:1 Peripherals, IRQ pins, software
IVOR5 Alignment - SRR0:1 Load or store operand not aligned
IVOR6 Program - SRR0:1 Illegal instruction, trap
IVOR7 FP Unavailable - SRR0:1 FP instruction attempt with MSR[FP]=0
IVOR8 System Call - SRR0:1 System call, “sc”, instruction
IVOR9 Aux. Proc. Unavail. - SRR0:1 Instruction attempt to non-configured APU
IVOR10 Decrementer EE, DIE SRR0:1 Decrementer timeout
IVOR11 Fixed-Interval Timer EE, FIE SRR0:1 Fixed-interval timer timeout
IVOR12 Watchdog Timer CE, WIE CSRR0:1 Watchdog timeout when ENW=1, WIS=0
IVOR13 Data TLB Error - SRR0:1 Data TLB miss in MMU
IVOR14 Instruct’n TLB Error - SRR0:1 Instruction TLB miss in MMU
IVOR15 Debug DE, IDM CSSR0:1 ROM Debugger when HID0[DAPUEN]=0
DE, IDM DSRR0:1 ROM Debugger when HID0[DAPUEN]=1
IVOR32 SPE APU Unavail. - SRR0:1 SPE APU instruction when MSR[SPE]=0
IVOR33 SPE Float-pt Data - SRR0:1 SPE FP data exception
IVOR34 SPE Float-pt Round - SRR0:1 Inexact result from floating-point instruction
* CE, ME, EE, DE are in MSR. DIE, FIE, WIE are in TCR. “src” is individual enable for each INTC source.
Debug interrupt, IVOR15, also requires EDM = 0 (EDM and IDM are in DBCR0).
Interrupts: Typical CPU Interrupt Behaviour
Interrupt is recognized
Some interrupts use
CSRR[0..1] (critical) or
Hardware context switch: DSRR[0..1] (Debug)
instead of SRR[0..1]
1. SRR0*: Loaded with address of
• Next Instruction, or
• Instruction causing the interrupt
2. SRR1*: Loaded with
• Bits 16:31 - MSR bits 16:31
• Bits 16:31 – exception specific information
3. MSR: All bits are cleared except ME,CE,DE
4. Instruction Pointer: points to unique interrupt vector
Use rfci, rfdi
when CSRR[0..1]
Software Interrupt handler (at interrupt vector) or DSRR[0..1]
are used
• Last instruction, rfi, (return from interrupt):
- Restores MSR bits 16:31 from SRR1
- Restores instruction pointer from SRR0
INTC: SW vs HW Vector Mode
Software Vector Mode (HVEN = 0) Hardware Vector Mode (HVEN = 1)
All external interrupt are auto-vectored (by hardware) to All external interrupts each has its own unique auto-vectored
IVOR4 ISR entry address as below: (by hardware) ISR entry address as below:
IVPR (16-bit) IVOR4 (12-bit) 0000 IVPR (16-bit) 000 INTVEC (9-bit) 0000
The software ISR handler of IVOR4 is responsible for The 9-bit INVEC filed is automatically updated by CPU when
Vector vectoring of the exact external interrupt ISR entry address as external interrupt request is asserted.
Address below: While all other types of interrupts except the external
interrupts ISR entry remain the same as that of in software
VTBA (20/21-bit) INTVEC (9-bit) 00/0 vector mode as below:
The 9-bit INVEC filed is automatically updated by INTC when
external interrupt request is asserted. IVPR (16-bit) IVORn (12-bit) 0000
Step1-HW: Step1-HW:
- Backs up machine state to SRR0:1 - Backs up machine state to SRR0:1
- Disables interrupts except CE, ME, DE - Disables interrupts except CE, ME, DE
- INTC updated the 9-bit INTVEC field of INTC_IACKR - INTC updated the 9-bit INTVEC field of INTC_IACKR
- Takes External Input Interrupt based on IVPR and offset (for - Takes unique IRQ vector based on IVPR and offset which
“IVOR4”) matches INTVEC
Step2-SW Prolog: Step2-SW Prolog:
- Saves SRR0:1* - Saves SRR0:1*
ISR Handler - Reads INTC_IACKR[INTVEC] - Re-enables MSR[EE]*
- Re-enables MSR[EE]* - Saves other registers
Workflow - Saves other registers Step3-SW ISR (clears interrupt flag)
- branches per INTC_IACKR[INTVEC] Step4-SW Epilog:
Step3-SW ISR (clears interrupt flag) - Executes mbar to ensure IRQ flag cleared
Step4-SW Epilog: - Restores most registers
- Executes mbar to ensure IRQ flag cleared - Disables EE* and writes to INTC_EOIR
- Restores most registers - Restores remaining registers and returns (rfi)
- Disables EE* and writes to INTC_EOIR
- Restores remaining registers and returns (rfi)
Steps marked in * are required if interrupt nesting is supported.

Different procedures between hardware and software vector modes are highlighted in blue.
INTC: Software INTC Interrupt Example
SRR Updated
MAIN with return
address and
Program IVOR4 Handler ISR VECTOR Table
current MSR
MSR updated to Base Address ISR0
{ IVOR4 Interrupt Prologue: VTBA
disable further ISR1
from INTC
……. EE Int’s (1) Save SRR’s to stack ISR2
ISR3
……. (2) ReadPrologue
IACKR to:
IVOR VECTOR Table
- acknowledge interrupt ISRn
} Base Address IVOR0 (to prevent servicing same
IVPR IVOR1
interrupt again) ISR293
IVOR2
IVOR3 - automatically return
physicalJump to ISR
address of ISR
IVOR4
IACKR = Contents of
(3) Store IACKR (VTBA + Interrupt #)
IVOR15 (4) Re enable interrupts in
MSR Epilogue
Jump to address in Prefix
Register (IVPR) + offset (5) Save GPR’s to stack Current
ISRnPriority
of 0x40 for IVOR4 (6) Branch with link to { Register (CPR)
IACKR (ISRn Address) updated
Context Save with
…….current interrupt
Note – MSR is updated based on current exception priority to
(For CE: ME and EE are also disabled) Context Restore
prevent pre-
}
EE = External Exceptions (All IVOR4 are EE) emption of <=
ME = Machine Exceptions priority int
CE = Critical Exceptions (Incl Watchdog)
INTC: Software INTC Interrupt Example
MAIN
Program IVOR4 Handler
{ Epilogue:
Write to EOIR
……. resets the CPR
back to previous
……. (1) Write mbar to finish
Prologue value so lower
any data transfers
priority interrupts
} in progress
are no longer
(2) Write to EOIR (End masked
of interrupt
Jump register)
to ISR
(3) Restore GPR’s
from stack
RFI Causes: (4) Disable Interrupts
(1) Branch back to Epilogue
origin (held in SRR0) (5) Restore SRR’s ISRn
(2) Restore of original from stack {
MSR from SRR1 (6) Execute RFI Context Save
…….
Context Restore
}
INTC: Hardware Interrupt Example
SRR Updated
MAIN with return handler_0
address and
Program Prologue
current MSR
{ MSR updated to ISR
Interrupt_n disable further Prologue saves
……. EE Int’s SRR registers Epilogue
……. and GPR as per
VECTOR Table
software vector ---
} Base Address b_handler_0 mode
IVPR + 2KB b_handler_1 handler_n
b_handler_2
b_handler_3 Prologue
Current Priority
ISR
Register (CPR) b_handler_n
updated with
b_handler_293 Epilogue
current intterupt
priority to Jump to address vector calculated Epilogue follows ---
prevent pre- as IVPR + 0x800 + (Vector x 4) same format as
emption of <= per software handler_293
priority int vector mode Prologue
ISR
Epilogue
5. Boot Assistant Module (BAM)
TM
BAM
Boot Mode Selection
Notes: Two boot modes are supported
- The gray modules are done by hardware automatically.
-Single Chip: boot from the first
- The white modules are done by BAM.
bootable section of the Flash main
array.
- Serial Boot: download boot code
from either LINFlex or FlexCAN
interface and then execute it.
Boot from Single Chip Mode
MPC560xB Flash is partitioned into boot sectors as

shown in the left diagram. Each boot sector contains at
offset 0x00 the Reset Configuration Half-Word (RCHW)
In single chip boot mode the hardware searches a
flash boot sector for a valid boot ID. As soon the device
detects a bootable sector, it jumps within this sector and
reads the 32-bit word at offset 0x4. The word is the
address where the startup code is located.
If a valid RCHW is not found, the BAM code is
executed, in this case, BAM just put MPC560xB into
static mode (low power SAFE mode).
BAM Overview
BAM is only executed in either one of the

following two cases:
Serial boot mode is selected by FAB pin
Hardware has not found any valid ID in boot
sectors.
If one of above case is true, the device
fetches code at address 0xffff_c000 and
execute the BAM software.
BAM Logic Flow
Serial Protocol
Boot from UART
Boot from FlexCAN
Password Check Flow
6. Power Arch Ecosystem
TM
Debug, Software & Tools
MPC560xB debug support – JTAG/Nexus2+
System Crossbar Debug Includes Nexus Class 1 (i.e. JTAG)
Integration Masters
VReg MCM
JTAG • Standard interface
PIT 4ch 32b • High speed
Power Mgt PowerPCTM Nexus 2+
Oscillator e200z0 • Run control
Core
FMPLL
• Flexible breakpoint and watchpoint
Interrupt
Controller set-up (4 IAC, 2 DAC)
• register/memory R/W
CROSSBAR SWITCH
Memory Protection Unit (MPU)
• minimum of 6 pins required
Class 2 adds the following (only on 208
I/O packages):
512K Standby RAM
Bridge
Flash
32K SRAM Boot
• Full duplex communication
Assist
64K Data
Flash Crossbar Slaves Module
• Non-intrusive program trace
(BAM)
• Ownership trace
Communications I/O System • Watchpoint messaging
And Class 2+ provides (only on 208
CTU
eMIOSLite 36 ch 3 4 3 1
6ch IC/OC ADC FlexCAN LINFlex DSPI I2C packages):
50ch PWM 10bit
• Read/Write access to memory
locations while CPU is running
Nexus: Nexus/ JTAG Schematic
Source: Carl Culshaw
Nexus: Nexus Fundamentals
ICE works by replacing the MCU with an emulator.
• Trace information is extracted by snooping the bus with an analyser
Nexus works by utilising an on-chip debug engine (which can be controlled by JTAG
or a Nexus Auxiliary port).
• Trace information is obtained non-intrusively by the Nexus engine, capturing the
information from the CPU and sending it to the debug tool via a nexus port on the
MCU.
• This trace information is captured by the debug tool and sent to the PC for off-line
analysis.
Target Application
PC
Nexus Probe
Large Trace Buffer

/ Dual port RAM USB or
Ethernet
Nexus Debug
Connector
Nexus: Nexus Class Definition
The Nexus standard defines
4 “classes” of debug from
class 1 static debug, through Class 1 Run time
to class 4 advanced debug control
with port replacement and Run Time Control
memory substitution.
Class 2
Dynamic Debug
Class 3
Data Trace
Class 4
Memory and
Advanced Debug port
substitution
Nexus: Nexus Class Definition – Class 1
Class 1 Class 1
Run Time Control
• Read/Write MCU registers / memory
Class 2 • Set / Clear Breakpoints
• Stop / Start code execution
Dynamic Debug • Control entry into / exit from debug
mode (from reset and user modes)
Class 3 • Stop execution on hitting a breakpoint
and enter debug mode
Data Trace • Single step instructions
• Read Nexus device ID
Class 4
Advanced Debug
Nexus: Nexus Class Definition – Class 2
Class 1 Class 2
Run Time Control All class 1 features plus:
• Ownership Trace Messages – Real
Class 2
time process / task ownership tracing)
Dynamic Debug • Watchpoint Messaging – Trigger a
nexus message on an event
Class 3
• Program Trace Messages – Real time,
Data Trace non intrusive instruction trace
Class 4
Advanced Debug
Developed in house
Developed offshore SW and Tools Market Coverage
3rd Party ownership
Autosar MCAL 2.1 Autosar OS

Autosar environment
Autosar MCAL 3.0 Autosar BSW
(SW & Tools)
Autosar OS Tresos Auto Core
FlexRay Drivers Flash Drivers Vector CAN Driver
Software Drivers LIN 2.1 Drivers FEE Drivers Sound Generation Drv
J2602 Drivers MC Complex Drv Stepper Motor Drivers
Graphic Library DSP lib

Software Libraries
General Motor Control eTPU+ Libs
RAppID Init Simulink Support

Tools
RAppID Toolbox
System Simulation
GHS Compiler Lauterbach Debugger PLS Debugger

Compiler & Debugger GNU Compiler iSystem Debugger P&E Debugger
GHS Time Machine Cosmic eTPU Compiler
Wind River Compiler CodeWarrior Compiler
Starterkit and evaluation boards EVB Mini Modules Adapters
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or TM
Pin Allocation Wizard - Screenshot
XPC56xxEVB - Evaluation System
XPC Evaluation board for XPC56xx devices. Allow to
evaluate and develop the whole range of XPC devices.
• Full modular design: motherboard, mini-

module for each device, standardized
connectors
• Standard communication
transceivers and connectors
• User’s buttons, jumpers and LED’s
• Device mini-module connector
EB tresos Studio
EB tresos Studio is a easy-to-use tool for

ECU standard software configuration,
validation and code generation
Full support for the AUTOSAR standard

Full support for the Freescale AUTOSAR software
and the EB tresos AutoCore
Will be used by Freescale for both OS and Mcal
configuration, started in August 2008
Integrated, graphical user interface
Based upon Eclipse and open standards
Online-help and parameter-specific help
Source: Elektrobit
Development Tools – An Existing Ecosystem
Initialization Modeling and

Compilers Debuggers Simulators Eval Boards Tools Code
works w/ any
CodeWarrior (v2.2) debugger

Green Hills
Wind River
GNU
Lauterbach

iSystem
P&E Micro
RAppID Init
dSpace
MathWorks
TM

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MPC56xx-

Power Architecture MCU for Automotive

“Monaco” “Pictus” “Bolero” “Spectrum”

CROSSBAR SWITCH CROSSBAR SWITCH CROSSBAR SWITCH

2.5K Code 10 bit 1or2 1 3 eMIOSLite

Junction Temperature Sensor

JTAG / Nexus Class 2+

►Family Overview VReg MCM JTAG

Family Differences Note: block diagram represents the MPC5606B

Device Flash SRAM SCI (LINFlex) CAN (FlexCAN) Pins

MPC560xS System Crossbar Debug

►Auto and Industrial Target Applications

Power ISA : Power Architecture :

Instruction Set Architecture targeted for Power,

e200, e300(667MHz), e500 (1 GHz), e600 (2GHz), e700 family:

e200 variants in IDC:

Freescale MSG SoC :

1970’s 1980’s 1991 1993 1996 1999 2002 2005 2007

e200z3 4-stage pipeline

2004 2005 2006 2007

OnCE / Nexus CPU Control SIMD & EFP

Unit Instruction Unit Multiply Unit

Instruction Cache Instruction Buffer

PC Branch SPR Data

Load / Store Unit

Data Bus Interface Unit

► 32 General Purpose Registers (GPRs)

► Special Purpose Registers (SPRs)

► Architectural Extensions via Auxilary Processing Units (APU):

► Cache and MMU

Pipeline Size 10 Stage 7 Stage 5 Stage 4 Stage 4 Stage 4 Stage

MMU 64 Entry 32 Entry 16 Entry 16 Entry 16 Entry -

CR ► Condition Register consists of eight 4-bit fields, CR0–CR7, that

CTR ► CounT Register holds a loop count that can be decremented

e200zX Specific Registers

e200zX Specific Registers

e200zX Specific Registers

& 16 EE External interrupt Enable 0 (Disabled)

& 26 IS Instruction address Space (not implemented on z0) 0 (Disabled)

Z 27 DS Data address Space (not implemented on z0) 0 (Disabled)

e200zX Specific Registers

► This ABI defines certain registers to have dedicated uses:

► If registers need to be saved across a function call:

r1 stack frame dedicated cr0-cr1 condition reg. fields volatile

r2 small data area 2 dedicated cr2-cr4 condition reg. fields non-

r3-r4 parameters/return volatile cr5-cr7 condition reg. fields volatile

r5-r10 parameters volatile lr link register volatile

r11-r12 function linkage volatile ctr count register volatile

r13 small data area dedicated xer integer exception volatile

r14-r30 local variables non- spefscr** SPE float limited-

►Cost is a key factor in embedded applications

► VLE Instructions have exact or similar semantics to BookE

► Some 32-bit BookE instructions do not need full 32-bit instruction

► 16-bit Power™ VLE instructions encoded with “se_” prefix

► 32-bit Power™ VLE instructions encoded with “e_” prefix

stw // BookE 32-bit instruction (not used on e200z0)

► Equivalents for (nearly) all 32-bit BookE instructions

► 32-bit VLE instruction

‘se_li’ instruction ‘se_sub’ instruction

► ~70 16 bit instructions

► VLE 16-bit encodings have same constraints as other 16-bit ISAs.

► ‘Branch’ VLE Encoding Example

• se_b 0x8 - PowerPC VLE 16-bit Encoding