P SURYA 02/02/2018

PH2015020

COMMENTS ON THE ADC SPECS

YEAR
(CITATIONS)
TITLE AUTHORS STAGE
ENOB N SNR SNDR NODE POWER AREA FREQ
N

Digital Self-Correction of Time-Interleaved ADCs(IISCC):

DIGITAL POST-CORRECTION ALGORITHM & INTER-CHANNEL MISMATCH CORRECTION
1. Compensating the mismatch between the individual channels of the converter of an
interleaved architecture.
2. An existing algorithm for single-channel pipelined converters is extended to include inter-
1.5bits 41.3
channel correction as well, requiring almost no additional hardware. Instead of traditionally P. Harpe; A.
per 6.6 dB
2005/1 solving the problem by using devices od larger sizes to have lower mismatches Zanikopoulos; A. van
stage* 11.6 71.6
3. The error sources are taken into account are: random deviations of the comparator levels in Roermund
18 dB
the sub-ADCs, random deviations of the sub-DAC levels, random offset, gain-error and third-
order distortion of the SHA.
4. It seems a logical step to use post-corrected pipelined converters in a time-interleaved
structure. However, the simulation results in the next paragraph show that the performance
of such a converter is poor due to the inter-channel mismatch of the converters.
High-level Accurate Model of High-resolution Pipelined ADC's: (#MATLAB)
1. Accurate model for the systematic design and the simulation of high-resolution pipelined ADCs
The design is based on the non-linearities affecting the ADC whereas the goal is the evaluation
of the best architecture matching the specifications (DNL and INL).
2. Bit partitioning along pipeline chain, amplifiers specifications (designed down to transistor-
level in both CMOS and BiCMOS technologies), capacitors size, power consumption and
calibration requirements are delivered.
3. A correct bit partitioning and an optimized OTA architecture will allow the specifications latch,
considering the power consumption and the calibration requirements as well
4. The MATLAB-based tool here presented is suitable for switched-capacitor pipelined ADCs and,
starting from a high-level modelling, allows complete non-linearity analysis, code density
graphs and spectral analysis.
5. TABLE I : REQUIRED INPUT DATA FOR THE DESIGN SECTION OF THE CAD TOOL.
---------------------------------------------------------------------------------------------------------------------------- C. Azzolini; D.
2006 6. High-level data: resolution, sampling frequency, power supply, input range, INL/DNL, noise Vecchi; A. Boni; G.
level min and max capacitance, temperature, noise and non-lin. distribution, etc. Chiorboli
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7. Technology data: capacitors mismatch coefficient, threshold voltages, channel length modul.
coeff., gate oxide capacitance, gain factor, etc.
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8. Amplifier data: architecture, min and max device size, common modes,device voltage beyond
saturation, etc.
Solution allows to reduce the design effort for the though challenging front-end stages
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9. MDAC data: capacitors value, amplifier minimum DC-gain, bandwidth, transconductance and
capacitive load, MDAC input capacitance, calibration requirements, etc.
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10. Operational amplifiers data:device size (MOSFET’s W and L, bipolar emitter area),
compensation network, biasing currents and voltages, power consumption
 COMMENTS ON THE ADC SPECS
YEAR
(CITATIONS)
TITLE AUTHORS STAGE
ENOB N SNR SNDR NODE POWER AREA FREQ
N

Seung-Hoon Lee and

1992 Digital-Domain Calibration of Multistep Analog-to-Digital Converters
Bang-Sup Song,