Documente Academic
Documente Profesional
Documente Cultură
Requirements VDDCORE/VCAP
The Flash program memory on PIC24FJXXXGA1/GB1 VSS
devices has a specific write/erase requirement that
must be adhered to for proper device operation. The
rule is that any given word in memory must not be writ-
ten more than twice before erasing the page in which it Regulator Disabled (VDD tied to VDDCORE):
is located. Thus, the easiest way to conform to this rule
2.5V(1)
is to write all the data in a programming block within
one write cycle. The programming methods specified in PIC24FJXXXGA1/GB1
this specification comply with this requirement. VDD
ENVREG
Note: Writing to a location multiple times without
erasing is not recommended. VDDCORE/VCAP
VSS
2.3 Pin Diagrams
The pin diagrams for the PIC24FJXXXGA1/GB1 fami-
Note 1: These are typical operating voltages. Refer
lies are shown in the following figures. The pins that are to Section 7.0 “AC/DC Characteristics and
required for programming are listed in Table 2-1 and Timing Requirements” for the full operating
are shown in bold letters in the figures. Refer to the ranges of VDD and VDDCORE.
appropriate device data sheet for complete pin
descriptions.
64-Pin TQFP
VCAP/VDDCORE
ENVREG
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RE4
RE3
RE2
RE1
RE0
RF1
RF0
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
1 48 RC14
RE5
47 RC13
RE6 2
46 RD0
RE7 3
RG6 4 45 RD11
RG7 5 44 RD10
RG8 6 43 RD9
MCLR 7 42 RD8
RG9 8 PIC24FJXXXGA106 41 VSS
VSS 9 40 RC15
VDD 10 39 RC12
PGEC3/AN5/RP18/C1INA/CN7/RB5 11 38 VDD
PGED3/AN4/RP28/C1INB/CN6/RB4 12 37 RG2
RB3 13 36 RG3
RB2 14 35 RF6
PGEC1/AN1/RP1/VREF-/CN3/RB1 15 34 RF2
PGED1/AN0/RP0/PMA6/VREF+/CN2/RB0 16 33 RF3
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
AVDD
RB8
RB9
RB10
RB11
VDD
RB12
RB13
RB14
RB15
RF4
RF5
PGEC2/AN6/RP6/CN24/RB6
PGED2/AN7/RP7/CN25/RB7
VSS
AVSS
80-Pin TQFP
VCAP/VDDCORE
ENVREG
RD13
RD12
RG0
RG1
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RE4
RE3
RE2
RE1
RE0
RF1
RF0
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
RE5 1 60 RC14
59 RC13
RE6 2
58 RD0
RE7 3
4 57 RD11
RC1
5 56 RD10
RC3
6 55 RD9
RG6
7 54 RD8
RG7
8 53 RA15
RG8
9 52 RA14
MCLR
10 51 VSS
RG9 PIC24FJXXXGA108
11 50 RC15
VSS
12 49 RC12
VDD
48 VDD
CN66/RE8 13
47 RG2
CN67/RE9 14
46 RG3
PGEC3/AN5/RP18/C1INA/CN7/RB5 15
45 RF6
PGED3/AN4/RP28/C1INB/CN6/RB4 16
44 RF7
RB3 17
43 RF8
RB2 18
42 RF2
PGEC1/AN1/RP1/CN3/RB1 19
41 RF3
PGED1/AN0/RP0/CN2/RB0 20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
RD15
PGEC2/AN6/RP6/CN24/RB6
PGED2/AN7/RP7/CN25/RB7
RA9
RA10
AVDD
RB8
RB9
RB10
RB11
VDD
RB12
RB13
RB14
RB15
RD14
RF4
RF5
VSS
AVSS
100-Pin TQFP
VCAP/VDDCORE
ENVREG
RG13
RG12
RG14
RD13
RD12
RG0
RG1
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RE4
RE3
RE2
RE1
RE0
RA7
RA6
RF1
RF0
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
RG15 1 75 VSS
VDD 2 74 RC14
RE5 3 73 RC13
RE6 4 72 RD0
RE7 5 71 RD11
RC1 6 70 RD10
RC2 7 69 RD9
RC3 8 68 RD8
RC4 9 67 RA15
RG6 10 66 RA14
RG7 11 65 VSS
RG8 12 PIC24FJXXXGA110 64 RC15
MCLR 13 63 RC12
RG9 14 62 VDD
VSS 15 61 RA5
VDD 16 60 RA4
RA0 17 59 RA3
RE8 18 58 RA2
RE9 19 57 RG2
PGEC3/AN5/RP18/VBUSON/C1INA/CN7/RB5 20 56 RG3
PGED3/AN4/RP28/USBOEN/C1INB/CN6/RB4 21 55 RF6
RB3 22 54 RF7
RB2 23 53 RF8
PGEC1/AN1/RP1/CN3/RB1 24 52 RF2
PGED1/AN0/RP0/CN2/RB0 25 51 RF3
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PGEC2/AN6/RP6/CN24/RB6
PGED2/AN7/RP7/RCV/CN25/RB7
RA9
RA10
RB8
RB9
RB10
RB11
RA1
RF13
RF12
RB12
RB13
RB14
RB15
VDD
RD14
RD15
RF4
RF5
AVSS
VSS
VSS
AVDD
VDD
64-Pin TQFP
VCAP/VDDCORE
ENVREG
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RE4
RE3
RE2
RE1
RE0
RF1
RF0
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
1 48 RC14
RE5
47 RC13
RE6 2
46 RD0
RE7 3
RG6 45 RD11
4
RG7 5 44 RD10
RG8 6 43 RD9
MCLR 7 42 RD8
RG9 8 PIC24FJXXXGB106 41 VSS
VSS 9 40 RC15
VDD 10 39 RC12
PGEC3/AN5/RP18/VBUSON/C1INA/CN7/RB5 11 38 VDD
PGED3/AN4/RP28/USBOEN/C1INB/CN6/RB4 12 37 D+/RG2
RB3 13 36 D-/RG3
RB2 14 35 VUSB
PGEC1/AN1/RP1/VREF-/CN3/RB1 15 34 VBUS
PGED1/AN0/RP0/PMA6/VREF+/CN2/RB0 16 33 RF3
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PGED2/AN7/RP7/RCV/CN25/RB7
RB8
RB9
RB10
RB11
RB12
RB13
RB14
RB15
RF4
RF5
PGEC2/AN6/RP6/CN24/RB6
VSS
AVDD
VDD
AVSS
80-Pin TQFP
VCAP/VDDCORE
ENVREG
RD13
RD12
RG0
RG1
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RE4
RE3
RE2
RE1
RE0
RF1
RF0
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
RE5 1 60 RC14
59 RC13
RE6 2
58 RD0
RE7 3
4 57 RD11
RC1
5 56 RD10
RC3
6 55 RD9
RG6
7 54 RD8
RG7
8 53 RA15
RG8
9 52 RA14
MCLR
10 51 VSS
RG9 PIC24FJXXXGB108
11 50 RC15
VSS
12 49 RC12
VDD
48 VDD
CN66/RE8 13
47 D+/RG2
CN67/RE9 14
46 D-/RG3
PGEC3/AN5/RP18/VBUSON/C1INA/CN7/RB5 15
45 VUSB
PGED3/AN4/RP28/USBOEN/C1INB/CN6/RB4 16
44 VBUS
RB3 17
43 RF8
RB2 18
42 RF2
PGEC1/AN1/RP1/CN3/RB1 19
41 RF3
PGED1/AN0/RP0/CN2/RB0 20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
RD15
PGEC2/AN6/RP6/CN24/RB6
PGED2/AN7/RP7/RCV/CN25/RB7
RA9
RA10
AVDD
RB8
RB9
RB10
RB11
VDD
RB12
RB13
RB14
RB15
RD14
RF4
RF5
VSS
AVSS
100-Pin TQFP
VCAP/VDDCORE
ENVREG
RG13
RG12
RG14
RD13
RD12
RG0
RG1
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RE4
RE3
RE2
RE1
RE0
RA7
RA6
RF1
RF0
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
RG15 1 75 VSS
VDD 2 74 RC14
RE5 3 73 RC13
RE6 4 72 RD0
RE7 5 71 RD11
RC1 6 70 RD10
RC2 7 69 RD9
RC3 8 68 RD8
RC4 9 67 RA15
RG6 10 66 RA14
RG7 11 65 VSS
RG8 12 PIC24FJXXXGB110 64 RC15
MCLR 13 63 RC12
RG9 14 62 VDD
VSS 15 61 RA5
VDD 16 60 RA4
RA0 17 59 RA3
RE8 18 58 RA2
RE9 19 57 D+/RG2
PGEC3/AN5/RP18/VBUSON/C1INA/CN7/RB5 20 56 D-/RG3
PGED3/AN4/RP28/USBOEN/C1INB/CN6/RB4 21 55 VUSB
RB3 22 54 VBUS
RB2 23 53 RF8
PGEC1/AN1/RP1/CN3/RB1 24 52 RF2
PGED1/AN0/RP0/CN2/RB0 25 51 RF3
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VDD
PGEC2/AN6/RP6/CN24/RB6
PGED2/AN7/RP7/RCV/CN25/RB7
RA9
RA10
AVDD
RB8
RB9
RB10
RB11
VDD
RA1
RF13
RF12
RB12
RB13
RB14
RB15
RD14
RD15
RF4
RF5
AVSS
VSS
VSS
TABLE 2-2: CODE MEMORY SIZE AND FLASH CONFIGURATION WORD LOCATIONS FOR
PIC24FJXXXGA1/GB1 DEVICES
User Memory Configuration Word Addresses
Write Erase
Device Address Limit
Blocks Blocks 1 2 3
(Instruction Words)
PIC24FJ64GB1XX 00ABFEh (22K) 344 43 00ABFEh 00ABFCh 00ABFAh
PIC24FJ128GA1XX
0157FEh (44K) 688 86 0157FEh 0157FCh 0157FAh
PIC24FJ128GB1XX
PIC24FJ192GA1XX
020BFEh (67K) 1048 131 020BFEh 020BFCh 020BFA
PIC24FJ192GB1XX
PIC24FJ256GA1XX
02ABFEh (87K) 1368 171 02ABFEh 02ABFCh 02ABFA
PIC24FJ256GB1XX
000000h
User Flash
Code Memory(1)
0XXXF9h(1)
0XXXFAh(1)
Flash Configuration Words
0XXXFEh(1)
0XXX00h(1)
User Memory
Space
Reserved
7FFFFEh
800000h
Executive Code Memory
(1024 x 24-bit)
8007FAh
Diagnostic and Calibration 8007F0h
Words
(8 x 24-bit)
800800h
Configuration Memory
Space
Reserved
FEFFFEh
Device ID FF0000h
(2 x 16-bit) FF0002h
FF0004h
Reserved
FFFFFEh
Note 1: The size and address boundaries for user Flash code memory are device dependent. See Table 2-2 for details.
P1
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 1 2 3 4
PGCx
P4 P4A
P3 P1A
P1B
P2
LSB X X X X X X X X X X X X X X MSB
PGDx 0 0 0 0 0 0 0 0 0 0 0 0 0
3.2.1.1 Differences Between Execution of During normal operation, the CPU automatically
SIX and Normal Instructions will force a NOP while the new data is read. When
using ICSP, there is no automatic stall, so any
There are some differences between executing instruc-
indirect references to a recently modified
tions normally and using the SIX ICSP command. As a
register should be preceded by a NOP.
result, the code examples in this specification may not
match those for performing the same functions during For example, the instructions, MOV #0x0,W0 and
normal device operation. MOV [W0],W1, must have a NOP inserted
between them.
The important differences are:
If a two-cycle instruction modifies a register that is
• Two-word instructions require two SIX operations
used indirectly, it will require two following NOPs: one
to clock in all the necessary data.
to execute the second half of the instruction and a
Examples of two-word instructions are GOTO and second to stall the CPU to correct the pipeline.
CALL.
Instructions such as TBLWTL [W0++],[W1]
• Two-cycle instructions require two SIX operations. should be followed by two NOPs.
The first SIX operation shifts in the instruction and • The device Program Counter (PC) continues to
begins to execute it. A second SIX operation – which automatically increment during ICSP instruction
should shift in a NOP to avoid losing data – provides execution, even though the Flash memory is not
the CPU clocks required to finish executing the being used.
instruction.
As a result, the PC may be incremented to point to
Examples of two-cycle instructions are table read invalid memory locations. Invalid memory spaces
and table write instructions. include unimplemented Flash addresses and the
• The CPU does not automatically stall to account vector space (locations 0x0 to 0x1FF).
for pipeline changes. If the PC points to these locations, the device will
A CPU stall occurs when an instruction modifies a reset, possibly interrupting the ICSP operation. To
register that is used for Indirect Addressing by the prevent this, instructions should be periodically
following instruction. executed to reset the PC to a safe space. The opti-
mal method to accomplish this is to perform a
GOTO 0x200.
Execute Previous Instruction, CPU Held in Idle Shift Out VISI Register<15:0> No Execution Takes Place,
Fetch REGOUT Control Code Fetch Next Control Code
P6
P14 P19 P7
VIH VIH
MCLR
VDD
Program/Verify Entry Code = 4D434851h
PGDx 0 1 0 0 1 ... 0 0 0 1
b31 b30 b29 b28 b27 b3 b2 b1 b0
PGCx
P18 P1A
P1B
Start
N=1
LoopCount = 0
Configure
Device for
Writes
Load 2 Bytes
N=N+1 to Write
Buffer at <Addr>
All
No bytes
written?
N=1 Yes
LoopCount = Start Write Sequence
LoopCount + 1 and Poll for WR bit
to be Cleared
No All
locations
done?
Yes
Done
TABLE 3-10: SERIAL INSTRUCTION EXECUTION FOR READING ALL CONFIGURATION MEMORY
Command Data
Description
(Binary) (Hex)
Step 1: Exit Reset vector.
0000 000000 NOP
0000 040200 GOTO 0x200
0000 000000 NOP
Step 2: Initialize TBLPAG, the Read Pointer (W6) and the Write Pointer (W7) for TBLRD instruction.
0000 200xx0 MOV <CW3Address23:16>, W0
0000 880190 MOV W0, TBLPAG
0000 2xxxx7 MOV <CW3Address15:0>, W6
0000 207847 MOV #VISI, W7
0000 000000 NOP
Step 3: Read the Configuration register and write it to the VISI register (located at 784h), and clock out the
VISI register using the REGOUT command.
0000 BA0BB6 TBLRDL [W6++], [W7]
0000 000000 NOP
0000 000000 NOP
0001 <VISI> Clock out contents of VISI register
0000 000000 NOP
Step 4: Repeat Step 3 twice to read Configuration Word 2 and Configuration Word 1.
Step 5: Reset device internal PC.
0000 040200 GOTO 0x200
0000 000000 NOP
All
No code memory
verified?
Yes
Done
P6
P19 P7
P14
VIH VIH
MCLR
VDD
Program/Verify Entry Code = 4D434850h
PGDx 0 1 0 0 1 ... 0 0 0 0
b31 b30 b29 b28 b27 b3 b2 b1 b0
PGCx
P18 P1A
P1B
Start
ConfigAddress = 0XXXFAh(1)
Send PROGP
Command
Is No
PROGP response
PASS?
Yes
Is
ConfigAddress = No
ConfigAddress
ConfigAddress + 2
0XXXFEh?(1)
Yes
Finish Failure
Report Error
1 2 15 16 1 2 15 16 1 2 15 16
PGCx
P8 P9 P20 P21
Opcode 4h D_96
Length 4h
Reserved 0h Field Description
Addr_MSB MSB of 24-bit destination address Opcode 5h
Addr_LS Least Significant 16 bits of 24-bit Length 63h
destination address Reserved 0h
Data 8-bit data word Addr_MSB MSB of 24-bit destination address
The PROGC command instructs the programming Addr_LS Least Significant 16 bits of 24-bit
executive to program a single Device ID register destination address
located at the specified memory address.
D_1 16-bit data word 1
After the specified data word has been programmed to D_2 16-bit data word 2
code memory, the programming executive verifies the
programmed data against the data in the command. ... 16-bit data word 3 through 95
D_96 16-bit data word 96
Expected Response (2 words):
The PROGP command instructs the programming
1400h
executive to program one row of code memory, includ-
0002h ing Configuration Words (64 instruction words), to the
specified memory address. Programming begins with
the row address specified in the command. The
destination address should be a multiple of 80h.
The data to program to memory, located in command
words, D_1 through D_96, must be arranged using the
packed instruction word format shown in Figure 5-5.
After all data has been programmed to code memory,
the programming executive verifies the programmed
data against the data in the command.
Expected Response (2 words):
1500h
0002h
Note: Refer to Table 2-2 for code memory size
information.
Field Description
15 12 11 8 7 0
Opcode Bh
Opcode Last_Cmd QE_Code
Length 1h
The QVER command queries the version of the Length
programming executive software stored in test
memory. The “version.revision” information is returned D_1 (if applicable)
in the response’s QE_Code using a single byte with the ...
following format: main version in upper nibble and
revision in the lower nibble (i.e., 23h means version 2.3 D_N (if applicable)
of programming executive software).
Expected Response (2 words):
Field Description
1BMNh (where “MN” stands for version M.N)
0002h Opcode Response opcode
Last_Cmd Programmer command that
5.3 Programming Executive generated the response
Responses QE_Code Query code or error code.
Length Response length in 16-bit words
The programming executive sends a response to the
(includes 2 header words)
programmer for each command that it receives. The
response indicates if the command was processed D_1 First 16-bit data word (if applicable)
correctly. It includes any required response data or D_N Last 16-bit data word (if applicable)
error data.
The programming executive response set is shown in 5.3.1.1 Opcode Field
Table 5-2. This table contains the opcode, mnemonic The opcode is a 4-bit field in the first word of the
and description for each response. The response format response. The opcode indicates how the command
is described in Section 5.3.1 “Response Format”. was processed (see Table 5-2). If the command was
processed successfully, the response opcode is PASS.
TABLE 5-2: PROGRAMMING EXECUTIVE If there was an error in processing the command, the
RESPONSE OP CODES response opcode is FAIL and the QE_Code indicates
the reason for the failure. If the command sent to
Opcode Mnemonic Description the programming executive is not identified, the
1h PASS Command successfully programming executive returns a NACK response.
processed
5.3.1.2 Last_Cmd Field
2h FAIL Command unsuccessfully
processed The Last_Cmd is a 4-bit field in the first word of
the response and indicates the command that the
3h NACK Command not known
programming executive processed. Since the program-
ming executive can only process one command at a
time, this field is technically not required. However, it
can be used to verify that the programming executive
correctly received the command that the programmer
transmitted.
Step 6: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware.
0000 040200 GOTO 0x200
0000 000000 NOP
0000 803B02 MOV NVMCON, W2
0000 883C22 MOV W2, VISI
0001 000000 NOP
<VISI> Clock out contents of the VISI register.
0000 000000 NOP
Param
Symbol Characteristic Min Max Units Conditions
No.
D111 VDD Supply Voltage During Programming VDDCORE 3.60 V Normal programming(1,2)
D112 IPP Programming Current on MCLR — 5 μA
D113 IDDP Supply Current During Programming — 2 mA
D031 VIL Input Low Voltage VSS 0.2 VDD V
D041 VIH Input High Voltage 0.8 VDD VDD V
D080 VOL Output Low Voltage — 0.4 V IOL = 8.5 mA @ 3.6V
D090 VOH Output High Voltage 3.0 — V IOH = -3.0 mA @ 3.6V
D012 CIO Capacitive Loading on I/O pin (PGDx) — 50 pF To meet AC specifications
D013 CF Filter Capacitor Value on VCAP 4.7 10 μF Required for controller core
P1 TPGC Serial Clock (PGCx) Period 100 — ns
P1A TPGCL Serial Clock (PGCx) Low Time 40 — ns
P1B TPGCH Serial Clock (PGCx) High Time 40 — ns
P2 TSET1 Input Data Setup Time to Serial Clock ↑ 15 — ns
P3 THLD1 Input Data Hold Time from PGCx ↑ 15 — ns
P4 TDLY1 Delay Between 4-Bit Command and 40 — ns
Command Operand
P4A TDLY1A Delay Between 4-Bit Command Operand 40 — ns
and Next 4-Bit Command
P5 TDLY2 Delay Between Last PGCx ↓ of Command 20 — ns
Byte to First PGCx ↑ of Read of Data Word
P6 TSET2 VDD ↑ Setup Time to MCLR ↑ 100 — ns
P7 THLD2 Input Data Hold Time from MCLR ↑ 25 — ms
P8 TDLY3 Delay Between Last PGCx ↓ of Command 12 — μs
Byte to PGDx ↑ by Programming Executive
P9 TDLY4 Programming Executive Command 40 — μs
Processing Time
P10 TDLY6 PGCx Low Time After Programming 400 — ns
P11 TDLY7 Chip Erase Time 400 — ms
P12 TDLY8 Page Erase Time 40 — ms
P13 TDLY9 Row Programming Time 2 — ms
P14 TR MCLR Rise Time to Enter ICSP™ mode — 1.0 μs
P15 TVALID Data Out Valid from PGCx ↑ 10 — ns
P16 TDLY10 Delay Between Last PGCx ↓ and MCLR ↓ 0 — s
P17 THLD3 MCLR ↓ to VDD ↓ — 100 ns
P18 TKEY1 Delay from First MCLR ↓ to First PGCx ↑ for 40 — ns
Key Sequence on PGDx
P19 TKEY2 Delay from Last PGCx ↓ for Key Sequence 1 — ms
on PGDx to Second MCLR ↑
P20 TDLY11 Delay Between PGDx ↓ by Programming 23 — µs
Executive to PGDx Driven by Host
P21 TDLY12 Delay Between Programming Executive 8 — ns
Command Response Words
Note 1: VDDCORE must be supplied to the VDDCORE/VCAP pin if the on-chip voltage regulator is disabled. See
Section 2.1 “Power Requirements” for more information. (Minimum VDDCORE allowing Flash programming is
2.25V.)
2: VDD must also be supplied to the AVDD pins during programming. AVDD and AVSS should always be within ±0.3V
of VDD and VSS, respectively.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
10/05/07