Documente Academic
Documente Profesional
Documente Cultură
float u[1000];
float ch1[334];
Uint16 EPwm_CMPA_Direction;
Uint16 EPwm_CMPB_Direction;
Uint16 EPwmTimerIntCount;
Uint16 EPwmMaxCMPA;
Uint16 EPwmMinCMPA;
Uint16 EPwmMaxCMPB;
Uint16 EPwmMinCMPB;
void main(void)
{
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the F2806x_SysCtrl.c file.
InitSysCtrl();
EALLOW;
GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 0; // GPIO18 = GPIO18
GpioCtrlRegs.GPADIR.bit.GPIO18 = 1; // GPIO18 = output ->1
GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 0; // 0=GPIO,
GpioCtrlRegs.GPADIR.bit.GPIO16 = 1; // 1=OUTput, 0=INput
GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 0; // 0=GPIO,
GpioCtrlRegs.GPADIR.bit.GPIO19 = 1; // 1=OUTput, 0=INput
GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 0;
GpioCtrlRegs.GPBDIR.bit.GPIO34 = 1;
GpioCtrlRegs.GPADIR.bit.GPIO0 = 1;
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // GPIO1 = epwm
GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1; // GPIO1 = epwm
GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1; // GPIO1 = epwm
GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1; // GPIO1 = epwm
GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1; // GPIO1 = epwm
GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1; // GPIO1 = epwm
EDIS;
EALLOW;
SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1; // Enable ADC peripheral clock
(*Device_cal)(); // Auto-calibrate from TI OTP
SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 0; // Return ADC clock to original state
EDIS;
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example. This is useful for debug purposes.
// The shell ISR routines are found in F2806x_DefaultIsr.c.
// This function is found in F2806x_PieVect.c.
InitPieVectTable();
//Configure ADC
EALLOW;
SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1; // ADC
AdcRegs.ADCCTL1.bit.ADCREFSEL = 0; // Use internal bandgap
AdcRegs.ADCCTL1.bit.ADCBGPWD = 1; // Power up band gap
AdcRegs.ADCCTL1.bit.ADCREFPWD = 1; // Power up reference
AdcRegs.ADCCTL1.bit.ADCPWDN = 1; // Power up rest of ADC
AdcRegs.ADCCTL1.bit.ADCENABLE = 1; // Enable ADC
// for(i=0; i<5000; i++){} // wait 60000 cycles = 1ms
(each iteration is 12 cycles)
//Note that SOC3, 7, 11, 13 & 15 are valid, but these SOCs are not configured
//since these ADC outputs do not exist on the controlSTICK. The configuration
//is configured as it is for readability.
EDIS;
InitEPwm1Example();
InitEPwm2Example();
InitEPwm3Example();
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;
if(t>=100)
t=0;
t = t + 60e-6;
EPwm1Regs.CMPA.half.CMPA = 1000 ;
EPwm1Regs.CMPB = 1000 ;
if(j>334)
j=0;
ch1[j]=V;
j=j+1;
GpioDataRegs.GPADAT.bit.GPIO18 = 0;
{
GpioDataRegs.GPBTOGGLE.bit.GPIO34 = 1; // Toggle GPIO34 once per
cycle
}
EDIS;
// The CPU acknowledges the interrupt.
void InitEPwm1Example()
{
// Setup TBCLK
EPwm1Regs.TBPRD = EPWM1_TIMER_TBPRD; // Set timer period 801 TBCLKs
EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
// Setup shadowing
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Set actions
EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on event A, up count
EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR; // Clear PWM1A on event A, down
count
void InitEPwm2Example()
{
// Setup TBCLK
EPwm2Regs.TBPRD = EPWM2_TIMER_TBPRD; // Set timer period 801 TBCLKs
EPwm2Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm2Regs.TBCTR = 0x0000; // Clear counter
// Set Compare values
EPwm2Regs.CMPA.half.CMPA = EPWM2_MIN_CMPA; // Set compare A value
EPwm2Regs.CMPB = EPWM2_MIN_CMPB; // Set Compare B value
// Setup shadowing
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Set actions
EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on event A, up count
EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR; // Clear PWM1A on event A, down
count
void InitEPwm3Example(void)
{
// Setup TBCLK
EPwm3Regs.TBPRD = EPWM3_TIMER_TBPRD; // Set timer period 801 TBCLKs
EPwm3Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm3Regs.TBCTR = 0x0000; // Clear counter
// Set actions
EPwm3Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on event A, up count
EPwm3Regs.AQCTLA.bit.CAD = AQ_CLEAR; // Clear PWM1A on event A, down
count