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Unateness of Complex Circuit: Timing Arc

STA & SI:: Chapter 1: Introduction

1.1a 1.1b 1.1c 1.2a 1.2b
INTRODUC Timing Unate: Unateness of Complex Circuit: LIB File syntax for Logic Gates: LIB File syntax for Complex Circuit:
TION Arc Timing Arc Timing Arc Timing Sense Timing Sense

Unateness of Complex Circuit: Timing Arc:

Vlsi expert
In last article (Unate: Timing Arc), we have discussed about the unateness property of Timing arc with respect to Logic gates. In the Timing
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Library, "Timing Arc information" is stored with the syntax "timing_sense".

In this article, we are trying to extend timing arc concepts from simple "Logic gate" to complex combinational circuit. For that first we need to Be the first of your friends to like th
understand how we can calculate or figure out the overall unateness of a complex circuit or say a system. To understand this, We start with few
standard logic functions like AOI (AND-OR-Inverter) which is not that complex but help us to understand the concept of unateness in system.

To understand the Timing Arc concept for combinational circuit, we should know how Timing Arc of a system calculated. Let's take an example to
understand this.

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In the above circuit, you can see that there are 2 type of Timing Arc (Net Timing Arc and Cell Timing Arc). SA
"Timing Paths" : Static mi
Net Timing Arc is always Positive Unate. Timing Analysis (STA) ap
Cell Timing Arc, we have already discussed in previous Article. (Unateness of Logic Gates ) basic (Part 1) Re
fixe
NAND Gate - Negative Unateness Basic of Timing be
NOT Gate - Negative Unateness Analysis in Physical sig
Design
 NOR Gate - Negative Unateness
"Setup and Hold Time"
: Static Timing Analysis
Note: To know more about the Unateness of Inverter, please read Article (STA) basic (Part 3a)
"Unateness- Timing Arc: Inverter" "Examples Of Setup
"Unateness- Timing Arc: NOR gate" and Hold time" : Static
Timing Analysis (STA)
"Unateness- Timing Arc: NAND gate" basic (Part 3c)

"Setup and Hold Time

So, If I want to understand the behaviors of signal at Y with respect to A (remember only A, Not with respect to other pins like B & C),
Violation" : Static
then we can conclude as Timing Analysis (STA)
basic (Part 3b)
Rising Input at A - Falling Output at Y or No Change.
Falling Input at A - Rising Output at Y or No Change. Delay - "Wire Load
Model" : Static Timing
Analysis (STA) basic
(Part 4c)
If you want to cross check this, there are several ways but I am going to explain (or say cover here) 3 ways.
Delay - "Interconnect
1. Truth table Method Delay Models" : Static
Timing Analysis (STA)
2. Circuit Method basic (Part 4b)
3. Function Method
"Time Borrowing" :
Static Timing Analysis
(STA) basic (Part 2)
1) Truth Table Method
Below is the Truth table ("Table_1") of AND-OR-INVERTER circuit of "Figure_1". I have highlighted all cases when A changes from 0 to 1 10 Ways to fix SETUP
(keeping all other inputs constant at a time), you can see that output either "Not Changing" or changing from 1 to 0. You can try reverse case also and HOLD violation:
(A changes from 1 to 0). Static Timing Analysis
(STA) Basic (Part-8)

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Below table (Table_2) help you to understand the Unateness from a Overall system point of view. It's very simple. I have explained with respect to
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Now, if above table (Table_2) is clear - let's try to understand how this table help us in AOI case (AND-OR-INVERTER) (Figure_1). A visitor from College
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So now, if you will see across different Systems (from 1 to 5), you can see that overall unateness is Negative Unate. Followers

3) Function Method
How will you identify the unateness in case you dnt have circuit, you only have equation (Boolean Equation) of circuit or design? Again, If I will
ask you that draw a circuit or create a truth table, then I am sure, you will try to skip it. But there is a solution of that. :)

For that, below definitions can help you to determine unateness of any variable of Function.
f is “positive unate” function in a dependent variable "x" if x’ does not appear in the sum-of-products representation.
 f is “negative unate” in a dependent variable "x" if x does not appear in the sum-of-products representation. Followers (480) Next
f is “non unate” (sometime known as biunate in switching theory) in a dependent variable "x" if you can not write a sum-of-products
representation without appearing x and x' both together. Means both be the part of SOP.

For example 1: F(w, x, z)= wx + w’z’

In the above function, if you try to implement above definition, you can easily figure out that
Positive unate with respect to x
Negative Unate with respect to z Follow
Non-unate with respect to w

For example 2: F(w, x, z)= wx + w’z’

Now, question is what will be with respect to y.
If you will see the equation, it's very much clear that even if you give rising edge or falling edge at "y", output is not going to change. That's means
it's neither Negative unate nor Positive unate nor Non-Unate. I am sure, now you may be confuse that what's this? :) Right now, I am leaving this
as a open topic of discussion for later on. You can comment about these type of variables.

Now, if above function definition is clear - let's try to understand how these can be implemented in AOI case (AND-OR-INVERTER) (Figure_1).

Figure_1 can be written in the form of equations as: Y = ((A.B) + C)'

Let's open in simplified SOP form.

Y = ((A.B) + C)'
  = ((A.B)').(C)'
  = (A'+B').C'
  = A'C' + B'C'

Now, you can easily say -

Y is Negative unate with respect to A
Y is Negative Unate with respect to B
Y is Negative Unate with respect to C

In Summary: We can use any method as per our convenience to see the unateness of a system or circuit. Most of the time, this is already part of
Lib file, but to understand the tool behavior, we should have these understanding.

In next article, we will discuss Unateness of OAI (OR-AND-Inverter), MUX and few other complex circuit.

Posted by VLSI EXPERT at 9:30 AM

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