Lecture 5

Gain and Biasing Considerations

Finite Output Resistance

Jayant Charthad
Stanford University
jayantc@stanford

A. Arbabian, R. Dutton, B. Murmann EE114/214A L05-1

 Common Source Amplifier Revisited

• Interesting question
– How much voltage gain can we get from this circuit?

VDD

R
VO +vo
Av = − g m R
ID+i d

vi

VI

A. Arbabian, R. Dutton, B. Murmann EE114/214A L05-2

 Upper Bound on Gain (1)
• Plug in expression for gm
2I D
Av = − g m RL = − RL
VOV
• For operation in the saturation region, we definitely require
I D R < VDD
• Therefore, we have
2VDD
Av <
VOV
• This is an upper bound only, useful for back of the envelope
calculations (and job interviews)
– Important to note that this expression does not hold with
equality

A. Arbabian, R. Dutton, B. Murmann EE114/214A L05-3

 Upper Bound on Gain (2)

• The above derived upper bound comes from the fact that both
gain and bias point depend on R
– Want large R for large gain
– Want small R to prevent device from entering triode region
• The upper bound may not be a serious issue in some circuits
– Nonetheless it is interesting and insightful to think about
ways around the issue
• We’ll do this graphically using “load line” plots

A. Arbabian, R. Dutton, B. Murmann EE114/214A L05-4

 Construction of Load Line Plot

Ir

VDD
VDD − Vo
Ir =
R R
Ir
Vo Vo

Vi Id
Id
ID i d = g m vi

Vo

A. Arbabian, R. Dutton, B. Murmann EE114/214A L05-5

 Putting Things Together

Ir, Id

VDD/R

Operating point

i d = g m vi

vo

Vo
VDD

A. Arbabian, R. Dutton, B. Murmann EE114/214A L05-6

 Larger Resistance

Ir, Id

VDD/Rsmall

VDD/Rlarge

i d = g m vi

vo

Vo
VDD

A. Arbabian, R. Dutton, B. Murmann EE114/214A L05-7

 Discussion
• The issue with this configuration is that the load line is pinned to
the point (VDD, 0)
• Larger VDD allows use of larger R and therefore larger gain
– This is also evident from the equation on slide 3
• It is possible to overcome this limitation by adding additional
degrees of freedom; consider e.g. the following alternative load
network
VDD VB Ix
VB − Vo
Ix = + IB
R IB R
R
Ir IB
Vo Ix
Vo
Vo
VB
A. Arbabian, R. Dutton, B. Murmann EE114/214A L05-8
 Plot for IB = ID

Ix, Id

i d = g m vi

vo

Vo
VDD

• Can increase R (and gain) without changing operating point

A. Arbabian, R. Dutton, B. Murmann EE114/214A L05-9

 “Infinite” Gain?

• Tempting to think that we can now make R nearly “infinitely”

large and get close to “infinite” gain
• This is not possible in practice for two reasons
– Finite dId/dVds of the transistor
• More later
– Sensitivity to mismatch between ID and IB will render the
circuit impractical
• We’ll look at this problem first

A. Arbabian, R. Dutton, B. Murmann EE114/214A L05-10

 Large R, ±10% Variation in IB

Ix, Id

Vo
VDD

• Very large changes in operating point (VO)

A. Arbabian, R. Dutton, B. Murmann EE114/214A L05-11

 Solutions

• Limit R to values such that expected mismatch in bias currents

causes acceptable bias point variations; avoid “balancing
marbles on the tip of a cone”
– More on mismatch later in this course
• Feedback
– Somehow sense VO and adjust IB (or ID) such that output sits
at a proper operating point, regardless of mismatch between
ID and IB
– More later in this course

A. Arbabian, R. Dutton, B. Murmann EE114/214A L05-12

 Intrinsic Gain
• Suppose we manage to bias the circuit such that ID=IB precisely
(e.g. using feedback) and let R®¥

IB
Vo

Vi Recall Lecture 4
about Spice:
(and linearization)

• In this case, it turns out that the voltage gain of the circuit is still
finite, and equal to the so-called “intrinsic gain” of the transistor
• Finite intrinsic gain is caused by the dependence of Id on Vds
– Transistor in saturation is a very good current source, but not
an ideal one…
A. Arbabian, R. Dutton, B. Murmann EE114/214A L05-13
 Finite dId/dVds

Id

i d = g m vi
IB

vo

Vo
(=Vds)

A. Arbabian, R. Dutton, B. Murmann EE114/214A L05-14

 Modeling Finite dId/dVds

• In a modern short-channel MOSFET several physical effects

cause finite dId/dVds
– Channel length modulation (CLM)
– DIBL, SCBE, …
– The precise dependencies are very hard to model
• Several pages of equations in a modern model such as BSIM4
and PSP
• In EE114/214A, we consider only channel length modulation
through a first order treatment
• This will help us construct a manageable model that contains
the relevant feature (namely, finite dId/dVds) without going
overboard with device physics

A. Arbabian, R. Dutton, B. Murmann EE114/214A L05-15

 Channel Length Modulation (1)
– VGS +
+ VD S –

N N
Qn(y), V(y)

y
DL(VDS)

y=0 y=L

• Increasing VDS causes the depletion region around the drain to

widen (basic PN junction physics)
• This pushes the pinch-off point further away from the drain,
resulting in an effective shortening of the channel
– Modeled as DL(VDS)

A. Arbabian, R. Dutton, B. Murmann EE114/214A L05-16

 Channel Length Modulation (2)

1 W
I D ≅ µCox (VGS − Vt )2
2 L − ΔL( VDS )

1 W
≅ µCox (VGS − Vt )2
2 ) ΔL( VDS )&
L '1 − $%
( L

1 W 2) ΔL( VDS ) &

≅ µCox (VGS − Vt ) '1 + $
2 L ( L %
1 W 2
≅ µCox (VGS − Vt ) [1 + λVDS ]
2 L

A. Arbabian, R. Dutton, B. Murmann EE114/214A L05-17

 Lamdba
• Single parameter that models finite dId/dVds assuming linear VDS
dependence
• Inversely proportional to channel length (see equation on
previous slide)
– Example technology: l(L) = 0.1V-1 × µm/L
• l = 0.10V-1 for L=1µm, l = 0.05V-1 for L=2µm, …
• VERY IMPORTANT
– l is a “fudge factor” that helps us take finite dId/dVds into
account to reason about the achievable small signal gain
– Never, ever, rely on a specific, precise value of lambda to
establish a circuit’s operating point
• Rule of thumb: if your circuit won’t work if l is varied it is plain
impractical

A. Arbabian, R. Dutton, B. Murmann EE114/214A L05-18

 Lamdba in HSpice (1)
• Unfortunately there is no Spice model that computes l as a
function of L automatically
– Must create separate models for each channel length
• The model file ee114_hspice.sp contains a number of models
that are automatically selected based on the chosen L value
– L=1µm (minimum), 1.2µm, 1.4µm, …
– EE114/214A process mask resolution = 0.2µm
.param vto=0.5 kp=50u lambda=0.1u *...
.param L1=1u L2=1.2u L3=1.4u *...

.model nmos114.1 nmos vto=vto kp=kp lambda=‘lambda/L1’ lmin=L1 lmax='L1+0.01u' *...

.model nmos114.2 nmos vto=vto kp=kp lambda=‘lambda/L2’ lmin=L2 lmax='L2+0.01u' *...
.model nmos114.3 nmos vto=vto kp=kp lambda=‘lambda/L3’ lmin=L3 lmax='L3+0.01u' *...
...

A. Arbabian, R. Dutton, B. Murmann EE114/214A L05-19

 Lamdba in HSpice (2)

*** example netlist

.include ee114_hspice.sp
*...
M1 d g s b nmos114 W=10u L=1.2um
HSpice will pick this model
*...
for simulating M1

.param vto=0.5 kp=50u lambda=0.1u *...

.param L1=1u L2=1.2u L3=1.4u *...
Ignore this part

.model nmos114.1 nmos vto=vto kp=kp lambda=‘lambda/L1’ lmin=L1 lmax='L1+0.01u' *...

.model nmos114.2 nmos vto=vto kp=kp lambda=‘lambda/L2’ lmin=L2 lmax='L2+0.01u' *...
.model nmos114.3 nmos vto=vto kp=kp lambda=‘lambda/L3’ lmin=L3 lmax='L3+0.01u' *...
...

A. Arbabian, R. Dutton, B. Murmann EE114/214A L05-20

 Small Signal Perspective

Id

gds

ID

Vo
(=Vds)

• Around the operating point, finite dId/dVds can be modeled as a

conductance gds (or resistance ro=1/gds)

A. Arbabian, R. Dutton, B. Murmann EE114/214A L05-21

 Small Signal Output Conductance

dI d d *1 W 2 '
g ds = = µC ( V − V ) ( 1 + λ V )
dVds () 2 %&
ox GS t ds
dVds Vds =VDS
L Vds =VDS

1 W
= µCox ( VGS − Vt )2 ⋅ λ
2 L
λI d λI D
= = Typical modeling challenge…sometimes
1 + λVds Vds =VDS
1 + λVDS zero-order approximations help a lot to
see the dominant factor…”scripting” in a
few weeks will let you keep the next-order
≅ λI D improvements (as needed)

• Approximation in last step is OK for quick calculations and large L

– This approximation overestimates gds
– Discrepancy factor in our technology bounded to 1+0.1×5 = 1.5

A. Arbabian, R. Dutton, B. Murmann EE114/214A L05-22

 MOSFET Model With Finite gds

G D
2I D W
+ gm = = 2 I D µCox
VOV L
vgs gmvgs r o=1/gds
- g ds ≅ λ ⋅ I D
S

A. Arbabian, R. Dutton, B. Murmann EE114/214A L05-23

 CS Amplifier Model With Finite gds
VB

IB R

+ +
Vo
vi gmvi ro R vo
Vi - -

1
Av = g m (R || ro ) = g m
1 1
+
R ro

gm g 2
Av R →∞
= g m ro = = " Intrinsic Gain" ≅ m =
g ds λI D λVOV

A. Arbabian, R. Dutton, B. Murmann EE114/214A L05-24

 A Note About “Early Voltage”
• “Early Voltage” (VA) is defined as 1/l (in Spice)
– Corresponds (roughly) to the extrapolated intercept of the
transistor's output characteristic with the Vds axis
• The intrinsic gain expression, in terms of Early Voltage has a
nice “feel” to it (V/V) given approximately by 2VA/VOV

ID

l2 < l1

|VA2| > |VA1| VDS

A. Arbabian, R. Dutton, B. Murmann EE114/214A L05-25

 Numbers
• For a minimum length device in the EE114/214A technology
(L=1µm)
– l=0.1V-1, VA=10V
– At VOV=150mV Þ gmro@2VA/VOV=133.33
• Suppose we want to build a common source stage with a
voltage gain of 5 (see example of Lecture 3)
– Does finite ro matter? No, we can see this without even
calculating ro by comparing the desired gain to typical
intrinsic gain values
1 1 1
Av = g m (R || ro ) ⇒ = +
Av g m R g m ro
Av
gm R = ≅ Av for g m ro >> Av
Av
1−
g m ro
A. Arbabian, R. Dutton, B. Murmann EE114/214A L05-26
 When do we care about gmro?

• Op-amp based feedback circuits

– Precision in feedback circuits relies on building very high
gain amplifiers
• Reference circuits
– E.g. current references or current mirrors
– Want to make current independent on voltage, which relies
on large ro

• More later…

A. Arbabian, R. Dutton, B. Murmann EE114/214A L05-27