qed 423 Name:, bi ‘Student 1D, 1. Design 4-bit decrement-by-2 it. Use contraction technique and start your design with a 4-bit binary ripple carry adder. S=A-2 is to be implemented. Do not draw the logic diagram of the circuit. (20pts) 5,=4.®B,8C, Cu =4,B FAC, +B,C, 7=0,1,2,3 Sa A-2 = A+ Tue's complement of 2 Reoolo 2-92 10 Xo=Ao, Y=Bo=0 Co=O S,= Av® 0 @0= Ao Q= 40.0 + Ao.0+ 6.0 =O Kaa Ma Biet $= A @1BO=A Og= Ard + ALO+ 4.0 = Ar Ke=Ar W2=Ba=4 3,2 A841 ©C2= Ar Cg = Asie Az CottCg= Arty %=Az Ys= Bat S52 Az O18 C3 = As OCs sominites Soluhons 28.12.2017 24I2. LOIF 2. Design a digital circuit that performs S=A+4B. Implement the circuit using only @ 4-bit binary adder. A and B are 4-bit numbers, ‘Multiply by 4: shift left by two positions with zero fil. (12pts) As AAs By B00 A®B Ltt] tit XXX Xe 3 2 Yo © 85 82 Sy So + [0,31 3. For the gated D latch, sketch the output Q. Assume that Q=0 initially, (2opts)4. Sketch the output Q of the positive-edge triggered D flip-flop. Q=0 initially. (20pts) b) State Table Present Taputs Next State | Output State D id ‘ LIX ( A x ~¥ Ae) Zo] \ \ oO [e) 3 ° oO SUL) BES 7 oO A ° 4 [e) \ 7 | T fa ! 7 | eo o 4 A 4 4 . 4 oO 3° 4 oO 4 oO 4 } Oo 5. A sequential circuit with two inputs X and Y, and one output Z is shown A 4 ° 4 } below. 7 a) Find the state equation and the output equation. (O4pts) 4 4 oO oO Drive the state table for the circuit. (16pts) ©) Draw the state diagram. (08pts) tel ala FG; fee POR Jo, 4 00/0, 10/o , oo/o, 40/0, AWA x] y b |, A(state variable) Y ~, 5 ql K [cox J L some oVo, M/o a) Altriy= X.A+VA x sa “7 CLK B= AY Tr Ke z output)