Documente Academic
Documente Profesional
Documente Cultură
CHAPTER 2: INTRODUCTION TO
THE FPGAs
Complex digital system design. EPS de Linares. Vicente Muñoz Diez. Office: D-115. Email: jmunoz@ujaen.es
Index
1. A brief review about digital logic gates
2. What is an FPGA?
3. Applications with FPGAs
4. FPGAs Vs. Processors
5. Pitfalls of FPGAs
6. Main manufactures on the market
7. How can we program an FPGA? VHDL Vs. Verilog
8. Extra material on Internet
Complex digital system design. EPS de Linares. Vicente Muñoz Diez. Office: D-115. Email: jmunoz@ujaen.es
1. A brief review about logic gates
The most basic and elemental digital logic gate is the inverter which is built
from two MOSFET transistors: NMOS and PMOS.
The layout defines all the masks necessary for creating the device.
The inputs and outputs of digital circuits can only be 0 (low level) or 1 (high
level).
Digital logic gates are defined by their table of truth
Asynchronous circuit
Complex digital system design. EPS de Linares. Vicente Muñoz Diez. Office: D-115. Email: jmunoz@ujaen.es
1. A brief review about logic gates
How fast is the response of an inverter?
Complex digital system design. EPS de Linares. Vicente Muñoz Diez. Office: D-115. Email: jmunoz@ujaen.es
1. A brief review about logic gates
CMOS technology allows to obtain complex logic gates only using MOSFET
transistors (resistors, capacitors or whatever else is not required).
What kind of logic
gate do we have ?
A B OUT?
0 0
0 1
1 0
1 1
Complex digital system design. EPS de Linares. Vicente Muñoz Diez. Office: D-115. Email: jmunoz@ujaen.es
1. A brief review about logic gates
CMOS technology offers to digital designers a paramount feature: scalability
Every logic
function can be
implemented by
NANDs gates
All the processes
can be developed
automatically from
the basic elements
Complex digital system design. EPS de Linares. Vicente Muñoz Diez. Office: D-115. Email: jmunoz@ujaen.es
1. A brief review about logic gates
The simplicity of the CMOS technology and its low power consumption are
the clues of its rise.
NAND GATE (CMOS Technology) NAND GATE (TTL Technology)
Complex digital system design. EPS de Linares. Vicente Muñoz Diez. Office: D-115. Email: jmunoz@ujaen.es
1. A brief review about logic gates
Homework: take a look to your notes about logic gates
OR NOR
NAND
XOR XNOR
Complex digital system design. EPS de Linares. Vicente Muñoz Diez. Office: D-115. Email: jmunoz@ujaen.es
1. A brief review about logic gates
Last challenge...
What kind of digital logic gate do we have ?
A B OUT?
0 0
0 1
1 0
1 1
Complex digital system design. EPS de Linares. Vicente Muñoz Diez. Office: D-115. Email: jmunoz@ujaen.es
2. What is a FPGA?
The acronym of FPGA comes from Field Programmable Gate Array
INPUTS OUTPUTS
Any connection is implemented inside the chip these ones have to be program by the user
Complex digital system design. EPS de Linares. Vicente Muñoz Diez. Office: D-115. Email: jmunoz@ujaen.es
3. Applications with FPGAs
Complex digital system design. EPS de Linares. Vicente Muñoz Diez. Office: D-115. Email: jmunoz@ujaen.es
3. Applications with FPGAs
Proximity
water sensor
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3. Applications with FPGAs
Land motor
Proximity land controller
sensor Function 1
Function 2
Driving System
Water sensor FPGA
Function 3
Water motor
Proximity controller
water sensor
The FPGA can be separately
programmed and the overall
system will still exhibit a real
time response
Complex digital system design. EPS de Linares. Vicente Muñoz Diez. Office: D-115. Email: jmunoz@ujaen.es
4. FPGA Vs. Processor
Land motor
Proximity land controller
sensor Function 1
Function 2
Driving System
Water sensor FPGA
Function 3
Water motor
Proximity controller
water sensor The FPGA's response
depend on the
propagation time and the
fanout.
For CMOS technology
fanout is ~34.000
Complex digital system design. EPS de Linares. Vicente Muñoz Diez. Office: D-115. Email: jmunoz@ujaen.es
4. FPGA Vs. Processor
Land motor
Proximity land controller
sensor Stack
Stack
Inst.1
pointer
Inst.2 Driving System
Water sensor Inst.3
Inst.4 Water motor
Proximity controller
water sensor Memory The processor is limited by the
internal clock.
If the processor needs too
much time for an instruction or
Processor cluster of them, the system
stops being a realtime system
Complex digital system design. EPS de Linares. Vicente Muñoz Diez. Office: D-115. Email: jmunoz@ujaen.es
4. FPGA Vs. Processor
The Curiosity was lunched in 2011 and landed on Mars in The FPGA has the advantage that
2012 . Although, it was governed by a processor, some can be reprogrammed from afar.
specifics tasks were controlled by FPGAs
Complex digital system design. EPS de Linares. Vicente Muñoz Diez. Office: D-115. Email: jmunoz@ujaen.es
5. Pitfalls of FPGAs
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6. Main manufactures on the market
Xilinx
On the market from 1984 Altera. No longer on the market!!
VHDL Evolution
Hardware program language created by U.S.
Defence Department for ASICs designs in 1981
Intermetrix, IBM and TI create a baseline language
IEEE leaded the project and publish the first
standard in 1987
The standard is revised each 5 year (or sooner)
Complex digital system design. EPS de Linares. Vicente Muñoz Diez. Office: D-115. Email: jmunoz@ujaen.es
7. How can we program an FPGA? VHDL Vs. Verilog
VHDL is used mostly
in Europe, Korea and
Japan
Verilog is used in
North and South,
South-East Asia and
India
VHDL Verilog
Strongly-typed Weak-typed
More verbose More concise
Very deterministic only deterministic if you follow some rules carefully
Non-C-like syntax More C-like syntax
Everything is exportable to Verilog No everything is exportable to VHDL
Complex digital system design. EPS de Linares. Vicente Muñoz Diez. Office: D-115. Email: jmunoz@ujaen.es
8. Extra material on Internet
Complex digital system design. EPS de Linares. Vicente Muñoz Diez. Office: D-115. Email: jmunoz@ujaen.es
Complex digital systems design
CHAPTER 2:
ARCHITECTURE OF
PROGRAMMABLE LOGIC DEVICES
Complex digital systems design. EPS de Linares. Vicente Muñoz Diez. Office: 110AB. Email: jmunoz@ujaen.es
Index
1. Introduction
2. Origin and classification of the PLDs and CPLDs
3. Architecture of the FPGAs
3.1 Types of FPGAs´ architectures
3.2 Main blocks in FPGAs
3.2.1 Logic blocks (LBs)
3.2.2 Input/output blocks (I/O blocks)
3.2.3 Specific functional blocks in FPGAs
3.3 Interconnection in FPGAs
3.3.1 Interconnection lines
3.3.2 Programmable connections
Complex digital systems design. EPS de Linares. Vicente Muñoz Diez. Office: D-115. Email: jmunoz@ujaen.es
1. Introduction
The are two ways when a digital implementation has to be done:
Complex digital systems design. EPS de Linares. Vicente Muñoz Diez. Office: D-115. Email: jmunoz@ujaen.es
1. Introduction
Software solution
Complex digital systems design. EPS de Linares. Vicente Muñoz Diez. Office: D-115. Email: jmunoz@ujaen.es
1. Introduction
Software solution
Complex digital systems design. EPS de Linares. Vicente Muñoz Diez. Office: D-115. Email: jmunoz@ujaen.es
1. Introduction
Software solution
The power of processor to handle and solve difficult tasks
is limited by
*) The sequential feature of its execution
*) The number of instructions is limited
Complex digital systems design. EPS de Linares. Vicente Muñoz Diez. Office: D-115. Email: jmunoz@ujaen.es
1. Introduction
Hardware solution
The designer has to define all the gates and the
interconnections between them (pitfall)
The circuit has an only one purpose but theoretically it
is faster than the solution implemented by software.
Complex digital systems design. EPS de Linares. Vicente Muñoz Diez. Office: D-115. Email: jmunoz@ujaen.es
1. Introduction
Hardware solution
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1. Introduction
Hardware solution
PLD and FPGA
The group of PLDs can be chronologically The FPGAs are an evolution of the PLDs
divided into the following categories : and could be included inside the group of
complex programmable logic devices
PROMs PALs PLAs GALs (CPLDs)
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2. Origin and classification of the PLDs and CPLDs
Floating gate
Fixed array
PROM
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2. Origin and classification of the PLDs and CPLDs
Fixed array
Programmable array
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2. Origin and classification of the PLDs and CPLDs
The PAL16L8 was a very popular
device which came in a 20 DIP
package
PAL16L8
How does
work?
Complex digital systems design. EPS de Linares. Vicente Muñoz Diez. Office: D-115. Email: jmunoz@ujaen.es
2. Origin and classification of the PLDs and CPLDs
All of them represent the origin of VHDL
Complex digital systems design. EPS de Linares. Vicente Muñoz Diez. Office: D-115. Email: jmunoz@ujaen.es
2. Origin and classification of the PLDs and CPLDs
Programmable Programmable
array array
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2. Origin and classification of the PLDs and CPLDs
GALs displayed
GAL 22V10 design
improvements to
handle the input and
output
Macro-Cells
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2. Origin and classification of the PLDs and CPLDs
Registered mode
S0= 0 S0= 1
S1= 0 S1= 0
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2. Origin and classification of the PLDs and CPLDs
Combinatorial mode
S0= 0 S0= 1
S1= 1 S1= 1
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3. Types of FPGAs´ architectures
Interconnection in FPGAs
- Interconnection lines
- Programmable connections
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3.1 Architecture of the FPGAs
According to the placing of the According to the placing of the connections lines
connections lines and logic blocks
Manhattan architecture
Channel-less
Sea of Gates
architecture
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3.1 Architecture of the FPGAs
Terrace architecture
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3.1 Architecture of the FPGAs
Manhattan architecture
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3.1 Architecture of the FPGAs
Complex digital systems design. EPS de Linares. Vicente Muñoz Diez. Office: D-115. Email: jmunoz@ujaen.es
3.2.1 Logic blocks in FPGAs
WARNING: each brand uses its own nomenclature which can even depend
on the FPGA series.
ALTERA
Simple logic blocks : Logic Elements (LEs)
Complex logic blocks: Logic Array Blocks
(LABs -Cyclon III-), Adaptive Logic Module
(ALM -Cyclon V-)
XILINX
Simple logic blocks : Logic blocks (LB)
Complex logic blocks (Virtex II): Slice
(composed by 4 LB), Configurable Logic
Block (CLB, composed by 4 slices) .
In other families (Spartan): SLICEL,
SLICEM, , SLICEX
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3.2.1 Logic blocks in FPGAs
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3.2.1 Logic blocks in FPGAs
The FPGAs from the family CK20K (currently obsolete) by Croospoint has
this configuration based on 2 lines of transistors (PMOS and NMOS) call
Transistor Pair Tile
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3.2.1 Logic blocks in FPGAs
GATE 1? ? GATE 2?
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3.2.1 Logic blocks in FPGAs
Good example of
terrace
architecture
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3.2.1 Logic blocks in FPGAs
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3.2.1 Logic blocks in FPGAs
The family XC8100 by Xilinx has the possibility to define 4 different kinds of
combinational functions depending on two control signals
How many
data inputs?
Complex digital systems design. EPS de Linares. Vicente Muñoz Diez. Office: D-115. Email: jmunoz@ujaen.es
3.2.1 Logic blocks in FPGAs
X1
Draw the internal design of a 3 input
f
X2 LUT configured for implementing a
X3 NAND gate
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3.2.1 Logic blocks in FPGAs
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3.2.1 Logic blocks in FPGAs
Post-Mapping provided an
specific implementation for
the FGPA serie
Post-Fitting provided an
specific implementation for
the model of the FGPA inside
the serie.
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3.2.1 Logic blocks in FPGAs
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3.2.1 Logic blocks in FPGAs
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3.2.1 Logic blocks in FPGAs
It is possible to track
down the physical
implementation till
arrive inside the Logic
Elements
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3.2.1 Logic blocks in FPGAs
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3.2.1 Logic blocks in FPGAs
Bypass
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3.2.1 Logic blocks in FPGAs
The full adder is a useful resource which allows arithmetic operations (sums,
products, counters and so on) to be done by the logic block
Complex digital systems design. EPS de Linares. Vicente Muñoz Diez. Office: D-115. Email: jmunoz@ujaen.es
3.2.1 Logic blocks in FPGAs
Altera calls their logic blocks Logic Elements which are implemented using a
standard architecture based on lookup tables + adder + flip-flop
Logic
Element
from
Cyclone II
family by
Altera
For Cyclone family the LEs are gathered in blocks of 16 LEs named Logic Array Blocks (LABs)
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3.2.1 Logic blocks in FPGAs
LE1
LE2
LE3
LE4
LE5
LE6
LE7
LE8
LE9
LE10
LE11
LE12
LE13
LE14
LE15
LE16
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3.2.1 Logic blocks in FPGAs
Nomenclature
Altera: input-output element (IOE)
Xilinx: input-output cell (I/O cells)
Lattice: Programmable I/O Cell (PIC)
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3.2.2 Input/Output blocks in FPGAs
Main elements of an I/O block
The tristate control will define the operation of the The output buffer will adapt the output to
output buffer the output standard used (TTL, LVTTL
LVCMOS, PCI, etc.) or to set the line in
high impedance. The output also
incorporates flip-flops.
The input buffer will enhanced the input signal and will join the
external input into the connection resources of the FPGA
passing through optional delays or flip-flops
Complex digital systems design. EPS de Linares. Vicente Muñoz Diez. Office: D-115. Email: jmunoz@ujaen.es
3.2.2 Input/Output blocks in FPGAs
FPGAs packaging types
Field-programmable gate arrays are available in a variety of IC package types and with
different numbers of pins and flip-flops. Usual IC package types for field-programmable
gate arrays are listed below:
Ball grid array (BGA) Very popular nowadays
Quad flat package (QFP)
Advantages
1) High density (hundreds of pins)
2) Low thermal resistance (better cooling)
3) Low-inductance leads and parasitic capacitances
Disadvantages
1) Inflexible (problems related to thermal stress)
2) Difficulty of inspection (X-ray or boundary scan)
3) Without reliable sockets for development
4) Equipment cost
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3.2.2 Input/Output blocks in FPGAs
Main elements of an I/O block (General overview)
The figure describes the main blocks of I/O cell from XC4000 family by Xilinx
3 Output stage:
1) Programmable buffer
2) Direct/registered output through FF
1
3) Slew Rate Control
2
A
Input stage:
A) Input buffer
C B B) Programmable delay
C) Direct/registered output through FF
Complex digital systems design. EPS de Linares. Vicente Muñoz Diez. Office: D-115. Email: jmunoz@ujaen.es
3.2.2 Input/Output blocks in FPGAs
Main elements of an I/O block (Programmable output buffer)
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3.2.2 Input/Output blocks in FPGAs
Main elements of an I/O block (Programmable output buffer)
The existed I/O standards are identified by the power supply and 4 remarkable voltages
and their margin noise values:
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3.2.2 Input/Output blocks in FPGAs
Main elements of an I/O block (Programmable output buffer)
Different I/O standards are identified by the power supply and 4 remarkable voltages:
Complex digital systems design. EPS de Linares. Vicente Muñoz Diez. Office: D-115. Email: jmunoz@ujaen.es
3.2.2 Input/Output blocks in FPGAs
Main elements of an I/O block (Programmable output buffer)
TTL inverter
CMOS inverter
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3.2.2 Input/Output blocks in FPGAs
Main elements of an I/O block (Programmable output buffer)
For Cyclone II a huge range of I/O standards could be used but, what is the reason of
this evolution regarding the fall of the voltage supply and also the margines noise?
P∝f2
P = I x V = I x ( VDD -VSS )
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3.2.2 Input/Output blocks in FPGAs
Main elements of an I/O block (Slew-rate control)
What is the Slew Rate?
Slew rate is the maximum voltage change per unit time in a
node of a circuit (typically the output), due to limited
current sink or source
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3.2.2 Input/Output blocks in FPGAs
Main elements of an I/O block (Slew-rate control)
Example 1
A digital circuit -which implements a double CMOS inverter- is exited with a 400 ps width
square wave at the input. The wave form is registered at the output, obtaining the
following measurements:
Represent the output and the input signal
tr = 80 ps tpd= 35 ps
Find the slew-rate of the output line
tf = 80 ps
Example 2
Find if an FPGA which implements a LVCMOS-3.3V standard output and displays a SR= 20
V/ns can be used for a application where a time rise of 30 ps is needed
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3.2.2 Input/Output blocks in FPGAs
Main elements of an I/O block (Slew-rate control)
The slew rate can be controlled for the Cyclone family by Altera
High slew-rate → Shape wave forms → High number of harmonics → EMI increasing
Medium slew-rate → Soft wave forms → Control of the harmonics → EMI controlling
Low slew-rate → no-shape wave forms → is it a 0 or 1? → Metastability
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3.2.2 Input/Output blocks in FPGAs
I/O blocks in commercial FPGAs (Cyclone II family by Altera)
1
2
3
2
4
2
5 5
1,3
4 6
6
output stage
1 Different I/O standards (LVTTL, LVCMOS, etc), slew-rate and current strength
2 Weak pull-up resistor to set the output to 1 by default
5
3 Tri-state buffer to isolate the output stage
4 Bus-hold circuitry very useful to keep the last state of the bus
5 Programmable delays to avoid to minimise set-up times
6 Open-drain output enables the device to provide system-level control signals
Input stage 7 Clamp diode for protection and adjustment of the logic levels
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3.2.2 Input/Output blocks in FPGAs
Clamp diodes
Clamp diodes are used for adding protection against harmful inputs although
they can be also used to adapt the voltage input levels.
Overshoot demising
because of clamp diodes
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3.2.2 Input/Output blocks in FPGAs
A delay setting in an I/O path affects the timing requirement on that pin. Use
programmable delay to improve the read or write timing in an interface.
Quartus II development software automatically programs these delays if you constrain the input or
output port. Use the set_input_delay or set_output_delay command with the TimeQuest timing analyzer
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3.2.2 Input/Output blocks in FPGAs
The undriven pins have to be avoided at all cost s due to line noise could
produce an unexpected 0 or 1. The I2C protocol bus set by default the
line to a high logic level by means a pull-up resistor.
The elements involve in the communication can only set the data or
clock line to zero by means a open drain output.
Let go to see a
transmission example
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3.2.2 Input/Output blocks in FPGAs
I2C Protocol. An example of open drain output
A B
1 1,0,1,0,1,0
0 0,1,0,1,0,1
1 0 Wake up!!
0 1 0 0
0 0 0 0
Disengage port (IDLE) The master takes the control
0 0 (start bit)
0 0
D
1,0,1,0,1,0 1,0,1,0,1,0
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3.2.2 Input/Output blocks in FPGAs
(Cyclone II family by Altera)
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3.2.2 Input/Output blocks in FPGAs
The I/O pins assignment in Cyclone II can be modified and checked by the tool Pin Planner
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3.2.2 Input/Output blocks in FPGAs
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3.2.2 Input/Output blocks in FPGAs
Complex digital systems design. EPS de Linares. Vicente Muñoz Diez. Office: D-115. Email: jmunoz@ujaen.es
3.2.2 Input/Output blocks in FPGAs
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3.2.2 Input/Output blocks in FPGAs
Tri-state control line stage
(Spartan II family by Xilinx)
2 7
1,3
output stage 4
5 6
2 Pull-up and pull-down resistor network
3 Tri-state buffer to isolate the output stage
4 Keeper latch circuitry to hold the last state of the bus
5 Programmable delays to avoid to minimise setup times
6 Vref pins to define a user-supplied threshold voltage for 1 logic input
Input stage 7 Protection against damage from electrostatic discharge (ESD) and over-voltage
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3.2.2 Input/Output blocks in FPGAs
(Spartan II family by Xilinx)
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3.2.3 Specific functional blocks in FPGAs
Most of the commercial FPGAs have and unspecific number of functional blocks which
carry out particular tasks. Some of this blocks could be implemented using standard
logical blocks however, the use and inclusion of these functional blocks made the
process more efficient.
Some of the most common specific functional blocks included in the commercial FPGAs
available on the market are listed below:
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3.2.3 Specific functional blocks in FPGAs
RAM memory
The RAM (random access memory) memory is included by the manufactures to provide
an easy way to have a element to store information which will be used during the
processes carried out by the FPGA.
The RAM memory can be implemented by logic blocks using the SRAM included in the
LUT. But, it is technically a waste of resources because the size of the built RAM is small
2m x n
Size (bits) of data stored by the memory
Size (bits) of the address
CLK Number of addressable storage units
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3.2.3 Specific functional blocks in FPGAs
RAM memory
RAM memories can be divided into single port or dual port memories depending on
the possibility of accessing to a memory address at the same time by two different paths.
Port 1
SRAM cell memory
Port 2
Dual port memories need more MOSFETs per memory cell thus, the area needed is higher. However, they allows a double access memory
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3.2.3 Specific functional blocks in FPGAs
RAM memory
Depending on the need to refresh the memory or not, RAM memories can be divided into
DRAM (dynamic RAM) or SRAM (Static RAM).
SRAM: if the power supply turns off the information will be lost although it is not needed
to refresh the memory to hold the information
DRAM: if the power supply turns off the information will be lost but, in addition it is
necessary to refresh the memory to hold the information
DRAM cell memory
Depending on the synchronism established according to the system clock for reeding or writing on the
memory, RAM memories can be divided into SDR SRAM and DDR SRAM.
SDR SDRAM: The data will be read or write according to the positive-going transition (raising edge) of the
clock
DDR SDRAM: The data will be read or write according to the positive-going and negative-going transition
(rising and falling edge) of the clock. Double Data Rate compare to SDR RAM
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3.2.3 Specific functional blocks in FPGAs
RAM memory blocks on the market for expansion sockets
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3.2.3 Specific functional blocks in FPGAs
RAM memory in commercial FPGAs (Cyclone II family by Altera)
Complex digital systems design. EPS de Linares. Vicente Muñoz Diez. Office: D-115. Email: jmunoz@ujaen.es
3.2.3 Specific functional blocks in FPGAs
RAM memory in commercial FPGAs (Cyclone II family by Altera)
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3.2.3 Specific functional blocks in FPGAs
RAM memory in commercial FPGAs (Cyclone II family by Altera)
Complete the following table for the different ram memory configurations for
Cyclone II
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3.2.3 Specific functional blocks in FPGAs
RAM memory in commercial FPGAs (Cyclone II family by Altera)
Memory for embedded processors (NIOS II)
Rd/Wr data for arithmetic computations (FIR filters)
Direct Digital Synthesis (DDS)
Long or width shift registers
Programmable delays
Circular Buffers (FIFO buffer)
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3.2.3 Specific functional blocks in FPGAs
RAM memory in commercial FPGAs (Spartan II family by Xilinx)
SRAM Memory
The memory blocks present at the Spartan II FPGA family can be configured to
obtain different ranges of width (bits for word) and depth (number of words) as it
happens for FPGAs by Altera
2m x n
Size (bits) of data stored by the memory
Size (bits) of the address
Number of addressable storage words
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3.2.3 Specific functional blocks in FPGAs
MULTIPLIERS
The digital signal processing (DSP) are based on two digital blocks: multipliers and
adders. Both digital functions can be implemented by logic blocks however, the
implementation of these devices by logic block implies a high cost of resources.
The new FPGAs available on the market include multipliers or more complex logic
blocks able to process signals (adding and multiplying) such as DSPs
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3.2.3 Specific functional blocks in FPGAs
MULTIPLIERS
The multipliers are usually placed close to the memory blocks for minimising the
input/output delay. For the family Cyclone II by Altera the multipliers operate with two
factors (A and B) of 18 bits expressed in two's-complement representation. The product
result (P) is a 36 bits data expressed in two's-complement representation as well.
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3.2.3 Specific functional blocks in FPGAs
MULTIPLIERS
1101 00000000
As the adders present in the logic blocks, the
multiplexers can be built using several ways. The shown
method uses shift left registers, adders and
multiplexers.
1
1101
X 1011 11010 1101
1101
11010 1
100111 100111
110100
0000
100111 0
1101000
1101000 100111
10001111
1
The digital signal processing blocks (DSPs) are logic block whose
architecture is optimised for the operational needs of digital signal processing.
Xilinx included DSPs in theirs high capacity an ALTERA included DSPs from Cyclone III
performance FPGAs (included from 2010 in and in Stratix family
Virtex IV)
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3.2.3 Specific functional blocks in FPGAs
DSPs
DSPs can be consider as a microprocessor with a short list of instructions
focused on a specific arithmetical operations and with a low consumption
compare to a common processor.
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3.2.3 Specific functional blocks in FPGAs
DSPs applications
Machine vision (MV) refers to both industrial and non-industrial applications where
operational guidance is provided to equipment for the execution of functions based on
the capture and analytical processing of images (Embedded Machine Vision, Printers,
Scanners, Currency, Smart Cameras and Large scale inspection)
Avionics and defence including single and multicore ARM, DSP, and ARM+DSP, are
well-suited to defence and avionics applications including radar, electronic warfare,
avionics, and software defined radios (SDR).
Biometrics. DSPs are widely used for biometric applications such as iris or fingerprint
biometric
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3.2.3 Specific functional blocks in FPGAs
PLLs
FPGAs have dedicated hardware to generate the clock signals. The most
common used device for this purpose is the Phase-Lock Loop (PLL).
Complex digital systems design. EPS de Linares. Vicente Muñoz Diez. Office: D-115. Email: jmunoz@ujaen.es
3.2.3 Specific functional blocks in FPGAs
PLLs
The PLL is a device utilised to regenerate the clock signal and avoid the
possible delays that could appear as a result of the rutting
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3.2.3 Specific functional blocks in FPGAs
PLLs
Block diagram of a
PLL circuit
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3.2.3 Specific functional blocks in FPGAs
PLLs (XILINX: Digital clock managers DCM)
The Digital Clock Manager (DCM) are the blocks used by Xilinx to regenerate and
establish the clock signal of the system. Their main features are listed below
1) Suppress the clock skew 3) Suppress the clock skew, rebuild the signal and
adapt the input clock signal to a different standard
2) Multiply or divide the clock signal (LVTTL, LVDS and so on)
3
General overview
of a DCM by Xilinx
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3.2.3 Specific functional blocks in FPGAs
PLLs (XILINX: Digital clock managers DCM)
The clock signal uses dedicated interconnections lines where their placement in the
overall layout of the FPGA is very specific in order to avoid delays.
Buffer
Clock Buffers are used to establish a
distribution suitable clock level. Buffers and
from Spartan DCMs have dedicated lines to be
family by Xilinx connected to each other and avoid
the transitions delays
Buffer Buffer
Buffer
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3.2.3 Specific functional blocks in FPGAs
PLLs and Clock signals in VHDL
The are several rules of thumb which must be followed to avoid problems related
to the clock signal: glitch
Glitch: it is an undesired transition that occurs before the signal settles to its intended value
Imagine that situation where the designer decided to hold the flip-flop output asynchronously:
CLK
Enable BAD DESIGNED
The glitch is a problem that appears when there is some delay charge on the clock signal and
and as a result there is an unexpected output.
Complex digital systems design. EPS de Linares. Vicente Muñoz Diez. Office: D-115. Email: jmunoz@ujaen.es
3.2.3 Specific functional blocks in FPGAs
PLLs and Clock signals in VHDL
The are several rules of thumb which must be followed to avoid problems related
to the clock signal: glitch
As a rule of thumb the clock signal must not be charged with any extra delay. In other words, the
clock lines have to go from the clock block managers to the logic blocks without passing through
any combinational function.
Enable
Process (clk)
WELL DESIGNED Begin
If (reset= '1') then
.....................
elseif ( rising_edge (clk) ) then
X<= '0';
CLK Take
Y<=X;
care
F<=Y;
.........
Wrong elseif ( rising_edge (clk) ) then
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3.3 Interconnection resources in FPGAs
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3.3 Interconnection resources in FPGAs
Interconnection lines
Configurable
connections
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3.3.1 Interconnection lines
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3.3.1 Interconnection lines
The table below lists the number and characteristics of the available
interconnections for a complex logic block (CLB) for the Virtex 2 family by Xilinx
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3.3.2 Configurable connections
The pass-transistors are the element used to implement the connections between
global vertical and horizontal lines
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