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Dept of Electronics & Communication Engg
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INDEX
3 INSTRUMENTATION AMPLIFIER 13
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INVERTING AMPLIFIER:-
CIRCUIT DIAGRAM:-
Rf
+15v
R1=10K 2 7
-
IC 741
Signal
Generator + 3 + 4
6
+
~
Vin CRO
-15v
- -
TABULATION:
MODEL GRAPH:
Vin
INPUT
Time (ms)
Vout
OUTPUT
Time (ms)
3
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EXP.NO: 01 DATE:
AIM:
To design the Inverting, Non-Inverting and Differential Amplifiers using
Op-amp IC741 and test their performance.
APPARATUS REQUIRED:
THEORY:
Op-amp in open-loop configuration has a very few application because
of its enormous open-loop gain. Controlled gain can be can be achieved by taking a
part of output signal to the input with the help of feedback. This is called as Closed-
Loop Configuration. The three basic types of closed-loop amplifier configuration
are: 1. Inverting amplifier.
2. Non-inverting amplifier.
3. Differential amplifier.
The entire configuration can be operated with either AC or DC input.
INVERTING AMPLIFIER:-
Rf
The circuit closed-loop voltage gain is Avcl .
R1
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NON-INVERTING AMPLIFER:-
CIRCUIT DIAGRAM:-
Rf
+15v
R1=10K 2 7
-
IC 741
+ 3 + 4
6
+
Signal Vin
~ CRO
Generator - -15v
-
TABULATION:
MODEL GRAPH:
Vin
INPUT
Time (ms)
OUTPUT
Vout
Time (ms)
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THEORY – (NON-INVERTING AMPLIFIER):-
If the input signal is given to non inverting terminal & the feedback
from output is connected to inverting terminal of an op-amp through a potential
divider network, then it is called as Non-Inverting Amplifier Configuration. It
operates in a same way as a voltage follower (unity gain buffer), except that the
output voltage is potentially divided before it is fedback to the inverting input
terminal. No phase shift or change in the circuit closed loop polarity occurs voltage
Rf
gain is Avcl 1 R1
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DIFFERENTIAL AMPLIFIER:-
CIRCUIT DIAGRAM:-
Rf=R2=100K
+15v
R1=10k 2 7
-
IC 741
Signal
Generators + 6
R1=10K 3 4 +
+ +
~ ~ R2=100K CRO
Vin1 Vin2 -15v
-
TABULATION:
2.
3.
7
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THEORY-(DIFFERENTIAL AMPLIFIER):-
A configuration which combines inverting & non-inverting
configuration with both input terminals are supplied with Vin1 & Vin2, then it is
called as Differential Amplifier configuration. This circuit amplifies the difference
between the two inputs. Differential amplifier with a single op-amp has the exact gain
of an inverting amplifier and it is given as
Vo Rf
AD (Using One Op-Amp) AVCL
(Vin1 Vin 2 ) R1
A differential amplifier with two op-amps has the exact gain of a non-inverting
amplifier and it is given as:
Vo Rf
AD (Using Two Op-Amps) AVCL 1 .
(Vin1 Vin 2 ) R1
PROCEDURE:
1. Select the value of R1, R2, R3 & Rf such that R1=R2 and R3=Rf.
2. Connect the circuit as per as the circuit diagram.
3. Provide constant input voltage Vin1 to Non-inverting terminal of op-amp
through R1 & constant input voltage Vin2 to inverting terminal of op-amp
through R2.
4. Measure the output voltage using CRO.
5. Calculate the theoretical gain and compare it with practical gain.
6. Practical gain & theoretical gain should be approximately equal.
7. Plot the graph of the input wave versus output wave for any one practical case.
RESULT:
Thus the Inverting, Non-Inverting and Differential Amplifiers are
designed and their performance was successfully tested using op-amp IC 741.
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INTEGRATOR:-
CIRCUIT DIAGRAM:-
Cf=0.01uf
Rf=15k
+15v
R1=1.5k 2 - 7
6
Signal IC 741
Generators +
+ 3 4 +
Vin ~ 1.5K
Rcomp
RL=10k CRO
-15v
-
TABULATION:
Frequency Output Voltage Gain = 20 log (V0 /Vin)
S.No
(Hz) (Volts) (dB)
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
MODELGRAPH:
9
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APPARATUS REQUIRED:
CIRCUIT DIAGRAM:
Cf=0.005μf
Rf=1.5k
+15v
R1=100Ω C1=0.1μf 2 - 7
6
IC 741
+ 3 + 4 +
ROM=100Ω R3=10K CRO
Signal
Generators -15v
-
0
TABULATION:
1. Frequency (Input)
2. Input Voltage (Vin peak)
3. Input Time Period (tVin)
4. Output Voltage (Vout peak)
5. Output Time Period (tVo)
MODEL GRAPH:
(i) SINE WAVE INPUT
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THEORY- (DIFFERENTIATOR):-
A differentiator or differentiation amplifier is a circuit which performs
the mathematical operation of differentiation; that is, the output waveform is the
derivative of the input waveform. The differentiator may be constructed from the
basic inverting amplifier if an input resistor R1 is replaced by capacitor C1. The
differentiation is very useful to find the rate at which a signal varies with time. For
maintaining the stability of differentiator, a series resistor R1 is connected with input
capacitor C1. the circuit will provide differentiation function but only over a limited
frequency range & over this range differentiator tend to oscillate (or) poor stability
dVin
results. The expression for output voltage is Vo R f C1
dt
PROCEDURE:
1. Select fa equal to the highest frequency of the input signal to be differentiated.
Calculate the component values of C1 & Rf.
2. Choose fb = 20fa & calculate the values of R1 & Cf, so that R1C1=Rf Cf.
3. Connect the components as shown in the circuit diagram.
4. Apply a sinusoidal & square wave input to the inverting terminal of op-amp
through R1 C1.
5. Observe the shape of the output signal for the given input in CRO.
6. Note down the reading and plot the graph of input versus output wave for both
cases.
(ii) SQUARE WAVE INPUT
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DESIGN PROCEDURE-(INTEGRATOR):-
Design of integrator to integrate at cut-off frequency 1 KHz.
1
Take fa =
2 Rf C f
= 1KHz.
Always take Cf < μf and
Let Cf = 0.01μf
1
Rf =
2 C f fa
Rf = 15.9KΩ ≡
Rf = 15KΩ
1
Take fb = = 10KHz.
2 R1C f
1
R1 = = 1.59KΩ.
2 fbC f
R1 ≡ 1.5KΩ
R1 R f
Rcomp = R1 // Rf = ≡ R1, Assume RL = 10KΩ
R1 Rf
Rcomp = 1.5KΩ
DESIGN PROCEDURE-(DIFFERENTIATOR):-
Design a differentiator to differentiate an input signal that varies in frequency
from 10Hz to 1KHz. Apply a sine wave & square wave of 2Vp-p & 1KHz frequency
& observe the output.
To find Rf & C1
Given: fa = 1KHz.
1
fa =
2 R f C1
fa = 1KHz.
Assume C1 = 0.1μf
Rf = 1.59KΩ ≡ 1.5KΩ
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To find R1 & Cf
Select fb = 20fa with R1 C1 = Rf Cf
1
fb = 20KHz =
2 R1C1
R1 = 79.5Ω ≡ 100Ω
6
RC 82 X 0.1X 10
Cf = 1 1 =
Rf 1.5K
Cf = 0.005μf.
Rom ≡ R1 // Rf = 100Ω
RESULT:
Thus an Integrator and Differentiator using op-amp are designed and their
performance was successfully tested using op-amp IC 741.
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CIRCUIT DIAGRAM:
+15v
3 7
+ Rf=1K
IC 741
6
2 - 4
+15v
R2=1K
-15v
R1=1K 2 7
-
IC 741
6
RG 22K 3 + 4
+ R1=1K
V1
-
~ R2=1K
-15v
+15v R1=1K V
-
2 7
-
IC 741
6
+ 3 + 4
~
V2
-15v
-
15
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INSTRUMENTATION AMPLIFIER
EXP.NO: 03 DATE:
AIM:
To construct and test the CMRR of an instrumentation amplifier using op-amp
IC741.
APPARATUS REQUIRED:
THEORY:
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TABULATION:
Vo
RG VI V2 Vo Ac =
S.No V1 V2
(KΩ) (Volts) (Volts) (Volts)
2
1.
2.
3.
4.
5.
V1 V2 Vo Vo CMRR =
S.No RG (KΩ) Ad =
20 log ( Ad )(dB)
(Volts) (Volts) (Volts) V1 V2 Ac
1.
2.
3.
4.
5.
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PROCEDURE:
1. Select the entire resistor with same value of resistance R. Let RG be the gain
varying resistor with different values of resistance for simplicity let RG, be a
constant value.
2. Connect the circuit as shown in the circuit diagram.
3. Give the input V1 & v2 to the non-inverting terminals of first & second op-
amp respectively.
4. By varying the value of RG, measure the output voltage for common mode and
differential mode operation. Since RG is selected as constant value, provide
different input value of V1 & V2.
5. Calculate the differential mode gain Ad and common mode gain Ac to
Ad
calculate the CMRR as CMRR=20 log .
Ac
RESULT:
Thus an instrumentation amplifier was constructed and CMRR is
tested using op-amp IC 741.
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LOWPASS FILTER:-
CIRCUIT DIAGRAM:-
R1=27K RF=20K
+15v
2 - 7
Signal IC 741
Generator 1.5K
3 + 4
6
+ +
Vin ~ 0.1uf
-15v
RL=10K CRO
-
TABULATION:
Frequency Output Voltage Gain = 20 log (V0 /Vin)
S.No
(Hz) (Volts) (dB)
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
MODEL GRAPH:
19
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APPARATUS REQUIRED:
From the frequency response, when f<fH; the gain is maximum lAl. When
A
f=fH; the gain is 70.7% of the maximum gain and when f fH; the gain drops or
2
rolls off. The frequency range from 0 to fH is called as Passband & fH to is called
as Stopband. Out of Butterworth, chebyshev & cauer filters, Butterworth filter is
preferred because it has flat pass band as well as flat stop band (flat-flat) filter.
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+15v
2 7
-
Signal 0.1μf IC 741
Generator
3 + 4
6
+
+
Vin ~ 1.5K -15v
RL=10K CRO
-
TABULATION:
Frequency Output Voltage Gain = 20 log (V0 /Vin)
S.No
(Hz) (Volts) (dB)
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
MODEL GRAPH:
21
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Design a HPF at cutoff frequency fL of 1KHZ & P.B gain of 2. Follow the same
procedure as LPF & interchange the R & C position with capacitor first & resistor in
parallel.
Vo Af ( f / f L )
In high pass filter Theoretical gain is given as =
Vin 1 ( f / f H )2
PROCEDURE - (LPF & HPF):
1. Connect the circuit as shown in the circuit diagram.
2. Select the corresponding cut-off frequency (higher or lower) and determine the
value of C&R. select the value of R1 & Rf depending on desired passband
gain Af..
3. Apply a constant voltage input sinusoidal signal to the non-inverting terminal
of op-amp.
4. Tabulate the output voltage Vo with respect to different values of input
frequency.
5. Calculate passband gain and plot the graph of frequency versus voltage gain &
check the graph to get approximately the same characteristic as shown in the
model graph.
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+15v
+15v
2 7
2 7
-
Signal 0.1uf
- IC 741
6
Generator IC 741 3 + 4
6 1.5K
3 + 4 +
+ CRO
Vin ~ 1.5K -15v
0.01uf -15v
RL=10K -
TABULATION:
Frequency Output Voltage Gain = 20 log (V0 /Vin)
S.No
(Hz) (Volts) (dB)
MODEL GRAPH:
23
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A filter which has a pass band between two cut-off frequencies fH & fL
is called as Bandpass filter. Where fH > fL BPF is basically of two types
(i) Wide band pass filter. (ii) Narrow band pass filter.
Based on figure of merit or quality factor Q, the types are classified as follows. If
Q<10, selectivity is poor & allows higher bandwidth & such BPF is called as wide
BPF.
If Q > 10, selective is more and allows only narrow bandwidth & such
BPF is called as Narrow BPF. Relationship between Q & center frequency fC is
given as
fc fc
Q & fc fH fL
BW fH fL
When frequency fL < f < fH then gain is maximum. At f < fL the gain is
gradually increasing (positive roll-off) from lower value & at f > fH the gain is
gradually decreasing (Negative roll-off) & exactly when f = fL & f = fH the gain is
A
70.7% of maximum gain .
2
PROCEDURE:
1. Select the lower and higher cut-off frequency and calculate the value of R & C
for the given frequencies.
2. Design for LPF & HPF separately and then combine the circuit by first placing
the HPF followed by a LPF (i.e) HPF in series with LPF.
3. Connect the circuit as shown in the circuit diagram.
4. Apply a constant voltage input sinusoidal signal to the non-inverting terminal
of op-amp.
5. Tabulate the output voltage Vo with respect to different values of input
frequency.
6. Calculate passband gain and plot the graph of frequency versus voltage gain &
check the graph to get approximately the same characteristic as shown in the
model graph.
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DESIGN PROCEDURE - (ACTIVE BPF):-
Design a BPF to pass a band of 1KHz to 10KHz with a passband gain of 4.
1. Select the highest cut-off frequency of LPF as fH = 10 KHz and the lowest cut-
off frequency of HPF as fL = 1 KHz.
2. Design the HPF first by taking fL = 1KHz. Assume the value of C < 1μf.
Let C = 0.1μf.
3. Calculate R from the expression.
1 1
FL = ; Therefore R1 =
2 RC 2 f LC
1
R= ;
2 (1KHz )(0.1X 10 6 )
R = 1.59KΩ ≡ R=1.5KΩ
4. Then design the LPF by taking fH = 10KHz. Assume the value of C < 1μf. Let
C = 0.01μf.
1 1
5. Calculate R from the expression fH = ; Therefore R =
2 RC 2 fHC
1
R= ;
2 (10 KHz )(0.01X 10 6 )
R = 1.59KΩ ≡ R=1.5KΩ
6. Calculate the values of Rf & R1 with the use of pass band gain.
Overall P.B gain of BPF = 4 = 2 (HPF) X 2 (LPF)
Therefore for both HPF & LPF the value of Rf = R1 to obtain a individual
Rf
P.B gain of 2. Af = (1+ ) = 2 (for HPF)
R1
Rf
Af = (1+ ) = 2 (for LPF)
R1
Let Rf = R1 = 22KΩ.
fc fc
7. Q of the filters is calculated as =
B.W fH fL
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DESIGN PROCEDURE (ACTIVE LPF):
Design a LPF at cutoff frequency fH of 1KHz with a passband gain of 2.
1. Choose the given value of fH = 1KHz.
1
R= = 1.5KΩ
2 X 1X 10 3 X 0.1 f
R = 1.5KΩ C = 0.1μf
4. Determine the value of R1 & Rf from pass band gain of the filter.
Rf
Af = 1 + = 2.
R1
Therefore Rf =R1 to select Af = 2.
Assume Rf = R1 = 22KΩ & Assume RL = 10KΩ
RESULT:
Thus an Active Lowpass, High pass and Band Pass Filters are designed
and tested using op-amp IC 741.
26
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+15v
0.01uf
2 - 7
IC 741
Vc + 6 R2=DRB
3 4
+
CRO
-
Vref R1=10K
TABULATION:
Output
waveform
Capacitive
waveform
MODEL GRAPH:
27
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EXP.NO: 05 DATE:
AIM:
To design an Astable, Monostable multivibrator and Schmitt trigger
using op-amp IC 741 and to test their characteristics.
APPARATUS REQUIRED:
THEORY-(ASTABLE MULTIVIBRATOR):-
28
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DESIGN PROCEDURE:-
Design of square wave generator at f0 = 1 KHz.
1. The expression of fo is obtained from the charging period t1 & t2 of capacitor
1
as fo =
2 RC ln[1 (2 R1 / R2 )]
1
= 1.16R1, such that fo simplifies to fo =
2 RC
1
4. Assume the value of C & Determine R from fo =
2 RC
Let C = 0.01μf
1 1
R= =
2 f oC 2 X (1X 10 )(0.01X 10 6 )
3
R = 50KΩ ≡ R = 47KΩ
29
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PROCEDURE:
1. Calculate the value of components using the design procedure given.
2. Connect the circuit as per as the circuit diagram.
3. As there is no specific input signal for this circuit switch ON the power
supply.
4. Note down the reading for output square wave (i.e) time & amplitude and
tabulate it.
5. Note down the reading for capacitor voltage & tabulate it.
6. Plot the reading in the graph and compare it with model graph.
30
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+15v
2 7
- R3=47K
IC 741
6
C=0.01uf D1 3 + 4
R1=10K
-15V
+
D2 CRO
C1=0.1uf -
R2=10K
Triggering
R4=100Ω
Input
Vin
TABULATION:
Amplitude Time period
S.No Waveforms
(volts) (ms)
1. Input waveform
2. Output waveform
3. Capacitive waveform
MODEL GRAPH:
INPUT
TIME (ms)
AMPLITUDE
OUTPUT
TIME (ms)
31
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DESIGN PROCEDURE:
PROCEDURE:
1. Calculate the value of components using the design procedure given.
2. Connect the circuit as per as the circuit diagram.
3. Apply the negative trigger voltage to the non-inverting terminal.
4. Note down the reading for output voltage Vo & ON & OFF time period &
tabulate it.
5. Note down the reading for capacitor voltage & tabulate it.
6. Plot the reading in the graph and compare it with model graph.
32
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SCHMITT TRIGGER:-
CIRCUIT DIAGRAM:-
+15v
ROM=R1//R2 7
-
10KΩ IC 741
3 + 4
6
+
Vin ~ -15V RL=10K
CRO
+
R2=100K -
R1
10K
TABULATION:
O/P
I/P Voltage I/P Time VUT (UTP) VLT (LTP) O/P Time
Voltage
(Volts) (ms) (Volts) (Volts) (ms)
(ms)
MODEL GRAPH:
33
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THEORY-(SCHMITT TRIGGER):-
34
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DESIGN PROCEDURE:-
1. Select the desire value of Vut & Vlt with same magnitude & opposite polarity.
Let Vut = 1V & Vlt = -1V.
2. For Op-amp 741C ± Vsat ≡ ±13V to ± 14V. And assume Vref = 0, Since the
another end of R1 is grounded.
6. Calculate ROM by
R1R 2 (10 K )(100 K )
ROM = R1 // R2 = .
R1 R 2 110 K
1000 K
ROM = ≡ 10KΩ. & select RL = 10KΩ (Assumption)
110 K
7. Calculate hystersis voltage
Vhy = Vut – Vlt
R1
= [+Vsat – (-Vsat)]
R1 R 2
10 K
= [26V] Since Vsat = 13V
110 K
= 0.0909 [26V]
Vhy = 2.363V
35
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PROCEDURE:
1. Design the value of circuit components and select VUT & VLT as given in the
design procedure.
2. Connect the circuit as shown in the circuit diagram.
3. Apply the input signal to the input terminal of op-amp & set VUT & VLT
values.
4. Note down the readings from the output waveform.
5. Plot the graph & show the relationship between Input sine wave & Output
square wave.
RESULT:
Thus an Astable, Monostable multivibrator and Schmitt trigger are
designed and tested using op-amp IC 741.
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RC PHASE SHIFT OSCILLATOR:-
CIRCUIT DIAGRAM:-
Rf=1MΩ
+15v
R1=33K 2 - 7
IC 741
+ 6
3 4
R1//Rf
33K -15v
+
CRO
C=0.1μf C=0.1μf0 C=0.1μf
-
TABULATION:.
MODEL GRAPH:
Vout
37
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EXP.NO: 06 DATE:
AIM:
To design RC Phase Shift and Wien Bridge Oscillator using op-amp IC
741 and to test its performance.
APPARATUS REQUIRED:
THEORY:
RC phase shift oscillator produces 360° of phase shift in two parts. Firstly,
each and every RC pair in the feedback network produces 60° phase shift and totally
there were three pairs, thus producing 180° Phase shift and secondly, the feedback
input is given to the inverting terminal of op-amp to produce another 180° phase shift
and a total phase shift of 360°.
The frequency of oscillation is given by f0 = 1 ; If an inverting
2 6 RC
amplifier is used, the gain must be atleast equal to 29 to ensure the oscillations with
constant amplitude that is, AV < 1. Otherwise the oscillation will die out.
DESIGN PROCEDURE:
Design a RC phase shift oscillator to oscillate at 200Hz.
1. Select fo = 200Hz.
2. Assume C = 0.1μf & determine R from fo.
1 1
fo = =R= = 3.3K.
2 6 RC 2 6 f oc
3. To prevent the loading of amp because it is necessary that R1>>10R.
Therefore R1=10R=33K.
4. At this frequency the gain must be atleast 29 (i.e)Rf / R1 =29.
Therefore Rf = 29R1.
Rf = 29 (33K) = 957KΩ.
Therefore use Rf = 1MΩ.
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R1=10K Rf=22K
+15v
2 - 7
IC 741
3 + 4
6
R=1.5K C=0.1uf
-15v +
CRO
R=1.5K -
C=0.1uf
TABULATION:
MODEL GRAPH:
Vout
39
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(i)
Select frequency f0 = 1KHz.
1
(ii) Use f0 = , A = 1+(Rf / R1) = 3. To find R & Rf.
2 RC
(iii) Therefore Rf = 2R1 & assume C = 0.1μf & find R from
1
R= = 1.59KΩ.
2 f oC
(iv) Assume R1 = 10K & find Rf from Rf = 2R1
Therefore Rf = 20K ≡ 22KΩ
PROCEDURE:
1. Select the given frequency of oscillation f0 = 1 KHz.
1
2. Assume either R or C to find out the other using formula . Also
2 RC
determine the value of other components as given in design procedure.
3. Connect the circuit as per as the circuit diagram.
4. Measure the amplitude and frequency of the output signal to plot the graph.
RESULT:
Thus RC Phase Shift and Wien Bridge Oscillator were designed and
tested using op-amp IC 741.
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PIN CONFIGURATION OF 555 TIMER IC
Applications:-
1. Monostable and Astable Multivibrator
2. dc-ac converters
3. Digital logic probes
4. Waveform generators
5. Analog frequency meters
6. Tachometers
7. Temperature measurement and control
8. Infrared transmitters
9. Regulator & Taxi gas alarms etc.
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6.8K +5V HI
RA
3.3K 7 8 4 3
RB IC 555
5
6 2 1 +
CRO Vo
-
Vc C=0.1μf 0.01uf
TABULATION:
Output
waveform
Capacitor
waveform
(Capacitor
voltage Vc)
43
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APPARATUS REQUIRED:
THEORY:
When the power supply VCC is connected, the external timing capacitor „C”
charges towards VCC with a time constant (RA+RB) C. During this time, pin 3 is high
(≈VCC) as Reset R=0, Set S=1 and this combination makes Q = 0 which has
unclamped the timing capacitor „C‟.
When the capacitor voltage equals 2/3 VCC, the upper comparator triggers the
control flip flop on that Q =1. It makes Q1 ON and capacitor „C‟ starts discharging
towards ground through RB and transistor Q1 with a time constant RBC. Current also
flows into Q1 through RA. Resistors RA and RB must be large enough to limit this
current and prevent damage to the discharge transistor Q1. The minimum value of R A
is approximately equal to VCC/0.2 where 0.2A is the maximum current through the
ON transistor Q1.
During the discharge of the timing capacitor C, as it reaches VCC/3, the lower
comparator is triggered and at this stage S=1, R=0 which turns Q =0. Now Q =0
unclamps the external timing capacitor C. The capacitor C is thus periodically
charged and discharged between 2/3 VCC and 1/3 VCC respectively. The length of
time that the output remains HIGH is the time for the capacitor to charge from 1/3
VCC to 2/3 VCC.
The capacitor voltage for a low pass RC circuit subjected to a step input of VCC
volts is given by VC = VCC [1- exp (-t/RC)]
Total time period T = 0.69 (RA + 2 RB) C
f = 1/T = 1.44/ (RA + 2RB) C
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MODEL GRAPH:
45
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DESIGN PROCEDURE:-
Design of Astable multivibrator of operation frequency = 1 KHz & duty cycle of 30%
using 555 timer IC.
Given Frequency=1000Hz
Duty cycle=30%
D= T low/T high = RB/RA+2RB*100 -----------------------------------(1)
T high =0.69(RA+RB)C
T low = 0.69 RBC
From equation 1
0.30 T high = T low
0.30 * 0.69(RA+RB)C = 0.69 RBC
0.201(RA+RB)C = 0.69 RBC
0.483 RB-0.207 RA= 0 -----------------------------------------------(2)
given f=1khz we know that T=1/f
T=1ms
T= T high + T low
0.69(RA+RB)C +0.69 RBC= 1ms.
0.69(RA+RB) +0.69 RB = 1ms./C
Let C=0.1μF
0.69RA+0.69RB +0.69 RB = 1ms./0.1*10-6
0.69RA+1.38RB = 10 4 ------------------------------------------------(3)
Procedure:
1. Calculate the component values using the design procedure.
2. Connect the circuit as shown in the circuit diagram.
3. Observe and note down the output waveform.
4. Measure the frequency of oscillations and duty cycle and then compare with
the given values.
5. Plot both the waveforms to the same time scale in a graph.
46
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MONOSATBLE MULTIVIBRATOR:-
CIRCUIT DIAGRAM:-
HI
+5V
10K
7 8 4 3
IC 555
5
6 2 1 +
0.1uf CRO Vo
Vc
Trigger -
Input
0.01uf
Vin
TABULATION:
1. Input waveform
2. Output waveform
Capacitive waveform
3.
(Capacitor voltage Vc)
MODEL GRAPH:
47
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THEORY- (MONOSATBLE):-
A Monostable Multivibrator, often called a one-shot Multivibrator, is a pulse-
generating circuit in which the duration of the pulse is determined by the RC network
connected externally to the 555 timer. In a stable or stand by mode the output of the
circuit is approximately Zero or at logic-low level. When an external trigger pulse is
given, the output is forced to go high ( VCC). The time for which the output remains
high is determined by the external RC network connected to the timer. At the end of
the timing interval, the output automatically reverts back to its logic-low stable state.
The output stays low until the trigger pulse is again applied. Then the cycle repeats.
The Monostable circuit has only one stable state (output low), hence the name
Monostable. Normally the output of the Monostable Multivibrator is low.
DESIGN PROCEDURE:-
Let, RA = 10K
Out put pulse width tp = 10μs
tp=1.1RAC
C= 0.909μF
C=0.1μF
PROCEDURE:-
1. Calculate the value of R & C using design procedure.
2. Connect the circuit as shown in the circuit diagram.
3. Apply Negative triggering pulses at pin 2 of frequency 1 KHz.
4. Observe the output waveform and measure the pulse duration.
5. Theoretically calculate the pulse duration as Thigh=1.1 RAC
RESULT:
Thus the Astable and Monostable multivibrator is designed and tested using
555 timer IC
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Pin Configuration:
Specifications:
1. Operating frequency range : 0.001 Hz to 500 KHz
2. Operating voltage range : ±6 to ±12V
3. Inputs level required for tracking : 10mV rms minimum to 3v (p-p)
max.
4. Input impedance : 10 KΩ typically
5. Output sink current : 1mA typically
6. Drift in VCO center frequency : 300 PPM/oC typically
(fout) with temperature
7. Drif in VCO centre frequency with : 1.5%/V maximum
supply voltage
8. Triangle wave amplitude : typically 2.4 VPP at ± 6V
9. Square wave amplitude : typically 5.4 VPP at ± 6V
10. Output source current : 10mA typically
11. Bandwidth adjustment range : <±1 to >± 60%
Center frequency fout = 1.2/4R1C1 Hz
= free running frequency
FL = ± 8 fout/V Hz
V = (+V) – (-V)
fL 1/ 2
fc = ±
2 (3.6) x10 3 xC 2
Applications:
1. Frequency multiplier
2. Frequency shift keying (FSK) demodulator
3. FM detector
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PLL IC 565
THEORY:-
The Signetics SE/NE 560 series is monolithic phase locked loops. The SE/NE
560, 561, 562, 564, 565, & 567 differ mainly in operating frequency range, power
supply requirements and frequency and bandwidth adjustment ranges. The device is
available as 14 Pin DIP package and as 10-pin metal can package. Phase comparator
or phase detector compare the frequency of input signal fs with frequency of VCO
output fo and it generates a signal which is function of difference between the phase of
input signal and phase of feedback signal which is basically a d.c voltage mixed with
high frequency noise. LPF remove high frequency noise voltage. Output is error
voltage. If control voltage of VCO is 0, then frequency is center frequency (f o) and
mode is free running mode. Application of control voltage shifts the output frequency
of VCO from fo to f. On application of error voltage, difference between fs & f tends
to decrease and VCO is said to be locked. While in locked condition, the PLL tracks
the changes of frequency of input signal.
PROCEDURE:
1. Determine the component values using the design procedure given here.
2. Connect the components as shown in the circuit diagram.
3. Note down the readings of output waveform with respect to input signal.
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CIRCUIT DIAGRAM:
DESIGN PROCEDURE:-
If C= 0.01μF and the frequency of input trigger signal is 2KHz, output pulse
width of 555 in Monostable mode is given by
1.1RAC = 1.2T =1.2/f
RA= 1.2/(1.1Cf)=54.5KΩ
fIN=fOUT/N
Under locked conditions,
fOUT = NfIN = 2fIN = 4KHz
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EXP.NO: 08 DATE:
AIM:
To design & test the characteristics of PLL and to construct and test frequency
multiplier using PLL IC565.
APPARATUS REQUIRED:
0.01μF 4
CAPACITORS
4
0.1 μf, 10μf, 1 μf EACH 01
52
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(a): Input
(b): PLL output under locked conditions without 555
(c): Output at pin4 of 565 with 555 connected in the feedback
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Theory:
The frequency divider is inserted between the VCO and the phase
comparator of PLL. Since the output of the divider is locked to the input frequency
fIN, the VCO is actually running at a multiple of the input frequency .The desired
amount of multiplication can be obtained by selecting a proper divide– by – N
network ,where N is an integer. To obtain the output frequency fOUT=2fIN, N = 2 is
chosen. One must determine the input frequency range and then adjust the free
running frequency fOUT of the VCO by means of R1 and C1 so that the output
frequency of the divider is midway within the predetermined input frequency range.
The output of the VCO now should be 2fIN . The output of the VCO should be
adjusted by varying potentiometer R1. A small capacitor is connected between pin7
and pin8 to eliminate possible oscillations. Also, capacitor C2 should be large enough
to stabilize the VCO frequency.
SAMPLE READINGS:
Amplitude (Vp-p)
Frequency (KHz)
PROCEDURE:-
1. The circuit is connected as per the circuit diagram.
2. Apply a square wave input to the pin2 of the 565
3. Observe the output at pin4 of 565 under locked condition.
4. Give the output of 565 to the pin2 of 555 IC.
5. Observe the output of 555 at pin3.
6. Now give the output of 555 as feedback to the pin5 of the 565.
7. Observe the frequency of output signal fo at pin4 of 565 IC.
8. Plot the waveforms in graph.
RESULT:
Thus the PLL characteristics are designed and tested and Frequency multiplier
using IC 565 is constructed and tested.
54
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PIN DIAGRAM:
Vin (0-30) V
HI
Vref=5V HI
12 11
R4=100E
6 10 Vo
R1=1K
IC 723 2
5
R2=3.3K 3
R3=30E
7
13 4
C=220pf
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EXP.NO: 09 DATE:
AIM:
To design and test the power supply voltage regulator using LM317 and
LM723
APPARATUS REQUIRED:
THEORY:
A voltage regulator is a circuit that supplies a constant voltage regardless of
changes in load current and input voltage variations. Using IC 723, we can design
both low voltage and high voltage regulators with adjustable voltages.
For a low voltage regulator, the output VO can be varied in the range of
voltages Vo < Vref, where as for high voltage regulator, it is VO > Vref. The voltage
Vref is generally about 7.5V. Although voltage regulators can be designed using Op-
amps, it is quicker and easier to use IC voltage Regulators.
IC 723 is a general purpose regulator and is a 14-pin IC with internal short
circuit current limiting, thermal shutdown, current/voltage boosting etc. Furthermore
it is an adjustable voltage regulator which can be varied over both positive and
negative voltage ranges. By simply varying the connections made externally, we can
operate the IC in the required mode of operation. Typical performance parameters are
line and load regulations which determine the precise characteristics of a regulator
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TABULATION:
1.
2.
3.
4.
5.
6.
7.
8.
MODEL GRAPH:
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PIN DIAGRAM:
MODEL GRAPH:
59
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TABULATION:
PROCEDURE:
1) Connections are made as per the circuit diagram.
2) The reference voltage of 5v is set and the input voltage is varied between (0-30) v
3) The corresponding output is taken using voltmeter.
4) The readings are tabulated and the graph is plotted.
RESULT:
The 723 & 317 voltage regulators are designed and the regulation of supply voltage
was tested.
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PIN DETAILS:
TECHNICAL INFROMATION:
TEMPERATURE
DESCRIPTION
RANGE
SG3524N(16-pin plastic DIP) 0 C to 70 C
SG3524F(16-pin cerdip) 0 C to 70 C
SG3524D(16-pin SO) 0 C to 70 C
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STUDY OF SMPS
EXP.NO: 10 DATE:
AIM:
To study the control of SMPS
THEORY:
The switching regulator is also called as switched mode regulator. In
this case, the pass transistor is used as a controlled switch and is operated at either
cutoff or saturated state. Hence the power transmitted across the pass device is in
discrete pulses rather than as a steady current flow. Greater efficiency is achieved
since the pass device is operated as a low impedance switch. When the pass device is
at cutoff, there is no current and dissipated power. Again when the pass device is in
saturation, a negligible voltage drop appears across it and thus dissipates only a small
amount of average power, providing maximum current to the load. The efficiency is
switched mode power supply is in the range of 70-90%.
A switching power supply is shown in figure. The bridge rectifier and
capacitor filters are connected directly to the ac line to give unregulated dc input. The
reference regulator is a series pass regulator. Its output serves as a power supply
voltage for all other circuits. The transistors Q1, Q2 are alternatively switched „on‟ &;
off, these transistors are either fully „on‟ or „cut-off, so they dissipate very little
power. These transistors drive the primary of the main transformer. The secondary is
centre tapped and full wave rectification is achieved by diodes D1 and D2. This
unidirectional square wave is next filtered through a two stage LC filter to produce
output voltage Vo.
SG 3524:
FUNCTION:
Switched Mode Power Supply Control Circuit
FEATURES:
Complete PWM Power Controlled circuitry.
Single ended or push-pull outputs.
Line and Load regulation of 0.2%.
1% maximum temperature variation.
Total Supply current is less than 10mA
Operation beyond 100KHz
RESULT:
Thus the control of SMPS IC SG3524 had been studied.
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Instrumentation Amplifier:
63
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Program:
.LIB EVAL.LIB
VCC1 4 0 DC 15
VEE1 0 5 DC 15
VCC2 9 0 DC 15
VEE2 0 10 DC 15
VCC3 14 0 DC 15
VEE3 0 15 DC 15
V1 7 0 SIN(0 5V 100)
V2 1 0 SIN(0 3V 100)
R1 3 2 1K
R2 8 6 1K
R3 2 6 500
R4 3 11 1K
R5 8 12 1K
RF 11 13 1K
R6 12 0 1K
X1 1 2 4 5 3 UA741
X2 7 6 9 10 8 UA741
X3 12 11 14 15 13 UA741
.TRAN 0 20MS
.OP
.PROBE
.END
64
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Lowpass Filter:
65
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Program:
.LIB EVAL.LIB
VCC 5 0 DC 15
VEE 0 6 DC 15
VIN 2 0 AC 4
R1 1 0 22K
R2 1 4 22K
R3 2 3 1.5K
RL 4 0 10K
C1 3 0 0.1U
X1 3 1 5 6 4 UA741
.AC DEC 10 10 1MEG
.OP
.PROBE
.END
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Highpass Filter:
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Program:
.LIB EVAL.LIB
VCC 5 0 DC 15
VEE 0 6 DC 15
VIN 2 0 AC 4
R1 1 0 22K
R2 1 4 22K
C1 2 3 0.1U
RL 4 0 10K
R3 3 0 1.5K
X1 3 1 5 6 4 UA741
.AC DEC 10 10 100K
.OP
.PROBE
.END
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Active Bandpass Filter:
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Program:
.LIB EVAL.LIB
VCC 5 0 DC 15
VEE 0 6 DC 15
VCC110 0 DC 15
VEE1 0 11 DC 15
VIN 2 0 AC 4
R1 1 0 22K
R2 1 4 22K
R3 3 0 1.5K
R4 4 7 1.5K
R5 8 0 22K
R6 8 9 22K
RL 9 0 10K
C1 2 3 0.1U
C2 7 0 0.01U
X1 3 1 5 6 4 UA741
X2 7 8 10 11 9 UA741
.AC DEC 10 10 10MEG
.OP
.PROBE
.END
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Astable Multivibrator:
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Program:
.LIB EVAL.LIB
VCC 4 0 DC 15
VEE 0 5 DC 15
R1 2 0 10K
R2 2 3 11.6K
R3 1 3 50K
C1 1 0 0.01U
X1 2 1 4 5 3 UA741
.TRAN 0 5MS UIC
.OP
.PROBE
.END
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Monostable Multivibrator:
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Program:
.LIB EVAL.LIB
VCC 6 0 DC 15
VEE 0 7 DC 15
VIN 4 0 PULSE(4 0 1MS 0.001MS 0.001MS 1MS 2MS)
R1 5 2 10K
R2 2 0 10K
R3 1 5 50K
R4 3 0 100
C1 4 3 0.1U
C2 0 1 0.1U
D1 1 0 D1N4148
D2 2 3 D1N4148
X1 2 1 6 7 5 UA741
.TRAN 0 20MS
.OP
.PROBE
.END
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Schmitt Trigger:
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Program:
.LIB.EVAL.LIB
VCC 5 0 DC 15
VEE 0 6 DC 15
VIN 1 0 SIN(0 4 100)
R1 3 0 10K
R2 3 4 100K
R3 1 2 10K
RL 4 0 10K
X1 3 2 5 6 4 UA741
.TRAN 0 30MS
.OP
.PROBE
.END
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RC Phase shift Oscillator:
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Program:
.LIB EVAL.LIB
VCC 7 0 DC 15
VEE 0 8 DC 15
IS 3 0 PWL(0US 0MA 10US 0.1MA 40US 0.1MA
50US 0MA 10MS 0MA)
R1 1 2 33K
R2 2 4 1.02MEG
R3 5 0 3.3K
R4 6 0 3.3K
R5 1 0 3.3K
R6 3 0 33K
C1 5 4 0.1U
C2 6 5 0.1U
C3 1 6 0.1U
X1 3 2 7 8 4 UA741
.TRAN 0 1
.OP
.PROBE
.END
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Wein Bridge Oscillator:
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Program:
.LIB EVAL.LIB
VCC 5 0 DC 15
VEE 0 6 DC 15
IS 2 0 PWL(0US 0MA 10US 0.1MA 40US 0.1MA
50US 0MA 10MS 0MA)
R1 1 0 15K
R2 1 4 30.2K
R3 2 3 1.5K
R4 2 0 1.5K
C1 3 4 0.1U
C2 2 0 0.1U
X1 2 1 5 6 4 UA741
.TRAN 0 1
.OP
.PROBE
.END
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ADDITIONAL EXPERIMENTS
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CIRCUIT DIAGRAM:
Rf=2R
+15v
R R R 2 7
-
IC 741
6
3 + 4
-15v
2R 2R 2R 2R 2R
-
V (0-10)V
+
b0 b1 b2 b3
INPUT - SWITCH
(ON-1 & OFF-0)
TABULATION:
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
.. .. .. .. ..
.. .. .. .. ..
.. .. .. .. ..
.. .. .. .. ..
.. .. .. .. ..
.. .. .. .. ..
.. .. .. .. ..
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
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EXP.NO: 12 DATE:
AIM:
To design and test the operation of a 4 bit R – 2R ladder type digital to analog
converter using op-amp IC 741.
APPARATUS REQUIRED:
THEORY:
Most DACs architectures are based on the popular R-2R ladder. Starting from
the left hand side of the circuit to the right hand side, one can easily prove that the
equivalent resistance to the right of each labeled node equals 2R. Consequently, the
current flowing downward, away from each node equal to the current flowing toward
the right; twice this current enters the node from the left. The currents and, hence, the
node voltages are binary weighted.
They are Current mode DAC and Voltage mode DAC based on whether the
circuit operated on current or voltage respectively. The major advantage of R-2R
ladder architecture when compared with the binary weighted type is the use of only
two value resistors. These two values R and 2R make the design simple for any
resolution and thus easily realizable as an integrated circuit.
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MODEL GRAPH:
0 1 0 1 1 0 1
0 0 1 1 0 1 1
0 0 0 0 1 1 1
0 0 0 0 1 1 1 Binary I/P
O/P VOLTAGE
(V)
DESIGN PROCEDURE:
1. Assume any value of R & find 2R.
2. Let R = 10KΩ; therefore 2R = 20KΩ ≡ 22KΩ.
3. Let Rf = 2R = 22KΩ.
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PROCEDURE:
2. Assume the value of Resistor R and thus select another resistor with twice a value
of the first resistor (2R).
3. Connect the circuit as shown in the circuit diagram. Connect the series resistances
R finally to the inverting terminal of the op-amp.
4. Connect the other end of the parallel arm resistors 2R to the digital switch to
represent binary logic conditions.
5. Calculate the output voltage from the voltmeter. Since negative output results from
op-amp connect the output of op-amp to the negative terminal of the voltmeter, to
get Positive deflections.
6. Plot the graph for output voltage versus input binary combinations.
RESULT:
Thus the R – 2R ladder type digital to analog converter is designed & tested
using op-amp IC 741.
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SAMPLE VIVA-VOCE QUESTIONS AND ANSWERS
EXPT NO.1:
INVERTING, NON-INVERTING AND DIFFERENTIAL
AMPLIFIERS USING OP-AMP
10. What is the maximum voltage that can be given at the inputs?
Ans: The inputs must be given in such a way that the output should be less than Vsat.
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17. List all Specifications of op-amp 741
Ans:
1. Voltage gain A = α typically 2,00,000
2. I/P resistance RL = α Ω, practically 2MΩ
3. O/P resistance R =0, practically 75Ω
4. Bandwidth = α Hz. It can be operated at any frequency
5. Common mode rejection ratio = α
(Ability of op amp to reject noise voltage)
6. Slew rate + α V/μsec
(Rate of change of O/P voltage)
7. When V1 = V2, VD=0
8. Input offset voltage (Rs ≤ 10KΩ) max 6 mv
9. Input offset current = max 200nA
10. Input bias current : 500nA
11. Input capacitance : typical value 1.4pF
12. Offset voltage adjustment range : ± 15mV
13. Input voltage range : ± 13V
14. Supply voltage rejection ratio : 150 μV/V
15. Output voltage swing: + 13V and – 13V for RL > 2KΩ
16. Output short-circuit current: 25mA
17. supply current: 28mA
18. Power consumption: 85mW
19. Transient response: rise time= 0.3 μs
19. What is the maximum voltage that can be given at the inputs?
Ans: The inputs must be given in such a way that the output should be less than Vsat.
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EXPT NO: 2
INTEGRATOR AND DIFFERENTIATOR USING OP-AMP.
1. Express the output voltage of an Integrator.
Ans: The expression for the output voltage of an op-amp integrator is given as
t
1
Vo = - Vin dt + C
R1Cf 0
Where R1 Input Resistance
Cf Feedback Capacitance
Vin Input Voltage and
C Constant
4. What are the problems faced by basic ideal integrator and how can we
overcome ?
Ans: The input offset voltage Vio and the part of input current charging the
feedback capacitor Cf produces the error voltage at the output of the ideal integrator.
Therefore, in practical integrator, to reduce the error voltage at the output, a resistor
Rf is connected in parallel to Cf. This Rf, limits the low-frequency gain and hence
minimizes the variations in the output voltage. Both stability and the roll-off problems
in basic ideal integrator can be corrected by additional resistor Rf.
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13. How ideal differentiator suffers from instability? How can we overcome
them?
Ans: The ideal or basic differentiator‟s circuit gain (Rf/R1) increases with
increase in frequency at a rate of +20dB/decade. This makes the circuit unstable.
Also, the impedance Xc1 decreases with increase in frequency, which makes the
circuit very susceptible to high frequency noise. When amplified, this noise can
completely override the differentiated output signal. Both stability and high frequency
noise can be corrected by addition of two components R1 and Cf. This circuit is called
as practical differentiator.
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17. Determine the output of differentiator for the following input waves.
Ans: The inputs and respective output waveform of differentiator are as follows,
Sine Wave Negative Cosine Wave
Cosine Wave Sine Wave
Square Wave Spike Wave
Sawtooth Wave Square Wave
X- - - - - X - - - - - X
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EXPT NO: 3
INSTRUMENTATION AMPLIFIER
1. What are the important requirements of an instrumentation Amplifier?
Ans: The requirements of an instrumentation amplifier are low noise, low
thermal and time drifts, high input impedance, accurate closed-loop gain, high CMRR
and high Slew Rate.
Flying-Capacitor IA :
Excellent CMRR, as common mode signals are completely ignored.
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6. Define CMRR of instrumentation Amplifier.
Ans: CMRR of instrumentation amplifier is defined as ratio of differential mode
gain to common-mode gain.
Ad
CMRR (dB) = 20 log │ │
Ac
The Differential mode gain is preferred than common mode gain. Common
mode gain indicates the gain of op-amp when common mode noise signals are
present.
Gain of II stage:
Differential output stage
R2
Vo = ( Vo2 – Vo1)
R1
Where Vo2 – Vo1 the differential input to second stage
R2 feedback resistor of op-amp 3
R1 Input resistor of op-amp3
Overall Gain :
Vo = A(V2 – V1)
R3 R2
Where A = AI x AII = (1+2 )x( )
RG R1
9. Give some examples of a monolithic IAs.
Ans: Examples of IC Instrumentation Amplifiers from Analog Devices
AD 521/522/524/624/625
AMP - 01
AMP – 02
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EXPT NO.4 :
ACTIVE FILTER (LP, HP & BP) USING OP-AMP 741
2. Why active filters are not suitable for high frequency applications?
Ans: Above MHZ range the op-amp open-loop gain rolls-off with increase in
frequency.
7. Does a filter affect both amplitude and phase of the input signal?
Ans: Yes.
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ACL(HPF) =
Vo
Vin
= Af ( 1 j(jf( f/ /fl)fl) )
│ ACL │ = Af (f/fl) / √1+ (f/fl)2 ; Ø = tan -1(f/fl)
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EXPT NO.5:
ASTABLE, MONOSTABLE MULTIVIBRATOR AND
SCHMITT TRIGGER USING OP-AMP
1. Define multivibrator.
Ans: A multivibrator is an oscillatory circuit capable of generating waveforms
without any Specific input signal. The circuit only has supply voltage connections,
from which the two amplifiers saturates one another to generate vibrations.
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12. Give the expression for the upper and lower threshold points of Schmitt
trigger.
Ans: The expression for upper threshold point and lower threshold point are as
follows
R1
Upper threshold voltage VUT = (+Vsat)
R1 R 2
R1
Lower threshold voltage VLT = (-Vsat)
R1 R 2
13. Write the truth table of a comparator.
Ans: Truth table of a Comparator
When V+ > V- +Vsat
When V+ < V- - Vsat
When V+ = V- High Impedance State
15. What happens when both threshold points in a Schmitt trigger is equal to
zero?
Ans: When VUT = VLT = 0, the Schmitt trigger behaves as a zero crossing
detector. There were two types of Schmitt trigger. They are positive and negative
Schmitt trigger.
16. Can a Schmitt trigger can be operated with single supply & single threshold
voltage?
Ans: Schmitt trigger can also be operated with single power supply or with a
single triggering input (Either Positive or Negative)
X - - - - - - X - - - - -X
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EXPT NO.6:
RC PHASE SHIFT AND WIEN BRIDGE OSCILLATOR
USING OP-AMP 741
1. State Barkhausen Criterion and its significance.
Ans: Barkhausen Criterion for oscillation gives the conditions for an oscillator
to oscillate.
i) AVβ ≤ 1; the product of forward gain AV and the feedback ratio β
must satisfy this condition.
ii) The total phase shift of AVβ must be 0° or 360°
3. How oscillations are created in RC phase shift and wien Bridge oscillator?
Ans: When the bridge is balanced and the overall phase attained is 0°, the
Wien bridge oscillator produces oscillations. RC phase shift oscillator produces 360°
of phase shift in two parts. Firstly, each and every RC pair in the feedback network
produces 60° phase shift and a totally there were three pairs, thus producing 180°
Phase shift and secondly, the feedback input is given to the inverting terminal of op-
amp to produce another 180° phase shift and a total phase shift of 360°.
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EXPT NO.7:
ASTABLE AND MONOSTABLE MODE OF IC 555 TIMER
3. What are the different types of packages available for 555 Timer IC?
Ans: The packages used for 555 Timer are 8-pin mini Dual-Inline-Package
(DIP) and 8-pin Metal Can.
4. List some applications of 555 timers in both Astable mode and Monostable
Mode.
Ans: In Astable mode of operation, some of the applications of 555 Timer
were: Tone- burst oscillator, Voltage controlled frequency shifter, square wave
generator etc., In Monostable or one-shot mode, some of the applications of 555 timer
were: Water-level fill control, Touch switch, Frequency divider, missing pulse
detector and many more.
6. Express the free running frequency of oscillation and total period of Astable
mode of 555 timer.
Ans: The free running frequency of oscillation is given as
1 1.44
f= = and thus the total period of oscillation T is
T ( Ra 2 Rb)C
T = 0.695 (Ra+2Rb)C
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EXPT. NO: 8
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PLL IC 565 AND FREQUENCY MULTIPLIER USING PLL 565
1. What is a PLL?
A PLL is a Phase Locked Loop Circuit used to track any changes in the input
frequency.
7. What happens when the two input signals given to PLL is having same
frequency or same phase?
When both the inputs are same, the PLL will start functioning in the
Lock mode and if once lock has been occurred, the PLL will start tracking the
Phase or frequency changes in the input signal.
8. What is VCO?
VCO is the integral part of PLL. A VCO is the Voltage Controlled
Oscillator. As the name implies it generates oscillations according to the input
voltage. This VCO is placed in the feedback path of a PLL. The output of the
VCO is changing according to the Error output voltage from the error
amplifier placed finally in the forward path.
X - - - - - - X - - - - -X
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EXPT NO.12
DIGITAL TO ANALOG CONVERTER USING OP-AMP 741
1. Mention Some Important DAC characteristics.
Ans: Resolution, Full-scale output Voltage, Offset error, Gain error,
Monotonocity and Relative accuracy.
6. What are the merits and demerits of different types of DAC conversion
techniques?
Ans: The binary weighted is the simplest DAC technique. But this technique
suffers from the fact that if, number of binary inputs was more, then the Value of
resistor also increases and becomes difficult to be implemented inside a IC.
The R-2R ladder network eliminates the above said disadvantage, since it uses
only two values of resistance R and 2R irrespective of number of binary inputs.
Ratioed emitter current is the disadvantage of this type.
The inverted ladder type eliminates the above said disadvantage by performing
voltage ratio rather than current ratio.
Current driven DAC is mainly used when there is a base errors. This type is
mainly used to compensate base losses of a bipolar DACs.
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