BiTEC Ltd

DSP Solutions for

Research & Industry

DSKcam
Users manual

Version 3.1

 BiTEC Ltd 2005

Page 2

Revision history 4

Introduction...............................................................................5

Features ................................................................................5

Applications ............................................................................6

Requirements ..........................................................................7

Hardware Installation ................................................................8

Software Installation ............................................................... 10

Example Software ..................................................................... 11

H263 streaming example .......................................................... 11

Streaming over the RS-232 interface ......................................... 11

Streaming over TCP/IP on Ethernet........................................... 11

Web server example................................................................ 12

Basic example ....................................................................... 13

UART example ....................................................................... 13

Compatibility ........................................................................... 13

Support .................................................................................. 13

Camera .................................................................................. 14

Frame grabber.......................................................................... 14

FIFO CPLD ............................................................................ 15

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Interrupt Control Register (ICR) ............................................... 15

I2C Control Register (I2CR) ..................................................... 16

FIFO Control Register (FCR) .................................................... 16

CPLD Version Register (CVER).................................................. 17

Memory timing requirements ..................................................... 18

TCP/IP Ethernet adaptor ............................................................. 18

Wireless LAN interface (option) ..................................................... 18

High-speed serial port ................................................................ 19

Software ................................................................................. 20

Frame grabbing...................................................................... 21

Triple Frame Buffering ............................................................. 21

Application program interfaces ..................................................... 23

DSKcam API........................................................................... 23

W3100A API........................................................................... 24

Appendix A: Memory Map............................................................. 28

Appendix B: Interrupt channels ..................................................... 29

Appendix C: Schematics .............................................................. 30

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Revision history
Version Comment

V1.1 First release

Updated to support extended DSK

V2.1
platforms

V2.2 Updated to include Ethernet adaptor

V2.3 Included web server example

V3.0 Updated for V3 DSKcam

V3.1 Updated for Wireless LAN

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Introduction
Care has been taken during the development of DSKcam to ensure end users can
start using their system with minimal effort. This manual describes the
functionality of the DSKcam and introduces the sample software shipped with
the unit.

Features
The DSKcam provides users with a complete, Smart Camera system bringing
together real-time, high performance DSP with image capture capabilities. Also,
by employing the integrated digital and analogue I/O included on the DSKs,
stand-alone PLC type systems can be developed and prototyped. The DSKcam
provides the following features,

VGA Colour resolution, CMOS Sensor camera delivering up to 30fps.

Raw RGB and YUV422 digital image output at VGA and QVGA resolution

6Mbit Video Frame buffer.

Embedded TCP/IP Ethernet module based on the WizNET W3100A device.

16C550 UART with 9-way, D-type, RS232 compatible output giving up to

1Mbps maximum transfer rate.

Example frame grabbing routines supplied.

UART compatible with TI, IOM mini driver for PIP and SIO support.

Fully compatible with the TI Image Processing Library for high

performance processing.

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Applications
Real-time video image processing is becoming more and more popular and
constantly finding new, exciting applications. Typical applications for a DSKcam
system are,

Machine vision

Video phone

Remote image sensing

Surveillance systems

Image recognition, filtering and compression

Video streaming

Stand-alone vision systems

Net attached smart cameras

VOIP projects

A block diagram of the DSKcam is shown in Figure 1. The camera, frame buffer ,
serial port, Ethernet adaptor and CPLD are the subject of the remainder of this
manual.

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Frame Grabber

Wi-FI*

BUFFER Y
D[8..15]

FIFO Y

TCP/IP
CTRL

RJ45
BUFFER UV
FIFO UV

D[0..7]

UART
CTRL
RS232

CPLD
CTRL

CTRL
DSK Interface

Figure 1 DSKcam block diagram (* Wi-Fi module optional)

Requirements
The DSKcam requires a full installation of the CCS version 2.21 or above. It is also
necessary to install the Device Drivers Development Kit (DDK) that can be
downloaded from the TI Website. The DDK package contains the necessary base
routines for the UART mini-driver. The TI Image Library is required to run the
sample video streaming application which can also be downloaded from the TI
website. For the sample host application, (Video For Windows) VFW or
compatible is required if a re-build is necessary. This can be downloaded from
the Microsoft Website. All other software and documentation is shipped with the
DSKcam.

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Hardware Installation
The DSKcam is based on two separate PCBs. The main daughter card interfaces
directly onto DSK and the camera head inserts into the 32-way header. The
daughter card connectors are polarity sensitive preventing incorrect insertion.
The second card, the camera head, must be inserted into the 32-way header on
the daughter card taking care of orientation. The correct insertion is shown in
Figure 2 and Figure 3 below. There is the option of including a 90-degrees
adaptor giving more flexibility in the orientation of the installed system see
Figure 2 and Figure 3 below.

Figure 2 DSKcam installation in vertical Figure 3 DSKcam installation in horizontal

position position

Also, the camera module may be connected via a ribbon cable. As the camera
signals may run at 13Mhz, it is recommended that the ribbon cable length be
kept to a minimum.

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Camera
head
90 degree
adaptor

Serial port
DSKcam
daughter
card
TI DSK
motherboard

Figure 4 DSKcam interface schematic

Figure 5 shows the DSKcam in more detail. The differences for units fitted for Wi-
Fi operation is indicated.

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W 3100A W-LINK
TCP/IP Active
Eternet LED*

Camera
interfa ce
port
www.BiTEC.Ltd.uk

© Copyright BiTEC Ltd 2005

Serial port

DSKcam v3.0
D-TYPE

Ethernet
RJ-45 ** Composite
out
(PAL)

W ireless
module*

Ethernet W ireless
CPLD JTAG
indicator factory
CPLD Port
LEDs reset*

Figure 5 Board detail. * Fitted on Wireless LAN option. ** Fitted on Ethernet option.

Software Installation
The CD ROM shipped with the DSKcam contains a sample video streaming
application to demonstrate the capture and processing of images. The contents
of the CD ROM should be copied into the c:\ti\myprojects folder within the CCS
directory structure. The streaming application can be opened in the CCS IDE and
compiled and downloaded to a target DSK with the DSKcam correctly inserted.
The project build options assume the CCS is installed in C:\ti with the DDK
installed in c:\ti\ddk. Any non-standard installation will require changes to the
include files and library file locations in the project build options.

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Example Software

H263 streaming example

The DSKCam comes bundled with an example h263 video streaming example.
Only simple encoding is performed with no advanced motion compensation
features included. The application can stream via the RS-232 or the Ethernet
adaptor. Clearly a higher quality video stream is achievable via the Ethernet
adaptor. The host application is based on a modified Telenor encoder and the
source code is supplied. The application has been compiled using the Open
Watcom 1.2 compiler which can be downloaded from www.OpenWatcom.org,

Streaming over the RS-232 interface

After connecting-up the serial interface to a PC using a standard D-type to D-type

connection, the sample application found in the host_app directory can be run.
On the command line, the user must specify which com port is used and the
desired output file for which the yuv data is written. A typical command would
be …

C:>tmndec32 –o6 COM2: tmp.yuv

A fixed baud-rate of 115,200bps is used, as this is the maximum permissible on

most standard PCs.

Streaming over TCP/IP on Ethernet

Streaming over TCP/IP Ethernet requires correct connection between the

DSKcam and an Ethernet network. This can be done via a router or direct
connection to a PC Ethernet adaptor using a cross-over RJ45 cable. A default IP
address is used within the DSKcam of 192.168.11.33 which can be changed in the
routine InitNetConfig. This file also allows the user to change the MAC address

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used by the Ethernet adaptor should conflicts occur. The same host application
as with the serial interface is used with command line invocation …

C:>tmndec32 –o6 192.168.11.33 out.yuv

Clearly, the IP address should be changed to reflect that programmed in

InitNetConfig. It may be necessary to verify the connection should any problems
occur with the host application. One way is to 'ping' the DSKcam from the PC.
This can only be done once the Eternet adaptor is programmed with its MAC and
IP address and hence the routine InitNetConfig must be executed beforehand.

Web server example

The DSKcam is shipped with a simple web server example. The server is based on
example published by M. Tim Jones (An Embeddable Web Server on
http://www.ddjembedded.com/resources/articles/). The server contains a
simple file system designed to hold web pages. An application which converts the
raw html files can be found in the tools directory. The file system application,
buildfs.exe, must be given the compete path name for the correct file access via
a web browser. The resulting file system, filedata.c, must be copied over the
existing filedata.c in the common directory before building the server
application.

The web server can generate dynamic pages. A special tag in, <DATA myvar>,
inserted in the raw html is intercepted by the web server. In order to respond to
the myvar variable the routine addDynamicContent("myvar",
&myvarfunc); must be executed to associate the variable with the function
myvarfunc. An example of this is included in the webserver.

A sample webpage is provided which outputs a jpeg image from the camera. The
jpeg routine is not optimised and is for demonstration purposes only. When the
application is running, the page can be accessed using the link.
http://192.168.11.33/index.html This assumes the default IP address is used.

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Basic example
A basic skeleton routine is provided with the DSKcam. This routine is designed as
a basis for developing a video processing application. All the necessary
commands for initialisation of the UART, camera and TCP interface are provided.
The user may run the example and then break execution to see the captured
image. Viewing the image can be done using the CCS graph viewing feature.
Details of how to do this are given in the file main.c

UART example
Use of the UART is demonstrated using the UART example. As the UART is
accessed using the TI, IOM mini driver the example is taken from the TI DDK
package. Please refer to the documentation in the DDK installation.

Compatibility
The DSKcam has been designed to run on the C6416DSK, C6711DSK, C6211DSK,
C6713DSK, C5510DSK and C5416DSK. Minor code changes may be necessary
according to which DSP family is used due to differences in the underlying
architecture. The DSKcam is also compatible with the ALTERA Startix II DSP
Development System. See www.altera.com for more details.

Support
Support for hardware and software issues relating to the DSKcam can be directed
to support@BiTEC.Ltd.uk. Other DSKcam users may gain from any comments and
suggestions on the USENET groups. Relevant groups for DSKcam are
news://comp.dsp and news://sci.image.processing. Software and documentation
updates are posted on http://www.BiTEC.Ltd.uk.

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Camera
The camera used in the DSKcam is based on the Omnivision OV7620 CMOS sensor.
With 124 registers, a full description of the device is beyond the scope of this
manual. The reader is referred to the OV7620 datasheet available on the
Omnivision website and may also be found on the DSKcam CDROM. Example
software is provided showing a typical programming arrangement ideal for
getting started. As the OV7620 has enjoyed a great popularity with OEM
manufactures, there is a wealth of information and programming tips on the
Internet. For more insight in to possible programming, the reader is referred to
the Linux, webcam community and in particular the OV511+, Linux driver
sources.

Access to the camera registers is via a serial i2c interface. Rather than installing
an i2c interface on the DSKcam, the functionality of i2c is implemented by ‘bit-
banging’ fields in the I2C, CPLD register (see below). As frequent programming
of the camera is not necessary, a bit-banging approach is more than adequate for
the DSKcam. Routines are provided on the CDROM for reading and writing to the
i2c interface.

By appropriate register programming, the camera can generate VGA or QVGA

format images in YUV422 or raw RGB. The frame update rate can also be
programmed for 30fps and below and even on-shot. This is indicated in the
sample software supplied.

Frame grabber
The frame buffer is based around two, Averlogic AL422 FIFOs. The FIFOs are big
enough to hold a complete colour VGA frame. The hardware interfacing the
camera to the FIFO allows continuous update of frames without DSP intervention.
As discussed later, there is a HOLD signal which the DSP can activate to prevent

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the FIFO from being updated when necessary. Reseting of the FIFO read address
pointer is accomplished by writing to the FIFO port.

FIFO CPLD
An ALTERA CPLD controls the DSKcam FIFO and chip select logic. This device is
used to generate the correct access signals for the FIFO while satisfying the DSP
External Interface requirements. The CPLD contains four, four-bit registers
appearing in D0-D3 of the databus. These are described below.

Address Register Comment

0xA0018000 Interrupt Control Reg (ICR) Used for the ALTERA DSK

0xA0020000 I2C Control Reg (I2CR)

0xA0028000 FIFO Control Reg (FCR)

0xA0030000 Unused

0xA0038000 CPLD Version Reg (CVER)

The register definitions are as follows,

Interrupt Control Register (ICR)

The ICR is necessary for compatibility with the ALTERA FPGA development kit. It
allows the DSKcam to multiplex the individual interrupt sources onto the single
External Interrupt 4 DSP signal. This is required as the ALTERA DSK only contains
one interrupt signal on the expansion connector.

Interrupt Control Register (ICR)

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Bit position R/W Function

D0 (FIFOINT) R When '1' indicates VSYNC interrupt

D1 (ETHEINT) R When '1' indicates W3100A interrupt

D2 (UARTINT) R When '1' indicates a UART interrupt

D3 (MUXINTS) R/W When '1' instructs CPLD to multiplex interrupts

I2C Control Register (I2CR)

This register is used to generate the I2C signals necessary for the camera control.

I2C Control Register (I2CR)

Bit position R/W Function

D0 (I2CDATA) R/W This signal drives and reads the I2C data line

D1 (I2CCLK) R/W This signal drives the I2C clock line

D2 (Unused) -

D3 (Unused) -

FIFO Control Register (FCR)

This register is used to control and read the necessary FIFO control signals. It is
used to hold and synchronise the FIFO read and write pointers appropriately.
Reading this register will de-activate a pending FIFO interrupt.

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FIFO Control Register (FCR)

Bit position R/W Function

This signal prevents the camera from writing a new

D0 (FIFOHLD) R/W
frame into the FIFO

D1 (FIFOEMT) R This signal indicates the FIFO is empty

Set this bit to cause an interrupt at each VSYNC pulse.

D2 (FIFOSNC) - This is used to ensure correct orientation of the FIFO
buffer with the 0 address location.

D3 (Unused) -

CPLD Version Register (CVER)

When read, this register yields a four bit number corresponding to the CPLD
version.

CPLD Version Register (FCR)

Bit position R/W Function

D0 (VER0) R Byte 0 of CPLD version code

D1 (VER1) R Byte 1 of CPLD version code

D2 (VER2) R Byte 2 of CPLD version code

D3 (VER3) R Byte 3 of CPLD version code

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Memory timing requirements

Memory accesses to the daughter card are via EMIF1 CE2 and CE3. Clearly the
access time into the FIFO is determined by the timing setup of the EMIF registers.
Users may wish to reduce the bus cycle times to improve performance although
incorrect operation may result.

TCP/IP Ethernet adaptor

The Ethernet adaptor is based on the WizNET W3100A device. This device
contains a complete hardware implementation of the TCP/IP protocol stack thus
removing the need for processing by the DSP. The device also supports raw MAC
functionality should it be necessary within an application. It also comes royalty
free and does not require any licensing. A complete description of the device is
available in the datasheet found on the CDROM. The WizNET API has been
modified to run under the TI DSP/BIOS operating system. See below for a
description of the API. This has been achieved by introducing a semaphore
scheme that does not block the CPU when waiting for connection opening,
closing or data transmission reception.

Wireless LAN interface (option)

The DSKcam has an optional Wireless LAN interface module based on the NM6000
module. Information regarding the setup and usage of the Wireless LAN module
can be found in the NM6000 data sheet on the DSKcam CD ROM. When powered,
the NM6000 setup is accessed through an integrated Web server on the module.
Connection to the web server is performed over the wireless network in ad-hoc

1
On the C64x, the daughter card asynchronous interface is controlled by EMIFA.

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(peer-to-peer). The NM6000 module appears as a node with address

characteristics.

• IP Address: 192.168.11.30

• Subnet mask:192.128.11.1

• Gateway: 255.255.255.0

In order to gain access to the module the user must enter

• User: admin

• Password: admin

These settings, including the IP address can then be changed. Details on how to
configure the NM6000 module can be found in the data sheet on the DSKcam CD
ROM.

The factory defaults for the wireless interface can be reset using the button on
the DSKcam board.

High-speed serial port

The DSKcam high-speed serial port is based on the TI16C550 UART. This device
can operate up to 1Mb/sec in full duplex asynchronous communications. An IOM
device driver for the DSKcam can be found in the accompanying CDROM (see the
Software section below). Details of how to use and install the device driver can
be found in document uart.pdf on the TI website and also included on the
CDROM. As a device driver is shipped with the board, it will not be necessary to
programme the device under normal circumstances. The datasheet for the TL
16C550 UART is contained in the documentation should users wish to program the
device directly.

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The 9-way d-type connector pinout is shown in the table below for both RS232
and RS485 options.

PIN RS232

2 Tx

3 Rx

5 GND

7 CTS

8 RTS

Software
Example applications are shipped with the DSKcam to enable users to grab,
process and review images. The application grabs an image under interrupt
control and then compresses the image into an h263 bit stream. This bit stream is
then transferred to the host PC via the serial port or TCP interface. The h263
compression only performs intra compression and does no motion compensation.
With the serial port running at 115kBits/sec, a frame rate of approximately 1 per
second is achievable.

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A host application is included in the package. Based on the Telenor h263 codec,
the application has the option to read the bit-stream from the serial port rather
then just a file. When reading from the port, the bit-stream is also saved to a file
on disk.

The example requires the TI C6x image-processing library and may require minor
adjustments to the build options before compilation depending on how the base
CCS package is installed.

Frame grabbing
Capturing images from the DSKcam is simple and, when correctly implemented,
requires little DSP processing. The sample streaming application uses a hardware
interrupt routine, EDMA channel and DSP/BIOS semaphore. See the DSKcam API
below.

Triple Frame Buffering

The video-streaming example employs triple buffering to improve system
performance. The concept of triple buffering is depicted in Figure 6 and is
recommended for most applications.

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Case 1 Case 2 Case 3

Buffer A Buffer A Buffer A

Buffer B Buffer B Buffer B

Buffer C Buffer C Buffer C

Figure 6: Tripple frame buffering

At start-up the three frame buffers A, B and C are as in Case 1. The DSP
processes the image in buffer A while the DSKcam interrupt routine stores frames
in buffers B and C in a circular manner. When the main application requests a
new frame the contents of buffer B is used and the interrupt routine now stores
new frames in buffers A and B. This process continues in Case 3 where the main
application processes from buffer C and the interrupt routine updates Buffers A
and B. This technique is easily achieved by using pointer updates. To prevent the
main application blocking out other tasks when waiting for a new frame, a
DSP/BIOS semaphore is used as communication between the interrupt routine
and the main application.

Occasionally, the DSP may cause and overrun on the FIFO transfer progress. This
is accommodated within the API by re-synchronising the FIFO pointers
appropriately. It should be noted that when re-synchronising, frames would be
lost.

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Application program interfaces

The DSKcam software bundle contains three APIs. The three APIs remove the
need for the programmer to develop a detailed knowledge of the underlying
hardware. The TCP/IP API is adapted from the WizNET API. The UART API is
based on the TI mini driver as discussed above. A simple API for the camera is
detailed below.

DSKcam API
Three functions form the DSKcam API. These functions are detailed below

int DSKcam_open(DSKcam_params *params)

This functions initialises the camera, installs appropriate interrupt service
routines and starts the background triple buffering. The function is called with a
DSKcam_params structure of the following form,

struct DSKcam_params {
int segid; /* Default 0 */
enum { VGA, QVGA} frame_size; /* Default QVGA */
ovcamchip_regvals camregvals[]; /* Default NULL */
} DSKcam_params;

The segid parameter defines the memory segment used in MEM_alloc for the
triple buffer. This memory region must be large enough for the buffer to be held.
The frame_size parameter determines the image used grabbed from the
camera. Finally, the user may which to include extra register or over-write the
default register programming used in the camera by including a list or
register/value pairs. The format of the camregvals is shown below,

typedef struct ovcamchip_regvals {

unsigned char reg;
unsigned char val;
} ovcamchip_regvals;

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If DSKcam_open is called with NULL a default set of parameters are used as

indicated above. The function returns the following error codes.

#define DSKcam_ERR_NONE 0
#define DSKcam_ERR_MALLOC 1
#define DSKcam_ERR_FSIZE 2
#define DSKcam_ERR_CAMERR 3
#define DSKcam_ERR_SEMERR 4
#define DSKcam_ERR_EDMABUSY 5
#define DSKcam_ERR_OPEN 6

int DSKcam_close(DSKcam_params *params)

This routine disables the interrupt routines and returns the heap memory used
for the triple buffering. The arguments and return values are identical to those
described for DSKcam_open.

unsigned char *DSKcam_getFrame()

This routine is the main interface for frame grabbing. When called, the routine
returns a pointer to a memory region containing a YUV interlaced image frame.
The routine will suspend the calling task until a new frame is available.

W3100A API
The DSKcam software includes a simple API to access the W3100A functions. The
API follows the Berkley socket style of TCP programming. Below is a description
of the various functions in TCP stack level.

void initW3100A(void)
Arguments None
Return value None

Description W3100A initialization function for S/W resetting of the W3100A. Sets the initial SEQ# to be
used for TCP communication.

void sysinit(u_char sbufsize, u_char rbufsize)

Arguments Sbufsize: tx memory size
Return value rbufsize: rx memory size

Description W3100A initialization function. Can also be called to change network settings.

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Function Name void setsubmask(u_char * addr)

Arguments addr: Pointer having the value for setting up the subnet mask

Return value None

Description Subnet mask setup function

Function Name void setgateway(u_char * addr)

Arguments addr: Pointer having the value for setting up the gateway IP

Return value None

Description Gateway IP setup function

void setIP(u_char * addr)

Arguments addr: Pointer having the value for setting up the source IP address

Return value None

Description W3100A IP address setup function

void setMACAddr(u_char * addr)

Arguments addr: Pointer having the value for setting up the MAC address

Return value None

Description MAC address setup function

void settimeout(u_char * val)

Arguments val: Pointer having the value for setting up the timeout. Upper 2 bytes have the initial
timeout value, while the last 1 byte has the number of retransmissions until timeout.

Return value None

Description Used for adjusting the TCP retransmission time. A timeout

interrupt takes place when re-transmission is attempted for establishing
the connection or for data transfer beyond the set value.

void setbroadcast(SOCKET s)
Arguments s: Channel number

Return value None

Description Enables/disables broadcasting data transfer in UDP or IP RAW mode.

void setTOS(SOCKET s, u_char tos)

Arguments s: Channel number

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tos: Value to be set for the TOS field of the IP header

Return value None

Description Handles protocol setup function in IP RAW mode

char socket(SOCKET s, u_char protocol, u_int port, u_char flag)

Arguments s: Channel number
protocol: Protocol designated for the channel
SOCK_STREAM(0x01) -> TCP
SOCK_DGRAM(0x02) -> UDP
SOCK_IPL_RAW(0x03) -> IP Layer RAW
SOCK_MACL_RAW(0x04) -> MAC Layer RAW
port: Source port designated for the channel
flag: Options designated for the channel
SOCKOPT_BROADCAST(0x80) -> ‘1’ refers to broadcast data transfer in
UDP mode
SOCKOPT_NDTIMEOUT(0x40) -> ‘1’ refers to use of only the register that
designates the timeout value
SOCKOPT_NDACK(0x20) -> ‘1’ refers to the delayed ACK not to be used
SOCKOPT_SWS(0x10) -> ‘1’ refers to the silly window syndrome to be
used

Return value Channel number if succeeded, or –1 if failed.

Description Initializes the designated channel and waits for completion of W3100A handling.

char connect(SOCKET s, u_char * addr, u_int port)

Arguments s: Channel number
addr: Destination IP address
port: Destination port number

Return value 1 if connection is established, or –1 if connection fails.

Description Initiates a connection to the designated peer in TCP client mode.

char listen(SOCKET s, u_char * addr, u_int * port)

Arguments s: Channel number
addr: Peer IP address at the time of connection establishment
port: Peer Port number at the time of connection establishment

Return value 1 if connection is established, or –1 if connection fails.

Description Waits for connection with a peer. (Blocking Mode) in TCP Server mode. See Nblisten for non-
blocking.

char NBlisten(SOCKET s)
Arguments s: Channel number

Return value 1
Description Waits for connection with a peer. (Non-blocking Mode) in TCP server mode.

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void initseqnum(SOCKET s)
Arguments s: Channel number

Return value None

Description Generates random values for the initial SEQ# to be used for establishing a TCP
connection.

unsigned int send(SOCKET s, u_char * buf, u_int len)

Arguments s: Channel number
buf: Pointer indicating the data to be sent
len: Size of the data to be sent

Return value Sent data size

Description Function for sending TCP data.

unsigned int recv(SOCKET s, u_char * buf, u_int len)

Arguments s: Channel number
buf: Pointer where the data to be received is copied
len: Size of the data to be received

Return value Received data size

Description TCP data receiving function. It continues to wait until len bytes are received.

Function Name u_int sendto(SOCKET s, const u_char * buf, u_int len,

u_char * addr, u_int port)
Arguments s: Channel number
buf: Pointer indicating the data to send
len: Size of the data to send
addr: Destination IP address

Return value Sent data size

Description UDP data sending function. Unlike TCP transmission, it designates the destination address and
the port.

Unsigned int recvfrom(SOCKET s, uchar * buf, uint len, uchar * addr,

uint * port)
Arguments s: Channel number
buf: Pointer where the data to be received is copied
len: Size of the data to be received
addr: Peer IP address for receiving
port: Peer port number for sending

Return value Received data size

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Description UDP data receiving function. Function for receiving UDP and IP layer RAW mode data, and
handling the data header.

char close(SOCKET s)
Arguments s: Channel number

Return value 1
Description Channel closing function.

unsigned int select(SOCKET s, uchar func)

Arguments s: Channel number,
Func:
SEL_CONTROL(0x00) -> return socket status
SEL_SEND(0x01) -> return free transmit buffer size
SEL_RECV(0x02) -> return data size in receive buffer

Return value Socket status or free transmit buffer size or received data size
Description Function handling the channel socket information.

char W3100A_mem_check(void)
Arguments s: Channel number

Return value 0 – memory OK - >0 memory fault

Description Function used to test the W3100A memory for faults.

Appendix A: Memory Map

All accesses to the DSKcam are through CE2 and CE3. The table below shows the
address mapping arrangement.

Address Read Write

0xA0000000 FIFO (16 bit)* FIFO (16 bit)*

0xA0008000 W3100A Base address W3100A Base address

0xA0010000 UART Base address UART Base address

0xA0018000 Interrupt Control Reg (ICR) Interrupt Control Reg (ICR)

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0xA0020000 I2C Control Reg (I2CR) I2C Control Reg (I2CR)

0xA0028000 FIFO Control Reg (FCR) FIFO Control Reg (FCR)

0xA0030000 Unused Unused

0xA0038000 CPLD Version Reg (CVER) UART base (8 bit)

0xB0000000 FIFO (16 bit) FIFO (16 bit)

* Access to the FIFO at 0xA0000000 is included for ALTER DSK compatibility only.
The FIFO should normally be accessed via 0xB0000000.

Appendix B: Interrupt channels

Interrupt Source Level

EXT_INT4 FIFO* High-to-low

EXT_INT5 W3100A High-to-low

EXT_INT6 UART Low-to-high

* The CPLD can be programmed to multiplex all interrupts onto the EXT_INT4
channel for compatibility with the ALTERA DSK. For the C6x and C5x DSK the
interrupt channels should be none multiplexed.

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Appendix C: Schematics

+5V RESET#
U8 U7A
UV0 1 28 DUV0 U2A 74HCT74
UV1 2 DI0 DO0 27 DUV1 74HCT00

4
UV2 3 DI1 DO1 26 DUV2
UV3 4 DI2 DO2 25 DUV3 2 5 2 HOLD

PR
5 DI3 DO3 24 3 Q D
6 WE RE 23 1 3
7 GND GND 22 CLK EXT_INT5
8 TST OE 21 RRST 6

CL
9 WRST RRST 20 YUV# Q +5V
10 WCK RCK 19 +5V

1
UV4 11 VDD DEC/VDD 18 DUV4
UV5 12 DI4 DO4 17 DUV5
UV6 13 DI5 DO5 16 DUV6
DI6 DO6 U7B
UV7 14 15 DUV7

13
DI7 DO7
74HCT74
8

CL
AL422B + Q
C12 RESET 11
2.2UF +5V J1 CLK
4 +5V +5V 9 12

PR
1 SIG Q D
DUV[7..0] 2 GND

10
3 GND R4 R5
GND 10K 10K
+5V PHONO
U9
U4 32 31
Y0 1 28 DY0 UV7 30 VTO GND 29 UV6
Y1 2 DI0 DO0 27 DY1 UV5 28 UV7 UV6 27 UV4
Y2 3 DI1 DO1 26 DY2 UV3 26 UV5 UV4 25 UV2
Y3 4 DI2 DO2 25 DY3 UV1 24 UV3 UV2 23 UV0
5 DI3 DO3 24 22 UV1 UV0 21
6 WE RE 23 20 VCC AGND 19
7 GND GND 22 18 VCC EXCLK 17
8 TST OE 21 16 PCLK AGND 15
9 WRST RRST 20 YUV# 14 VSYN AGND 13 FSR1
10 WCK RCK 19 12 HREF SCL 11 DR1
Y4 11 VDD DEC/VDD 18 DY4 10 FODD SDA 9 R2 DX1
Y5 12 DI4 DO4 17 DY5 Y7 8 RST PWDN 7 1K Y6
Y6 13 DI5 DO5 16 DY6 Y5 6 Y7 Y6 5 Y4
Y7 14 DI6 DO6 15 DY7 Y3 4 Y5 Y4 3 Y2
DI7 DO7 Y1 2 Y3 Y2 1 Y0
Y1 Y0
AL422B +
C3 OV7620
2.2UF
UV[7..0]
Y[7..0]

+5V

DY[7..0]

C7 C14 C1
0.1UF 0.1UF 0.1UF

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A[21..2]

+5V +5V
+5V +5V
PERI1
MEM1
1 2
1 2 3 12V -12V 4
A21 3 5V 5V 4 A20 5 GND GND 6
A19 5 XA21 XA20 6 A18 7 5V 5V 8
A17 7 XA19 XA18 8 A16 9 GND GND 10
A15 9 XA17 XA16 10 A14 11 5V 5V 12
11 XA15 XA14 12 13 SPARE(N/C) SPARE (N/C) 14
A13 13 GND GND 14 A12 15 RSVD(N/C) RSVD (N/C) 16
A11 15 XA13 XA12 16 A10 17 RSVD(N/C) RSVD (N/D) 18
A9 17 XA11 XA10 18 A8 19 SPARE(N/C) SPARE (N/C) 20
A7 19 XA9 XA8 20 A6 21 3.3V 3.3V 22
21 XA7 XA6 22 23 CLKX0 N/C 24
A5 23 5V 5V 24 A4 25 FSX0 DX0 26
A3 25 XA5 XA4 26 A2 27 GND GND 28
27 XA3 XA2 28 29 CLKR0 SPARE (N/C) 30
29 /XBE3 /XBE2 30 31 FSR0 DR0 32
31 /XBE1 /XBE0 32 33 GND GND 34
33 GND GND 34 35 CLKX1 N/C 36
35 XD31 XD30 36 37 FSX1 DX1 38 DX1
37 XD29 XD28 38 39 GND GND 40
39 XD27 XD26 40 41 CLKR1 SPARE (N/C) 42
XD25 XD24 FSR1 DR1 DR1
3.3V 41 42 FSR1 43 44
3.3V 3.3V 3.3V GND GND
43 44 45 46
45 XD23 XD22 46 47 TOUT0 TINP0 48
47 XD21 XD20 48 49 SPARE(N/C) EXT_INT5 50 EXT_INT5
49 XD19 XD18 50 51 TOUT1 TINP1 52
51 XD17 XD16 52 53 GND GND 54
D15 53 GND GND 54 D14 EXT_INT4 55 XEXT_INT4 N/C 56
D13 55 XD15 XD14 56 D12 57 N/C N/C 58
D11 57 XD13 XD12 58 D10 59 N/C N/C 60
D9 59 XD11 XD10 60 D8 RESET# 61 /XRESET N/C 62
61 XD9 XD8 62 63 GND GND 64
D7 GND GND D6 RRST XCTRL1 XCTRL0 HOLD
63 64 65 66
D5 65 XD7 XD6 66 D4 67 XSTAT1 XSTAT0 68
D3 XD5 XD4 D2 EXT_INT6 EXT_INT6 EXT_INT7
67 68 CE3# 69 70
D1 69 XD3 XD2 70 D0 71 N/C N/C 72
71 XD1 XD0 72 73 N/C N/C 74
73 GND GND 74 75 N/C N/C 76
RE# /XRE /XWE WE# GND GND
75 76 77 78
OE# /XOE XRDY GND XCLKOUT2
CE3# 77 78 CE2# 79 80
79 /CE3 /CE2 80 GND GND
GND GND TI6000 DBRD MEMORY 40X2
TI6000 DBRD EXPANSION 40X2

D[15..0]

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+5V
DUV[7..0]

U12
DUV0 2 18 D8 C8
DUV1 3 A1 Y1 17 D9 0.1UF
DUV2 4 A2 Y2 16 D10
DUV3 5 A3 Y3 15 D11
DUV4 6 A4 Y4 14 D12
DUV5 7 A5 Y5 13 D13
DUV6 8 A6 Y6 12 D14
DUV7 9 A7 Y7 11 D15
A8 Y8
OE# 1
19 G1
CE2# G2
74HCT541

DY[7..0]

U3
DY0 2 18 D0
DY1 3 A1 Y1 17 D1
DY2 4 A2 Y2 16 D2
DY3 5 A3 Y3 15 D3
DY4 6 A4 Y4 14 D4
DY5 7 A5 Y5 13 D5
DY6 8 A6 Y6 12 D6
DY7 9 A7 Y7 11 D7
A8 Y8
OE# 1
19 G1
CE2# G2
74HCT541

D[15..0]

U11B

4
CE2#
6
5 YUV#
RE#

74HCT32

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D[15..0]

+5V

U8

10 1 D0
SDI D0 2 D1
DSP_WE# 18 D1 3 D2
WR1 D2 P1
19 4 D3
DSP_RE# 21 WR2 D3 5 D4 RS232
22 RD1 D4 6 D5
25 RD2 D5 7 D6
35 ADS D6 8 D7 C14
CPLD_RESET MR D7
36 0.1uF

5
9
4
8
3
7
2
6
1
37 CTS 11 +5V
38 DSR SDO
39 DCD 34 C13
RI OUT1 31 0.1uF
OUT2

3
16
9 XIN 23

C1-
C+
RCLK DDIS 24 2
TXRDY UART_INT# V+
R7 Y1 A2 28 29
1M 16.0Mhz A3 27 A0 RXRDY 30 11 14
A1 INTRPT EXT_INT6 T1IN T1OUT
A4 26 32 10 7
A2 RTS 33 12 T2IN T2OUT 13
12 DTR 9 R1OUT R1IN 8
13 CS0 17 R2OUT R2IN
14 CS1 XOUT 15 6
CS_UART# CS2 BAUDOUT V-

C2+

C2-
C9 C11 C16
15pF 50pF TL16C550A 0.1uF U10

5
MAX232A/SO

C15
0.1uF
A[4..2]

+5V

C6
0.1uF

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+5V
R5
200R
U6
U1 1
DSP_EXT_INT5 +5V

3.3V 1 25 2
2 3.3V GND 26 +5V
ETH_INT# INT RESET DSP_RESET# 3.3V
DSP_WE# 3 27 7
4 WR TPTX+ 28 RXO+
DSP_RE# RD GND
A[21..2] CS_ETHER# 5 29 8
6 CS TPTX- 30 RXO-
CPLD_RESET 200R
A16 7 RESET L_COL 31 COL R12 5
8 A14 GND 32 Wireless Linc/ACT
200R
A14 9 GND L_100ACT 33 100ACT R13 6
A15 10 A12 TPRX+ 34 Factory Reset
200R
A12 11 A13 L_10ACT 35 10ACT R14 3
A13 12 A10 TPRX- 36 TXO+
200R
13 A11 L_LINK 37 LINK R15 4
A11 14 GND GND 38 TXO-
A10 15 A9 GND 39 D1 9
A9 16 A8 D1 40 D0 GND
A8 17 A7 D0 41 D3 10
A6 D3 GND

1
A7 18 42 D2 W-LINK
A6 19 A5 D2 43 D5 S1
A4 D5 NM6000A
A5 20 44 D4
A4 21 A3 D4 45 D7
A3 22 A2 D7 46 D6

2
A2 23 A1 D6 47

FACTORY RESET
24 A0 GND 48
GND 3.3V 3.3V

IIM7000A
R1
U3
D[15..0] 200R
1
TD+
2
TD-
3
TCT
4
NC
5
NC
6
RCT
7
RD+
8
RD-
9 3.3V
GND 10
MAG GND
R4

0R

C7 C4
0.1uF 0.1uF

 BiTEC Ltd 2005


BiTEC Ltd
12 The Close, Leamington Spa
Warwickshire, CV31 2BL
United Kingdom
Tel. +44-(0) 797-964-5514
Fax +44-(0) 871-661-0229
E-mail: info@BiTEC.Ltd.uk
Internet: www.BiTEC.Ltd.uk
 BiTEC Ltd 2005
Page 35
All information and data contained in this data sheet are
without any commitment, are not to be considered as an
offer for conclusion of a contract, nor shall they be construed
as to create any liability. Any new issue of this data sheet
invalidates previous issues. Product availability and delivery
are exclusively subject to our respective order confirmation
form; the same applies to orders based on development
samples delivered. By this publication, BiTEC Ltd does not
assume responsibility for patent infringements or other rights
of third parties, which may result from its use.
Further, BiTEC Ltd reserves the right to revise this
publication and to make changes to its content, at any time,
without obligation to notify any person or entity of such
revisions or changes. No part of this publication may be
reproduced, photocopied, stored on a retrieval system, or
transmitted without the express written consent of BiTEC
Ltd.