Seminar Report

On
IC Designing, IC Fabrication and IC Manufacturing, IC Verification,
IC Testing

By:- Hiren Patel (CE- 79)

Amit Siddhapura (CE- 110)
SEM -VII

Guided By:- Mr. Mrudang T. Mehta

Mr. Tushar Ratanpara

DEPARTMENT OF COMPUTER ENGINEERING,

DHARMSINH DESAI INSTITUTE OF TECHNOLOGY,

NADIAD- 387001
(2010 – 2011)
 Abstract
We report on IC technology which consist of IC
design flow chart, fabrication, manufacturing, testing
and verification. IC design consist different phases of
IC. Testing and verification contains different fault
model and generation pattern for testing.
Introduction
An integrated circuit (also known as IC,
microcircuit, microchip, silicon chip, or chip) is a
miniaturized electronic circuit (consisting mainly of
semiconductor devices, as well as passive
components) that has been manufactured in the
surface of a thin substrate of semiconductor material.
Integrated circuits are used in almost all electronic
equipment in use today and have revolutionized the
world of electronics. Computers, cellular phones, and
other digital appliances are now inextricable parts of
the structure of modern societies, made possible by
the low cost of production of integrated circuits.
1 IC Design
There are several hundred CAD tool suites in the
market today, which can help us in integrated circuit
(IC) design.
1.1 IC design flow
Design Flow is a term used to describe the various
Figure1: design flow
design phases of an IC design. The first thing needed
to start a design, is a specification of what needs to be
done („specs‟). Given a specification, the most
general approach adopted is shown in figure
Design idea
Based on the specification given, the design team
forms a general idea about the solution to the
problem. System level decisions are made regarding
the design and a general consensus is reached
regarding the major functional blocks that that go
into the making of the chip. At the end of this stage, a
general block diagram solution of the design is
agreed upon. CAD tools are generally not needed at
this stage.
Behavioral description
Hardware Description Languages (HDLs) are used to
model the design idea. Circuit details and electrical
components are not specified .Instead, the behavior
of each block at the highest level of abstraction is
modeled. Simulations are then run to see if the blocks
do indeed function as expected and the whole system
performs as a whole. Behavioral descriptions are
important as they corroborate the integrity of the
design idea.
Structural description
HDLs are used to describe the construction of the
design at the next level of abstraction. In this stage,
various electronic components and circuit details that
go into the making of the various blocks of the
system are modeled. These may include primitives
like logic gates and very large pre-designed blocks
called standard cells. Simulations are then run on
each block separately to test its operation. Once this
is completed, all blocks are interconnected and a
system level simulation is run. A successful
simulation ensures that an electronic circuit can
indeed be built to match the behavioral description.
Schematic description
A schematic description is similar to a structural
description. In a rigorous context, schematics can be
considered to be at a lower level of abstraction, as the
topology of the circuits needs to be considered. In
most cases, graphical tools are used to build the
circuits in a virtual breadboard like environment. Just
as in the previous stage, various electronic
components like logic gates and standard cells are
placed and interconnected to make the circuit blocks.
This is an alternative form of structural description
with more attention being paid to topology. A
successful simulation ensures that an electronic
circuit that matches the behavioral description can be
built.
Layout description
This is the lowest level of abstraction possible in
circuit description. In this stage, the circuit is
described with respect to the silicon and other
materials that go into the making of the IC. Extreme
attention is paid to geometry of the components. In
other words, this is how the IC would look, if we
took a closer look at it through the microscope.
Parasitic elements need to be extracted at each stage.
The placement and interconnects of each and every
individual entity of the previous stage need to be
specified. Extensive simulations of each block are
run in this stage. A floor plan of the chip is made and
the blocks are routed together. After the routing
phase, simulations of the entire design are run.
LVS
After the completion of the layout description of each
block, a Layout vs.Schematic (LVS) check is
performed. This ensures that the layout is in
conformance with the schematic. The design process
moves back and forth between Layout, LVS and
DRC.
DRC
This stage is often dependent on the final process
technology that is used to manufacture the chip. The
design rule check ensures that the rules laid down by
the fabrication process technology are not violated. A
good example would be, some processes need
transistors, wires and polysilicon to be of a certain
minimum width. The layout would have to be drawn
based on such constraints. The design toggles
between Layout, LVS and DRC.
CIF, GDS II
This is the final stage before fabrication. Most
fabrication plants accept submissions in CIF or GDS
II. These are computer generated files that describe
the IC layout. They incorporate all the necessary
details for manufacturing the chip. MOSIS accepts
submissions in both CIF and GDS II formats and
these files can be submitted electronically. A chip
design team‟s job comes to a momentary pause until
the first few prototyped chips arrive from the
fabrication plant. After the „silicon‟ arrives, the
testing phase begins. The first basic tests include a
functional verification of the chip under ideal
conditions. Once the functionality is verified,
extensive tests are performed by stretching various
electrical parameters like frequency of operation and
temperature to extremities. The chip‟s behavior is
then documented into the chip‟s user manual.
2 IC manufacturing and fabrication
It would not be easy to extract silicon from
rocks and dirt, and convert it to the raw material used
to make ICs, but it is in fact somewhat involved.
The raw material normally employed in the creation
of ICs is high-purity quartz from countries such as
Norway and Brazil. Repeated reduction and
rectification refines the quartz to approximately
99.999999999%, or "eleven nines" purity. The reason
of the purity is the circuits to be formed on an IC are
now so small and highly integrated. Furthermore, as
circuit elements are produced within the IC in the
following process, traces of chemical elements such
as boron, phosphorous and arsenic are added to the
oxidized silicon as required to form the
characteristics of the intended semiconductor circuit.
In order to maintain the precision of this reaction, the
purest possible silicon is necessary.
As shown in the portion of the periodic table
displayed below, silicon is a Group IV element with
an atomic number of 14 - meaning it has 14 electrons,
in this case four of which are in the outermost shell.
In crystallized silicon, adjacent atoms share electrons,
which means that their outermost shells are united by
a total of eight electrons. The most stable forms of
silicon consist of either two or eight atoms, and
permit virtually no electrical conductivity. This is
neither a conductor nor an insulator... this is a pure
semiconductor.
Germanium, also a Group IV element with an atomic
number of 32, was the first semiconducting material
discovered and can also be used independently as a
semiconductor. Silicon, as the world‟s second most
common element with characteristics strikingly
similar to those of germanium, is extremely well-
suited for microfabrication. It is the perfect choice for
integrated-circuits.

Even though we are dealing with silicon of "eleven
nines" purity, it is not yet in a state in which it can be
used in the production of ICs. The molecular
structure consists of many crystals in disarray - the
molecules must be uniformly arranged vertically,
horizontally and diagonally to form a single crystal
(monocrystal). This is due to the extremely high level
of integration achieved in IC design. The following
steps in the process entail the creation of a
monocrystalline silicon ingot (lump) and then the
cutting of silicon wafers measuring 200-300mm in
width. One IC can consist of hundreds of individual
parts. Within a single IC, there may be as many as
one to ten million devices. If these steps are
performed using silicon with an unstable molecular
structure, it is not possible to achieve the same level
of quality. In order to ensure uniform IC quality, the
silicon base must be extremely homogeneous. This is
why it is necessary to convert the silicon to
monocrystal form.
The next step in the process is the creation
of the monocrystalline silicon ingot. The most widely
employed method, and the one we'll discuss here, is
the Czochralski (CZ) method. First, the "eleven
nines"-pure silicon is melted in a quartzware crucible.
Minute quantities of conductive, impure elements
such as boron and phosphorous are added, giving
birth to p-type or n-type monocrystals. Next, while
rotating the crucible, a tiny seed crystal tied to a
length of piano wire is lowered into the molten
silicon. It is then stirred in the direction opposite the
rotation of the crucible, creating monocrystal silicon
identical to the seed crystal. Careful control of the
molten silicon's temperature enables the creation of a
silicon ingot 200 to 300mm in width, and as long as
is required. Monocrystal atoms are arranged in a very
orderly fashion. To illustrate... if we were using
carbon instead of silicon, this would be a diamond
ingot
Adding boron gives the monocrystal a p-type or
positive character, while adding phosphorous results
in an n-type or negative-character monocrystal
Over the past few years, compounds such as gallium-
arsenide and gallium-phosphorous have become more
in vogue as materials for use in IC manufacture, but
problems still exist with these compounds when it
comes to microfabrication and large-diameter wafer
manufacture. Silicon remains the most practical
material. The benefits of increased wafer size include
the ability to manufacture ICs in larger quantities,
which improves the cost performance for the
manufacturing process and subsequently enables
price reductions for electronic equipment.
Once the silicon monocrystal has been
prepared, the actual IC manufacturing process can
begin. The basic principles are as described below.
1.Making silicon wafers from monocrystal
silicon First, the monocrystalline silicon ingot is
sliced into wafers using a diamond blade, to a
thickness of approximately 0.5mm. The wafers are
beveled and polished in order to minimize chipping
and cracking, and then a portion of each wafer is cut
off to create the "orientation flat" or "notch".
Currently, the notch is most commonly cut in the
shape of a "V". This is one of the standards of wafer
formation and processing. (See fig. 1)
2. Oxide film coating The wafers are baked
in a furnace at about 1000°C while being exposed to
a combination of oxygen and silicon gas, creating an dissolves, leaving only the bare oxide film on those
oxide film on the surface. After formation and regions. The negative photoresist areas remain
processing, this oxide film will determine the shape virtually intact, and the resist left on the surface is
of the circuit. (See fig. 2) referred to as the "resist mask.". (See fig. 5)

3. Photoresist coating The oxide film-coated

wafers are rotated at high speed, allowing a very thin,
uniform layer of photoresistant film (photosensitive
agent) to form on the surface of the wafers. In the
photolithography process that follows, the wafers are
illuminated to locate areas coated in positive 6. Etching A gas or liquid is then used to dissolve the
photoresist (likely to dissolve under illumination) and revealed oxide film layers, and to ensure all
negative photoresist (less averse to illumination). remaining photoresist is removed, a powerful
This is one way in which photographic technology is developing agent is applied. This process is called
contributing significantly to IC manufacturing. "etching". (See fig. 6)

4. Forming circuit patterns though

photolithography The next step is to form the circuit
patterns on the surface of the wafers. In
scanner/steppers such as Nikon's NSR series, the
electronic circuit pattern contained within the reticle
(the photomask used to transfer the pattern to the
wafer) is reduced to 20 or 25% in size as it is
projected onto the wafer. Photolithography is
performed one chip at a time, with exposure repeated
hundreds of times for each wafer. The NSR-S207D,
for example, can process 300mm wafers at a rate of
7. Doping Impurities - or "dopants" - including
boron, phosphorous and arsenic are embedded into
the wafer in a temperature-controlled furnace,
creating transistors, diodes and other devices. A heat
treatment known as "annealing" is then applied to the
impurities to ensure the proper reaction. In order to
form all of the necessary devices on the wafer, steps
3 through 6 above are performed repeatedly. The
number of repetitions depends on the type of IC, but
these steps must generally be performed anywhere
from a dozen to several dozen times. (See figs. 7-1 &
7-2)
up to 115 per hour. (See fig. 4)
8. Interconnection Next, in order to connect
5. Developing During the developing the various devices created on the surface of the
process, the positive photoresist on each wafer wafer, a technique called "vapor disposition" is used
to cover the entire surface with aluminum. The
aluminum is then stripped from places where it isn't
required, leaving only the circuit traces
(interconnection). In recent years, damascene
processing using copper and other materials has
become increasingly common. (See fig. 8)
9.Dicing Every wafer is checked to confirm
that the circuits have been formed correctly on each
chip. Then the undersurface is polished and a
diamond cutter used to dice the wafer into individual
chips by cutting a checkerboard pattern. (See fig. 9)
10. Bonding The diced chips are connected
to leadframes (the frames used to connect the chip to
the pins) using extremely fine gold wire. This process
is called "wire bonding". (See fig. 10)
11. Molding After it is wire-bonded to the
leadframe, each chip is inspected, and then encased
in a synthetic resin or ceramic package in a procedure
referred to as "encapsulation molding". At last, the
process is nearly complete. (See fig. 11)
1
12. The final step Theleadframe is trimmed off and
the leads are formed into the shape required to mount
the IC on a circuit board. Various packages are
produced depending on the processing. (See figs. 12-
1 & 12-2)
IC manufacturing technology is constantly
evolving. The materials technology and
nanotechnology of today will continue to advance,
creating new techniques to meet tomorrow's
production needs. Nikon stepper technology is also
playing a central role in the manufacture of next-
generation ICs, through the development of
photoresists with increasingly intricate structures
(down to the molecular level) and photolithography
employing new light sources such as laser, electron
beams and soft X-rays.
3 IC Testing & Verification
The evaluation of the reliability and quality of digital
device is commonly called testing, yet it comprise
distinct phases that are usually kept separate, both in
the research community and in industrial practice.
1. Verification is the initial phase at design time when
one ensures the match of requirements specifications
to the current functionality, that is, a digital device
needs to be verified for correctness. Verification
checks that all design rules are adhered to.
2. Testing more precisely refers to the phase when
one must ensure that only defect-free production
devices are shipped, and faults arising from
manufacturing are detected. Testing methods must:
(a) be fast enough to be applied to large numbers
ofdevices during production; (b) take into
consideration possible access to large expensive
external tester machines.
3.1 IC Verification
Several methods of IC Verification:
Formal verification methods
Equivalence checking Check whether two
descriptions of same design are consistent Mostly
used for implementation verification Assumes that
“master design” is correct!
Model checking
Construct behavioural description of system as FSM
Specify properties in temporal logic Use model
checker to verify validity of properties with respect to
FSM.
Theorem proving
(One of the earliest approaches!)
Describe implementation and spec in formal logic
Prove in that spec and implementation are suitably
related.Much research has been done on the theory.
But no big breakthrough in practice (yet).
3.2 Fault Models
At the defect level, an enormous number of different
failures could be present and it is totally infeasible to
analyze them as such. Thus failures are grouped
together with regards to their logical fault effect on
the functionality of the circuit, and this leads to the
construction of logical fault models as the basis for
testing algorithms and the evaluation of fault
coverage. More precisely, a fault denotes the physical
failure mechanism, the fault effect denotes the logical
effect of a fault on a signal-carrying net, and an error
is defined as the condition (or state) of a system
containing a fault (deviation from correct state).
Faults can be further divided into classes according to
their characteristics, as shown in Figure 2. Here we
discuss only permanent faults, that is, faults in
existence long enough to be observed at test time, as
opposed to temporary faults (transient or
intermittent), which appear and disappear in short
intervals of time, or delay faults, which affect the
operating speed of the circuit.
The fundamental fault model is a stuck-at fault,
which implies the fault effect to be a line segment
stuck at logic 0 or 1 (stuck-at 0 or stuck-at 1). Testing
may consider single or multiple stuck-at faults and
Figure 3 shows an example for a simple circuit. The
faultfree function is shown as Z, while the faulty
output functions, under the occurrence of the single
stuck-at faults of either line a stuck-at 0 (a/0) or of
line b stuck-at 1 (b/1), are shown as Z*. A stuck-at
fault needs a single appropriate input pattern to
stimulate the fault by controlling the inputs and
making the faulty output observable, and the goal of
test patterns generation algorithms is to find such
settings for all detectable faults.
On the other hand, a delay fault defines the fault
effect to be slow-to-rise (from 0 to 1) or slow-to-fall
(from 1 to 0), such that the final value may indeed be
correct, but outside the timing parameters expected.
To detect such faults, one must apply two patterns as
stimuli: the first to set a line at a certain value and the
second to change that value. This, of course,
increases the complexity of a fault detection
algorithm, Even considering only single stuck-at
faults, not all possible faults need to be explicitly
tested, as many have the same fault effect and are
indistinguishable. For example, an input stuck-at-0
fault for an AND gate has the same logical effect as
the output stuck-at-0, and one needs only test for
either one. Fault collapsing is the process of reducing
the total number of faults to be examined using fault
equivalence classes based on fault effects.
3.3 Test Pattern Generation
Test pattern generation is the process of generating
an appropriate (minimal) subset of all input patterns
to stimulate the inputs of a circuit such that a desired
percentage of detectable faults can be exercised and
detected The process can be divided in two distinct
phases: (1) derivation of a test and (2) application of
a test. For (1), one must first select appropriate
models for the circuit (gate or transistor level) and for to 1 to control line g being 1, thus assigning
faults; one must construct the test such that the output
signal from a faulty circuit is different from that of a x1=x2=1, which also forces line f to be 0. This leaves
good circuit. This can be computationally very x3 with a choice of either 0 or 1 to maintain h=0.
expensive, but one must remember that the process is Thus 2 test patterns are found: (x1 x2 x3) = {(1 1 0)
done only once during the design stage. The or (1 1 1)}.
generation of a test set can be obtained either by
algorithmic methods (with or without heuristics), or 4. References
by pseudo-random methods. On the other hand, for
phase (2), a test is subsequently applied many times [1]Introduction to VLSI circuits and system By John
to each device and thus must be efficient both in
P. Uyemura.
space (storage requirements for the patterns) and in
time. Often such a set is not minimal, as near [2] DIGITAL DESIGN FLOW OPTIONS by Sagar
minimality may be sufficient. The main Vidya Reddy.
considerations in evaluating a test set are: (a) the time [3]www.wikipedia.com
needed to construct a minimal test set; (b) the size of
the test pattern generator, i.e., the software or
hardware module used to stimulate the circuit under
test; (c) the size of the test set itself; (d) the time to
load the test patterns; and (e) the equipment required
(if external).

3.3.1 Path Sensitization

Most algorithmic test pattern generators are based on

the concept of sensitized paths, through
controllability and observability. Given a line in a
circuit, one wants to find a sensitized path to
stimulate a possible fault and carry its logical effect
to an observable output. For example, to sensitize a
path that passes through an AND gate, one must set
all other inputs of the gate to logic 1 to permit the
sensitized signal to carry forward.
Figure 5 summarizes the underlying
principles of constructing a test pattern for each fault
through path sensitization, which is not a full
algorithm, but underlies the overall logic. In Part (a)
one wants to find possible input patterns to test the
fault on line g/0. One must set line g to 1 and might
expect a faulty signal to be 0, thus the notation g:1/0.
In forward propagation, line h must be set to 0 in
order for the fault to become observable at the output
Z: 1/0. In Part (b) of Figure 5, the second phase of
backward propagation is shown, where possible
controlling inputs are set. Lines a and d must be set