A Low Phase Noise Tri-band LO Generation for Ku
and E Band Radios for Backhauling Point-to-Point
Applications
i i i 2
D. Cabrera , JB Begueret , N. Verrascina , O. Tesson , O. Mazouffre , P. Gamand
'IM S Laboratory, University of Bordeaux, France
2NXP Semiconductors, Caen, France
Abstract- This paper demonstrates a fully integrated tri­
band LO generation system based a low phase noise 12 GHz sub­
harmonic VCO and an injection locked frequency tripler (ILFT)
as the signal source. The system generates simultaneously three
outputs atfo,fol2 and 2xfo, with maximum frequency of 36 GHz,
18 GHz and 72 GHz respectively. The system which
implemented in a 0.25-llm SiGe:C BiCMOS technology, has a
phase noise of -107.72 dBclHz at 1 MHz offset from the 36 GHz
signal measured at thefo-port. All outputs have a tuning range of
9.5%. The in-band output power at thefo,fol2 and 2xfo outputs
is higher than 3 dBm, 0 dBm and -20 dBm respectively. The
whole system draws 120 rnA for a power supply of 2.5 V.
Keywords-phase noise; multiband millimeter wave frequency
generation; subharmonic VCO; frequency tripler; injection
locking.
I. INTRODUCTION
Wireless backhauling is a suitable solution for the next
generation of wireless infrastructure. M m-wave radio links in
the Ku/E frequency bands as defmed by the Point-to-Point
(P2P) standard [ 1] provide the transmission/reception capacity
required to cope with the needed data rates, but as the same
time it poses stringent specifications on the transceiver front­
end building blocks; among others the phase noise capabilities
of the Local Oscillator (LO) is quite challenging.
Thanks to the good spectral purity and tuning range (TR)
capabilities, fundamental LC-based YCOs have been widely
used in LO generation at RF frequencies. However, when the
oscillating frequency scales (keeping the same orders of TR)
the YCO phase noise experiences a considerably degradation,
therefore increasing the design challenge. One promising
approach to overcome this difficulty is the use of subharmonic
YCOs followed by frequency multipliers [ 2-5]. Indeed,
subharmonic oscillators can benefit from three fundamental
factors: low oscillating frequency, bigger tank capacitance and
better tank quality factors. The conjunction of these factors is
enough to compensate the 20 xlog(n) phase noise degradation
after a frequency multiplication by n.
In particular, in [ 5] the authors demonstrated the potential of
this technique to generate a low phase noise 31 GHz LO for a
direct conversion transceiver in the Ku-band. In the present
work, the capabilities of that previous prototype are further
extended enabling its integration in a multiband transceiver for
the Ku/ E frequency bands.
978-1-5090-0484-3/16/$31.00 ©2016 IEEE
i 2
I. SYSTEM ARCHITECTURE
A block level diagram of the proposed system is depicted in
Fig. 1. As in [ 5] the system is based on a sub-harmonic YCO
followed by an injection-locked frequency tripler (lLFT)
is composing the LO-Core. Compared to the previous design, the
central frequency (fa) of the LO-core was shifted to 34 GHz
while keeping the same TR, thus enabling its integration in a
Low-IF front-end for the 38 GHz band dedicated to the P2P
standard. Two circuit blocks are added subsequently in order to
provide two signals at fol2 and 2 xfo. These signals are suited
to be applied in an image rejecting mixer (not described in this
work) to generate the 70-80 GHz frequencies required by the
E-band front-end.
@fo-+_--l
Fig. I. Conceptual block diagram of the proposed tri-band LO generation.
II. CIRCUIT DESCRIPTION
The fol2 block chain is composed by a frequency divider
followed by an output buffer, thus providing the driving
capabilities and output power to a 50 Q output. On the other
hand, thefo and 2 xfo signals are both obtained from the same
output buffer. As it is observed in the Fig. 1, emitter-followers
(EFs) are used to distribute the signals among the different
blocks thus providing, at the same time, a good isolation to the
LO-core. The wideband nature of the emitter-followers was
preferred over narrowband tuned amplifiers due to the higher
sensitivity of the latter to process variations that could result in
strong attenuation of the desired signals. Electromagnetic
simulations were used to characterize the interconnections and
PADs of bothfa and 2 xfo signal paths.
A. Divider-by-2
Regenerative dividers are in general a good compromise
between input frequency range and power consumption. This
type of topology is used as the first stage in high division
factors at mm-wave frequencies [ 6, 7]. The divider used in this
work is depicted in Fig. 2(a), and it is based on the
56
implementation in [ 6], where a transimpedance amplifier
(TIA) and a double-balanced mixer are used.
a)
Fig. 2. Schematic view of the blocks composing the system: a) Divider-by-2. b) 18GHz output buffer. c) 36 and 72 GHz output stage.
For a given bias current of the TIA the loop gain can be
increased by increasing both RI and Rf or by increasing the
bias current of the transconductance stage in the double­
balanced mixer. The cutoff frequency of the loop gain is
determined by both the mixer and the TIA. Increasing the TIA
bias current increases its cutoff frequency. Note that RI, Rf, 11
(the DC current passing through Ml) and 12 (the DC current
passing through M 2) should be carefully chosen to let enough
voltage room for the Vds voltage of the bias transistor Ml.
B. Output Buffers
The designs are based on the cascode amplifiers in figures
2(b) and 2(c). This topology provides good input/output port
isolation while providing adequate power gain [ 8]. In both
buffers, for a power supply of 2.5 V, a total of 20 rnA (10 rnA
per branch) of DC current was enough to provide a simulated
output power> 3 dBm over a 50 Ohms load. In both buffers,
the common-emitter transistor is a high-speed NPN with
emitter area chosen for maximum ft. For cascode transistors a
high-voltage NPN was used.
Since the previous stage of both buffers is an emitter-follower
(i.e., a stage with low output impedance), a strategy based on
strong matching 9 [ ] is used. In the strong impedance matching
technique a low output (input) impedance is matched with a
high input (output) impedance. Thus, a high input impedance
buffer is targeted. This can be accomplished by resonating (at
the frequency of interest) the capacitive input impedance of
the buffers with a parallel inductance. The differential nature
of the signals involved led naturally to the use of a
transfonner. In both designs 1:1 transformers are used. As
observed in the figures 2(b) and 2(c), the center tap at the
secondary winding is conveniently used for bias the input
transistor.
57
The sensitivity of the divider, defmed as the lower input
voltage for proper division and the input frequency range are
defined by the gain and the cutoff frequency of the loop.
For the output matching network, both buffers use baluns.
Indeed, the 50 n output load is transfonned to the optimum
impedance at the cascode transistor collector.
Electromagnetic (EM ) simulations of the PAD were
performed to characterize it. S-parameters (for different
frequencies in a broad frequency range) were taken into
account during the simulations and all the stages of the design,
including the input/output matching network. In a similar way,
EM simulations for the interconnections associated to the
layout were performed and considered in the design of both
input/output matching networks of the 36 GHz buffer. For the
18 GHz buffer, a similar approach was used but, due to its
lower frequency, the impact of the interconnections in the
layout was evaluated using a RLC extraction.
Choosing the output of the common emitter node (Fig. 2(c))
the signal at 2 xfo can be obtained. This technique is inspired
from the frequency doubler described in [ 2]. Note that the
resistance RbI sets the current in the amplifier. The inductance
LmI and capacitance Cm4 were set to maximize the output
power. This modification proves to be enough for a targeted
simulated output power of -20 dBm in the frequency band.
III. SYSTEM INTEGRATION, LAYOUT CONSIDERATIONS AND
MEASUREMENTS
All blocks in the system work in differential mode up to the
output buffers where the differential to single-ended
conversion of the fo and fol2 signals takes place. The sub­
harmonic VCO (see Fig. 1) does not share the same voltage
supply (VDD) with the rest of the system. By doing so it is
possible to evaluate the unlocked condition of the system.
The system is implemented in the NXP QUBIC4Xi SiGe:C
BiCM OS process [ 10]. In Fig. 3, a picture of the fabricated
circuit is presented. A highly compact layout and an area
efficient arrangement of the blocks were achieved thanks to
the transformers (baluns) in the input (output) matching
networks of the output buffers. Indeed, the placement and
routing between the blocks were carefully performed having
the LO-core in the center of the die. The block chain for the fo
andfol2 signals was disposed at opposite sides of the die and
therefore minimizing unwanted coupling between the ports.
Since all DC-pads were located at the same side of the die, a
single DC multi-contact wedge was used, thus enabling fully
on-die characterization of the circuit.
During the measurements, the fo, fol2 and 2 xfo ports were
always loaded with a 50 n impedance.
21% of the total power consumption. As a reference, the table
II shows a comparison with previous published VCOs; note
that since the system is intended to generate simultaneously
three different tones to an external 50n load, standard figure­
of-merit of VCOs are not well suited for comparisons.
IV. CONCLUSIONS
A tri-band low phase noise LO generation system suitable for
a Ku/E multiband front-end radio was successfully
demonstrated. Based on a low-phase noise sub-harmonic VCO
the system generates simultaneously LO signals at three
different RF outputs fo, fol2 and 2 xfo with adequate output
power and tuning range.

Fig. 3. Photograph of the fabricated chip. Chip size: 2000 J.lm by 800 J.lm

For the measurements, the two channels of the R&S®FSU26

signal analyzer were used. By using a subharmonic mixer, the
frequency range of one channel can be extended. This channel
was used to measure either the signal at fo or 2 xfo. All tests
were performed at a temperature of 25° C. Fig. 4. Measured phase noise at I MHz at theJo-port in the unlocked (green)
In order to verify the functional characteristics of the system, and locked condition (blue).
the unlocked condition was fust verified. The sub-harmonic
VCO was thus disabled by setting its VDD=O resulting in the
ILFT (see Fig. 1) in free-running. At thefo-port, the measured
phase noise at 1 M Hz is presented in Fig. 4 (green): we
observed a value of -86 dBc/Hz. In a second step, the sub­
harmonic VCO was enabled and set to its maximum
frequency; the figure 5 presents the measured spectrum. A
signal power of 3 dBm was measured. However, since the
1 dB output compression point of the sub-harmonic mixer
used in the measurements is 3 dBm, the maximum output
power at thefo-port could not be verified.
The measured phase noise of the locked system is presented in
the figure 4. The measured phase noise at 1 M Hz offset
is -107.7 dBc/Hz; an improvement of more than 20 dB when
compared to the unlocked condition is thus achieved. The
measured frequency range at the fo-port for the different
frequencies of the sub-harmonic VCO are presented in Fig. 6.
At its maximum frequency, the 18 GHz signal has a phase
Fig. 5. Measured spectrum at theJo-port when locked to the YCO.
noise at 1 M Hz offset of -113 dBc/Hz with signal power of
o dBm. The phase noise difference betweenfo andfo/2 signals
is thus very close to the theoretical 20 xlog(2) factor. Finally,
the system was taken close to its lowest frequency and the
phase noise at 1 M Hz offset from the resulting 67 GHz signal
at the 2 xfo port was -100 dBc/Hz. At this frequency the signal
power was -20 dBm. The table I summarize the measurement
results obtained. Note that the EFs stages (see Fig. 1) dissipate

58
 36G 000 ACKNOWLEDGMENT

35.5G This work is part of the "RF2THz" project supported by the

N European CATRENE program.
I 35G
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67 outputs) -100
2xfo

59