USN f/ * /s f* I( tzBC021

M.Tech. Degree Examination, Dec.2013 I Jan.20l4

GMOS VLSI Design
Time: 3 hrs. Max. Marks:100

o Note: Answer any FIVE full questions.

E a. Derive the expression for the threshold voltage of a MOS transistor and explain the

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significaace of different parameters present in the equation. (10 Marks)
b. Briefly .*p,F*- the fo llowing terms :
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i) Punch tlirough , ,.] ,ii

il) Impact ionization. ,

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(06 Marks)
c. Suppose Voo: l'.2Y andvt: 0.4V. Determine Vo,1in Fig.Q,'l(c) for
69
.o' i) V;, : 0V ; ii) Vi,= 0.6V ; iii) Vi" : 0.9V ; iv) V;n : 1.2Y. Neglect the bodyeffect.

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oo (04 Marks)
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a. Consider the nMOS transistor in a 0.6pm process::with gate oxide thickness of 100A'. The
-d
doping level is Nn:2, I0'' cm-3 and the nominal threshold voltage is 0.7V. The body is
tied to ground with a substrate contact. How much does the threshold change at room
2a
'ia temperature if the source is at 4V instead of OV? (07 Marks)
o;
b. Define noise margin and its significance in the design of an inverter base circuit. (07 Marks)
tro. c. With relevant""response curves explain the transmission gate:: Oqlput characteristics for
o.w
oi change in control input and for change in switched input. (06 Marks)
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3 a. Eesciibe in detail twin tub CMOS process of fabrication. (08 Marks)
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b. Derive the expressions for rise time and fall time of a CMOS (08 Marks)
bot
tr5Q c. Obtain the scaling factors for the following:
qo D Gate capacitance (C*)
tr> ii) Maximum operating frequency (fo).
O.
iii) Power dissipation per unit area (Pu).
U< iv) Gate delay (T6). (04 Marks),

o
z 4 a. Explain the phenomenon of charge storage and charge leakage and obtain the expression for
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the holding time tmra. (10 Marks)
o. b. How do clocked SR and JK latch operate? Draw relevant waveforms. Draw NAND
implementation cut for both. (10 Marks)

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5 a. Calculate the Cin and Cout values of capacitance for the structure represented in Fig.Q.5(a).
(08 Marks)

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3.\
-i

Fie.Q.s(a)
:'
b. Derive the threshold voltage Vl for 2 input NOR gate. :'. (08 Marks)
c. Draw nMOS and CMGS version of the circuit to realize the following Boolean expression.
Z=A(D+E)+BC. (04 Marks)

6a. Analyze a nMOS current mirror cirouit. (05 Marks)

b. Explain the general principle of band gap reference and hence obtain the expression for Vss.
(10 Marks)
c. List out advantages of CMOS over nMOS. (05 Marks)

7a. (10 Marks)

b. Mention the causes of latch up and guidelines for avoiding latch up. (10 Marks)

8a. Describe charge sharing and its solution in brief. (05 Marks)
b. Show how domino CMOS logic gate can be cascaded with static CMOS logic gates and also
mention the limitation of the same. , .t (05 Marks)
c. Describe different clock distribution schemes. (10 Marks)
 tzECl29
USN

M.Tech. Degree Examination, Dec.2013 I Jan-2O14

SOG Design
Time: 3 hrs. Max. Marks:100
,]

Note: Answer uny FIYE full questions.

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o
o
I a. What is Moore's law? What are the limitations impose by small device geometrics.
(15 Marks)
o. (05 Marks)
b. Compare system-on-based, system-on-chip and system-on-package.

(.)
! 2 a. What is short channel effect? Explain. (10 Marks)
(.)
! b. What is scaling? What are its types? Explain constant voltage scaling. (10 Marks)
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bo-
3 a. Consider an n-channel MOS process with the following parameters : substrate doping
ilicon gate
density No =10'ucm'3, polysilicon doping
sate doping de,1sit1 =2x1020cm-3, gate
)r!*-".)
oxide thickness tox : 50 oxide-interface fixed gl-rarge^density N6y : 4 x 1010
-oo I

Ec€ and
r;r
.= oi "m'
source and drain difhrsion doping density Np =,'f'6lz c*'. In addition, the channel region is
Ho
OE: implanted with p-type impurities (impurity concentration N1 : 2x10"cm-2) to adjust the
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threshold voltage. The junction depth of the source and drain diffusion regions is
x.i : 1.0 pm.Plot the variation of the zero-bias threshold voltage Vro es a function of the
channel length (assume that Vps = Vss : 0 and the threshold voltage without the channel
a=

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6O b. Explain : (i) Canonical SOC design (ii) Soft IP versus Hard IP. (10 Marks)

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4 a. Explain waterfall versus spiial system design flow. (10 Marks)

!6= b. Explain system design process. 'i '','. (10 Marks)

LO
o€ 5 a. What is flash memory? Explain NOR flash memory cell and pompare with NAND flash
JO memory cell. (10 Marks)

o'v b. What is DRAM? Explain with the design. (10 Marks)

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a. What is network topology? Explain. (10 Marks)

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b. WMt are switching strategies? Explain packet switching and its types. (10 Marks)

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^;o a. What are the limitations of traditional ASIC design? (10 Marks)
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b. Explain extensible processors as an alternative to RTL. (10 lllarks)
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o- a. Explain design of timing closure: logic design issues. (10 Marks)
e< b. What is routing? Explain NOC routing and its schemes. (10 Marks)
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 USN
12EC118

M.Tech. Degree Examination, Dec.2013 I Jan.2ol4

Advanced Embedded System
Time: 3 hrs. Max. Marks:100
Note: Answer any FIVEfull questions.

()
I a. Distinguish between Big-Endian and Little-Endian processors, with an example. , (06 Marks)
o
o
b. Explain the different types of RAM used for embedded system design. (08 Marks)
!
a c. Describe the role of Brown-Out protection circuit. (06 Marks)

2 a. Explain,the operation of the 12C on-board communication interface; with a discussion on

(.)
the sequenee of operations required. (08 Marks)
()
! b. Discuss ZigBee network model. (06 Marks)
oX L. Explain the important operational quality attributes to be ,considered in any embedded
system design. ': " (06 Marks)
6v

coo a. Compare dataflow graph"(DFG) and control data flowgraph (CDFG) model. (06 Marks)
.= c.l b. Design an embedded system for driver/passenger 'seat belt warning' in an automotive using
Ho
FSM model implement wait state using timer, ,, (08 Marks)
oE
eO c. What is UML? What are the fundamental building blocks of UML? Explain sequence
o> diagram, with an example. (06 Marks)
(,)
=
6:
4a. Discuss "super-loop" based embedded firm ware design. (06 Marks)

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b. With a neat diagram, explain the conversion process of a high level language to machine
language. Also explain the advantages of high level language based development. (10 Marks)
o0c c. What is "inline assemblv"?
.:..::.
(04 Marks)

Ed
5a. Explain the round ,obin pro..ss scheduling. (06 Marks)
io b. Three processes P1,'Pi, P3 with estimated completion time 10;, J, 7 ms respectively enters the
oj= ready queue togbtlier. Calculate Waiting Time (WT) and Turn Around Time (TAT) for each
:q process. Also calculate average WT and average TAT in SJF (Shortest Job First) algorithm.
o\! (08 Marks)
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c. Differentiate between threads and processes. (06 Marks)

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6 a. What is dead lock? Explain Coffman conditions favoring dead locks.
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G; (06 Marks)
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>,q b, ,, What is semaphore? Compare 'binary semaphore' and 'counting semaphore'. (06 Marks)
oo'
-bo i, Describe the role of device driver in the OS context. (08 Marks)
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:o 1 a. List down the features of simulator based debugging and also discuss the advantages of
o i simulator firmware debugging. (06 Marks)
\J< b. Explain the 'Boundary Scan' based hardware debugging. (08 Marks)
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o
c. Describe the role of 'Monitor program' in frmware debugging. (06 Marks)
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Write short notes on:
o a. RPC (Remote Procedure call).
b. PLD (Programmable Logic Devices).
c. Java for embedded development.
d. Object-OrientedModel. (20 Marks)
 USN 12E,C130

M.Tech. Degree Examination, Dec.2013 /Jan.20l4

VLSI Design Verification
:::

Time: 3 hrs. Max. Marks:100

Note: Answer any FIVEfull questions.

o
o
I a. Discuss the importance of verification in VLSI design. Why formal methods are a preferred
o way of verification? (10 Marks)
(!
b. How verification time may be reduced? (05 Marks)
c!
c. What is reconvergent model of verification? Give some examples. (05 Marks)

(J 2a.Describe1ittinqproceSS,withhelpoffollowingcode:
=()
! module abc (a, b, c); ":';""tt:'t":t
oX input a. b:
!,2
output c:
G,U reg c:
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ool
trca
if (a::2'b01) . '

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6$ c (: T'blj
ts() if 16: T'b0)
(.)tr
-O c : T',b0:
end module (10 Marks)
ou: b. Compare testing and verification. (05 Marks)
a= c. Briefly explain the model checking pto'Cess. (05 Marks)
oc)
60 3 a. Explain the terms:
botr i) FSM coverage"
ii) Statement coverage and
,6
iii) Transition coverage.
E6 Write a test for the following FSM. State any assumptions made.
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'Ca
OE
a-=l 4=l
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9E
ao
atE
!o (10 Marks)
5.v
>' (F b. What are code metrics? Give some examples. (05 Marks)
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C o.
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Discuss how ASIC verification is performed. (05 Marks)
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tr> 4a. For the following code, write verification code. Highlight its statement coverage.
o
module HA (a, b, c, s)
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input a, b;
-
o output c, s;
o
Z reg c, s;
xor (s, a, b);
o
a and (c, a, b);
end module Marks)
b. Give schematic of a typical RC timing model of a CMOS gate. (05 Marks)
c. What is unateness of a signal? Explain with suitable waveforms. (05 Marks)
 12EC130

5a. Justify the need for a verification specification document. Describe its functionality and
usage. (10 Marks)
b. Give an example of timing description of an output pin inNDLM format. (05 Marks)
c. What is the need for parasitic extraction and how it is used in back annotation? (05 Marks)

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'";;' 6 a. Discuss the effect of IR drop in signal integrity. (05 Mnrks)
b. Give an overview of design sign off process. (0b Mnrtg
$n
.,rtg: Discuss various timing parameters used in a static timing analysis. ,(05'Marks)
d. ::Describe setup and hold times. (05 Marks)
':':
, ':"

7a. Whflengging of variables is critical for drawing a ROBDD?

"'
'i''Jrl' (05 Marks)
b. Draw R@Op for the function f = abc + a'bc'+ ab'c + ab'c'
. .d' ,ir!
(10 Marks)
c. What are Slffi;polvers? ;' (05 Marks)
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'
8 Write short notes"@lury FOUR: 11,,,,,,.''\,,

a. Equivalence checkilig_. :.ti\

b.
c. Event based simulators ", i,
d. Design rules for digital VLSI.,:'', .

e. Waveform skew measurements .'-'...,

f. Antenna effects during plasma etch. ,,,,,4:'1 ", (20 Marks)

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,a '=t"'''
- tt''t_
::. :.: ::.

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I
USN tzF,.C12t

M.Tech. Degree Examination, Dec.2013 I Jan.20l4

Digital System Design Using Verilog
Time: 3 hrs. Max. Marks:100
, Note: 1. Answer anJ) FIVEfull questions.
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2. Assume suitable data wherever required.
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o 3. Mention top level blocks with input-output,poris.
L

E 1 a. Design the logic circuit shown in Fig.Q.1(a) for a night light that is lit only when the switch
is ON and the light sensor shows that it is dark. The logic is to be realized using 2:1 MUX
o
only. If there are three lamps in the room controlled using the same logic, how do you
OJ

modify the circnit shown in Fig.Q.1(a). (10 Marks)

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bo*

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tl
oo
tr€
.= c\
noo
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o=
-o Fig.Q.1(a)

b. With the help of a detailed flow chart, discuss VLSI design flow. Mention the importance of
a: each step in design flow. (t0 Marks)
oO
do
cat
2a. Ink jet printer have six catridge's for different colored ink: Black, Cyan, Magenta, Yellow,
Light Cyan and Light Magenta. A multibit signal in such a printer indicates selection of one
a6 of the colors. To print tlre colors stored in different drums drivers need to be enabled for
each of the colors.
'Ea
Os
i) Devise a minimal length code for the signal selection repre.senting each color.
ii) Design the logic shown in Fig.Q.2(a) that can enable the'corresponding driver based
sa on the multibit signal.
oj ii| If the number of colors are increased from 6 to 8, discuss the necessary changes to be
o= ,,m6de to the multibit signal and the logic. (10 Marks)
AE
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x .!i
>,t: .r.s*
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aJ=
t{l
*o GEN1RAL
tr>
VL
o LTBfiARY
!.) <
Jc'i t'uiv crr an;51 .
o Fig.Q.21a)
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b. Write a verilog code for l0:1 multiplexer using case statement. (10 Marks)
a
3 a. Design a 4-brt unsigned combinational multiplier using 4-bit adder. (10 Marks)
b. Discuss fixed point and floating point number format with example. (10 Marks)

I of2
 rzECl2t

4a. write verilog code for a positive flip-flop with clock enable, positive logic
edge triggered
asynchronous preset and clear and both u.tiu. high and active
low outputs' It is illegal for
boih preset and clear to be active together'
(10 Marks)
r ,
numbers a and.
Oerelop a datapath to perform coLplex multiplication of two complex
b.
represented u, u : u, i lal ana b
: br + jbi. The data path need to perform sequential!
.o-pt.* multiplication, *ith shared ,.roui.., and register to storeworking
intermediate. results'
p'i":.lPlt-'
its
Mention the control signals for the sequential datapath and discuss
{10 Marks)

54. rDesign a 64Kx 16bit composite -:::? using 16K x bit.memory component' (10 Marks)
.8
b. Dev, a verilog code foi a32 x 7 bit Rom, that can store the data shown
in Table Q.5(b).

able Q.5(b
Address Content Address Content
0 0000001 1111111 6
1 0000011 1.111 7
1 10

2 00001 1 1 1111100 8
3 0001111 1111000 9
"., 4 0011111 10-f5 0000000
;5 0111111 '"1,6,31 1010101
(10 Marks)
'.
l.r
the functionality of each modules'.
6 a. Discuss the internal architecture of'FP'GA'highlighting
. (10 Marks)
mention the
b. Define signal integrity, discuss giound bounce issue in signal integrity and
(10 Marks)
technique adopted to reduce ground bounce effect,

7 a. With a neat blockdiagr discuss the organization '' of a high performance embedded
(08 Marks)
computer with multipleltuses. '
b. Write instructions tlrat increment a 16-bit unsigned inte$er stored in memory. The address
of
the least signifieanr'bye is in 12. The most significant byt€ is.il the next memoti#iijl?}
,:.. i

c. Discuss ttrO. l ortance of cache memory, how is cache memo,rX,used in a embedded

processof.".'' i (06Marks)

g a. Discuis physical design flow and mention the importance of floor planning in PhYsical
(06 Marks)
ceslgn.
,Briehy discuss serial interface standards for I/O devices. (06 Marks)
b. (08 Marks)
, o,' Develop verilog code for 4-bit counter'
''........

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