Documente Academic
Documente Profesional
Documente Cultură
Metal-oxide-semiconductor memory capacitors composed of dual-layer nanocrystalline ZnO embedded zirconium-doped hafnium
oxide high-k film were fabricated, characterized, and compared with those with the single-layer nanocrystalline ZnO embedded
sample. Distinct layers of discretely dispersed nanocrystalline dots embedded in the amorphous high-k matrix were observed. The
nanocrystalline ZnO dots trap many electrons. The dual-layer sample not only drastically increases the charge storage density but
also improves the charge trapping speed due to the coulomb blockade effect. This is a potentially important gate dielectric
structure for high density, high speed nonvolatile memories.
© 2009 The Electrochemical Society. 关DOI: 10.1149/1.3276055兴 All rights reserved.
Manuscript submitted October 5, 2009; revised manuscript received November 25, 2009. Published December 31, 2009. This was
paper 762 presented at the San Francisco, California, Meeting of the Society, May 24–29, 2009.
Downloaded on 2015-06-09 to IP 132.239.1.230 address. Redistribution subject to ECS terms of use (see ecsdl.org/site/terms_use) unless CC License in place (see abstract).
H84 Electrochemical and Solid-State Letters, 13 共3兲 H83-H86 共2010兲
ing and retention characteristics.21 Assuming that the density of the embedded samples, i.e., ⌬VFB = 0.43 and 0.98 V, separately, which
nc-ZnO dots in the cross-sectional view is proportional to that in the corresponds to electron trapping densities 共Qe’s兲 of 1.34 ⫻ 1012 and
top view, the density of the dual-layer nc-ZnO sample is about 3.06 ⫻ 1012 cm−2, separately. The latter is comparable to that of the
2.38 ⫻ 1012 cm−2. The 3.7 nm thick amorphous hafnium silicate IL dual-layer nc-Si embedded SiO2 capacitor.23 Judging from the Qe of
formed between ZrHfO and Si has a low electron barrier height to the single-layer embedded sample and the nc-ZnO density, in aver-
Si.22 Separately, the top amorphous Al2O3 IL has a large energy age, each nc-ZnO dot stores about one electron, which is in the same
barrier, i.e., ⬃2.9 eV, which makes it difficult to inject electrons order of magnitude as that of nc-Si in SiO2.24,25 The increase in the
from the gate electrode to the dielectric layer or to leak electrons charge trapping density from the addition of the second embedded
from the trapped nc-ZnO site in the dielectric layer to the gate elec- layer is consistent with the increase in the number of the nc-ZnO
trode. The insets in Fig. 1d and e show that the nanodots in both dots in the dielectric structure. Figure 2a also shows that after a
single- and dual-layer embedded samples have periodic lattice −8 V stress, the C-V curve of the single-layer embedded sample
fringes spacing about 0.28 nm, which corresponds to the ZnO共100兲 slightly shifts to the negative direction, i.e., ⌬VFB = −0.15 V, which
layer. indicates the trap of a small amount of holes. It is not contributed by
Figure 2 shows C-V curves of 共a兲 single- and 共b兲 dual-layer nc- the ZrHfO part of the film, as shown in the inset of Fig. 2a. The low
ZnO embedded samples before 共fresh兲 and after being stressed for hole trapping capability is probably related to nc-ZnO properties.
10 ms with a constant gate voltage 共Vg兲 of −8 or +8 V. The C-V Defects, such as Zni and VO, in nc-ZnO are sub-conduction-band
curves were measured at 1 MHz over a small voltage range, i.e., trapping centers for electrons instead of holes.16-18 Therefore, only a
−2 to 1 V, so that the amount of charges introduced from the mea- small portion of the injected holes were retained at the nc-ZnO site.
surement process is negligible. The −8 V stress condition induced a For the dual-layer embedded sample, the negative shift of the C-V
hole-rich accumulation layer and the +8 V stress condition induced curve after a −8 V stress is negligible, as shown in Fig. 2b. Because
an electron-rich inversion layer near the Si/high-k interface. Charges the dual-layer embedded sample has a thinner top control dielectric
that obtained enough energy could be injected into the gate dielec- layer than the single-layer embedded sample, as shown in Fig. 1a
tric layer. The shift of the VFB of the sample’s C-V curve, i.e., and b, it may be easier to inject electrons from the Al electrode to
⌬VFB = VFB共after stress兲 − VFB共fresh兲, represents the amount of the dielectric film or to detrap holes from the nc-ZnO sites to the Al
charges trapped due to the gate stress process. Because the control electrode under the strong gate bias condition. However, more stud-
sample has a negligible C-V shift under either a +8 or −8 V stress ies are required to verify the exact mechanism.
condition, as shown in the inset of Fig. 2a, the contribution of the Figure 3 shows the C-V hysteresis curves of the control sample
ZrHfO part of the embedded sample to the total charge trapping is and the two nc-ZnO embedded samples with the gate being swept
minimum. Figure 2a and b shows that after a +8 V stress, the C-V from −2 to + 8 V 共forward兲 and then back to −2 V 共backward兲.
curve shifts to the positive direction in both single- and dual-layer The control sample shows very small C-V hysteresis corresponding
Downloaded on 2015-06-09 to IP 132.239.1.230 address. Redistribution subject to ECS terms of use (see ecsdl.org/site/terms_use) unless CC License in place (see abstract).
Electrochemical and Solid-State Letters, 13 共3兲 H83-H86 共2010兲 H85
Downloaded on 2015-06-09 to IP 132.239.1.230 address. Redistribution subject to ECS terms of use (see ecsdl.org/site/terms_use) unless CC License in place (see abstract).
H86 Electrochemical and Solid-State Letters, 13 共3兲 H83-H86 共2010兲
25. T. Z. Lu, J. Shen, B. Mereu, M. Alexe, R. Scholz, V. Talalaev, and M. Zacharias, 27. C.-H. Lin and Y. Kuo, ECS Trans., 16共5兲, 309 共2008兲.
Appl. Phys. A: Mater. Sci. Process., 80, 1631 共2005兲. 28. Y. Shi, K. Saito, H. Ishikuro, and T. Hiramoto, J. Appl. Phys., 84, 2358 共1998兲.
26. S. K. Samanta, P. K. Singh, W. J. Yoo, G. Samudra, Y.-C. Yeo, L. K. Bera, and N. 29. K. I. Han, Y. M. Park, S. Kim, S.-H. Choi, K. J. Kim, I. H. Park, and B.-G. Park,
Balasubramanian, Tech. Dig. - Int. Electron Devices Meet., 5, 170 共2005兲. IEEE Trans. Electron Devices, 54, 359 共2007兲.
Downloaded on 2015-06-09 to IP 132.239.1.230 address. Redistribution subject to ECS terms of use (see ecsdl.org/site/terms_use) unless CC License in place (see abstract).