3/13/2018 IBM unveils world’s first 5nm chip | Ars Technica

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IBM unveils world’s first 5nm chip

Built with a new type of gate-all-around transistor, plus extreme ultraviolet lithography.
SEBASTIAN ANTHONY - 6/5/2017, 7:23 AM

IBM's Nicolas Loubet, looking fairly awestruck by a wafer of the new 5nm chips. The ASML EUV machine used to etch the 5

IBM, working with Samsung and GlobalFoundries, has unveiled the world's first 5nm silicon chip. Beyond the usual power, performance, and density
improvement from moving to smaller transistors, the 5nm IBM chip is notable for being one of the first to use horizontal gate-all-around (GAA)
transistors, and the first real use of extreme ultraviolet (EUV) lithography.

GAAFETs are the next evolution of tri-gate finFETs: finFETs, which are currently used for most 22nm-and-below chip designs, will probably run out of
steam at around 7nm; GAAFETs may go all the way down to 3nm, especially when combined with EUV. No one really knows what comes after 3nm.

2D, 3D, and back to 2D

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3/13/2018 IBM unveils world’s first 5nm chip | Ars Technica
For the longest time, transistors were mostly fabricated by depositing layers of different materials on top of each other. As these planar 2D transistors
got shorter and shorter (i.e. more transistors in the same space), it became increasingly hard to make transistors that actually perform well (i.e. fast
switching, low leakage, reliable). Eventually, the channel got so small that the handful of remaining silicon atoms just couldn't ferry the electricity
across the device quickly enough.

FinFETs solve this problem by moving into the third dimension: instead of the channel being a tiny little
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2D patch of silicon, a 3D fin juts out from the substrate, allowing for a much larger volume of silicon. Transistors go 3D as Intel re-invents
Transistors are still getting smaller, though, and the fins are getting thinner. Now chipmakers need to the microchip
use another type of transistor that provides yet another stay of execution.

Enter GAAFETs, which are kind of 2D, but they build upon the expertise, machines, and techniques that were required for finFETs. There are a few ways
of building GAAFETs, but in this case IBM/Samsung/GloFo are talking about horizontal devices. The easiest way to think of these lateral GAAFETs is to
take a finFET and turn it through 90 degrees. Thus, instead of the channel being a vertical fin, the channel becomes a horizontal fin—or to put it
another way, the fin is now a silicon nanowire (or nanosheet, depending on its width) stretched between the source and drain.

In the case of IBM's GAAFET, there are actually three nanosheets stacked on top of each other running
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between the source and drain, with the gate (the bit that turns the channel on and off) filling in all the Intel forges ahead to 10nm, will
gaps. As a result, there's a relatively large volume of gate and channel material—which is what makes move away from silicon at 7nm
the GAAFET reliable, high-performance, and better suited for scaling down even further.

A beautiful series of transmission electron microscopy images showing the stages of building a GAAFET. This image nicely illustrates the improvem
IBM, Samsung, Global Foundries, et al.

Fabrication-wise, GAAFETs are particularly fascinating. Basically, you lay down some alternating stacks of
silicon and silicon-germanium (SiGe). Then you carefully remove the SiGe with a new process called
atomic layer etching (probably with an Applied Materials Selectra machine), leaving gaps between each
of the silicon layers, which are now technically nanosheets. Finally, without letting those nanosheets
droop, you fill those gaps with a high-κ gate metal. Filling the gaps is not easy, though IBM has seemingly
managed it with atomic layer deposition (ALD) and the right chemistries.

One major advantage of IBM's 5nm GAAFETs is a significant reduction in patterning complexity. Ever Enlarge / A side-on shot of the completed gate-
since we crossed the 28nm node, chips have become increasingly expensive to manufacture, due to the all-around transistors. Each transistor consists
added complexity of fabricating ever-smaller features at ever-increasing densities. Patterning is the of three nanosheets stacked on top of each
multi-stage process where the layout of the chip—defining where the nanosheets and other other, with the gate material all around them.
components will eventually be built—is etched using a lithographic process. As features get smaller and
more complex, more patterning stages are required, which drives up the cost and time of
producing each wafer.

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3/13/2018 IBM unveils world’s first 5nm chip | Ars Technica
IBM Research's silicon devices chief, Huiming Bu, says this 5nm chip is the first time that extreme ultraviolet (EUV) lithography has been used for front-
end-of-line patterning. EUV has a much narrower wavelength (13.5nm) than current immersion lithography machines (193nm), which in turn can
reduce the number of patterning stages. EUV has been waiting in the wings for about 10 years now, always just a few months away from commercial
viability. This is the best sign yet that ASML's EUV tech is finally ready for primetime.
Applied Materials

Enlarge / A few possible paths towards 5nm and 3nm transistors. (Top right shows GAA, but with vertical nanowires rather than the horizontal nanosheets discussed
here.)

So, how good are GAAFETs?

IBM says that, compared to commercial 10nm chips (presumably Samsung's 10nm process), the new
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5nm tech offers a 40 percent performance boost at the same power, or a 75 percent drop in power Beyond silicon: IBM unveils world’s
consumption at the same performance. Density is also through the roof, with IBM claiming it can first 7nm chip
squeeze up to 30 billion transistors onto a 50-square-millimetre chip (roughly the size of a fingernail), up
from 20 billion transistors on a similarly-sized 7nm chip.

GAAFETs don't necessarily have the 5nm node sewn up, though. As always with the semiconductor industry, chipmakers prefer to tweak existing
fabrication processes and transistor designs, rather than spending billions on deploying new, immature tech. Current silicon-germanium FinFETs will
probably get us to 7nm, and the use of exotic III-V semiconductors might take the finFET a step further to 5nm.

At some point, though, it probably won't be worth the time, cost, and complexity of producing ever-
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smaller transistors and chips. Someone will realise that much larger gains can be had by going properly IBM is trying to solve all of
3D: stacking dozens of logic dies on top of each other, connected together with through-silicon vias computing’s scaling issues with 5D
(TSVs). Intel has been looking at chip stacking to mitigate its slow progress towards the 10nm node since electronic blood

at least 2015. Maybe we'll soon see the fruits of that labour; though I doubt they'll be cooled
with electronic blood just yet.

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SEBASTIAN ANTHONY
Sebastian is the editor of Ars Technica UK. He usually writes about low-level hardware, software, and transport, but it is emerging science and the future of technology
that really get him excited.

EMAIL sebastian@arstechnica.co.uk // TWITTER @mrseb

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