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# CMOS Differential Amplifier

VDD

(7)
(1)
VG1
+
VID +
ID1 ID2
E+=VID/2

## VG1 VSS VG2 (10)

VSS
+
E-=-VID/2
VC VIC
VGS1 +
VGS2 (2)
VG2

ISS

VSS

(a) (b)

Figure 1. General MOS Differential Amplifier: (a) Schematic Diagram, (b) Input Gate Voltages
Implementation.

Figure 1(a) shows the schematic diagram of a typical differential amplifier. The differential input
is given by:

## VID = VG1 − VG2 = (VGS1 + VC ) − (VGS2 + VC ) --(1)

2I D1 2I D2
VID = VGS1 − VGS2 = (VGS1 − VTN ) − (VGS2 − VTN ) = − --(2)
β1 β2

VG1 + VG2
VIC = --(3)
2

## VG2 = VIC − VID / 2 --(5)

1
Figure 1(b) shows the implementation of the 2 gate voltages in terms of the differential and common mode
voltages. Its PSpice implementation using voltage controlled voltage source is given below:

VID 7 0 DC 0V
E+ 1 10 7 0 0.5
E- 2 10 7 0 -0.5
VIC 10 0 DC 0V

Two special cases of input gate signals are of interests : pure differential and pure common mode input
signals. Pure differential input signals mean VIC=0, from equation (4) and (5);

VG1 = VID / 2
VG2 = −VID / 2
This case is of interest when studying the differential gain of differential amplifier, see Figure 2(a). Pure
common-mode input signals mean VID=0, from equation (4) and (5);

VG1 = VIC
VG2 = VIC

This case is of interest when studying the common-mode gain of differential amplifier, see Figure 5(a).

## Assume both transistor drivers are matched, that is:

β1 = β 2 = β

2I D1 2I D2
VID = − --(6)
β β

β / 2VID = I D1 − I D2 --(7)

## The transistor currents satisfy the following equations:

I SS = I D1 + I D2 --(8)

I OD = I D1 − I D2 --(9)

I D1 = (I SS + I OD ) / 2 --(10)

I D2 = (I SS − I OD ) / 2 --(11)

## Substituting Eq(10) and Eq(11) to Eq(7)

β / 2VID = (I SS + I OD ) / 2 − (I SS − I OD ) / 2 --(12)

2
Normalizing by ISS

β I OD I
VID = ( 1 + − 1 − OD ) --(13)
I SS I SS I SS

## To simplify the equation, let

β I OD
x= VID , and y = --(14)
I SS I SS

## The equation reduces to:

x = 1+ y − 1- y

Solve for y,

x 2 = (1 + y) - 2 (1 + y)(1 − y) + (1 − y) = 2 - 2 1 - y 2

x2
1− y2 = 1−
2
x4
1− y = 1− x +
2 2

4
2
x
y 2 = x 2 (1 − )
4
The result is:

x2 x
y = x 1- , provided | |≤ 1 --(15)
4 2

## Substituting for x and y, one obtains

I OD β βVID 2
= VID 1 − --(16)
I SS I SS I SS 4

βVID 2 βVID 4
I OD = I SS − 2
--(17)
I SS 4I SS

1 1 βVID βVID 2 4

I D1 = I SS + I SS − 2
--(18)
2 2 I SS 4I SS

3
1 1 βVID βVID
2 4
2I SS
I D2 = I SS − I SS − , provided | VID |≤ --(19)
2 2 I SS 4I SS
2
β

2. Low Frequency Small Signal Equivalent Circuit With Pure Differential Input
Signal

(3) VDD

M3 M4
w=25.8u w=25.8u
(5)
l=5.4u l=5.4u

IO +2∆I
ID3 +∆I ID4 +∆I
M1
w=9.6u (6) M2
ID1 +∆I ID2 −∆I +
l=5.4u w=9.6u
VG1 VG2l=5.4u V
VSS VSS O
(1) (2)
+ -
VID/2 VC VGS2
VGS1
+
VID/2

ISS

(4) VSS

(a)

S3 S4
g ds3

g ds4
g m3

gm4v gs4

D3 D4

D1 D2

g ds1
gm1(v id/2) g ds2 gm2(-v id/2)
VC
S1 S2

(b)

4
Figure 2. Differential Amplifier Implementation: (a) Differential Amplifier with PMOS current
mirror load, (b) Small Signal Equivalent Circuit for Purely Differential Input Signal.

An active load acts as a current source. Thus it must be biased such that their currents add up
exactly to ISS. In practice this is quite difficult. Thus a feedback circuit is required to ensure this equality.
This is achieved by using a current mirror circuit as load, as in Figure 2. The current mirror consists of
transistor M3 and M4. One transistor (M3) is always connected as diode and drives the other transistor
(M4). Since VGS3=VGS4, if both transistors have the same β, then the current ID3 is mirrored to ID4, i.e.,
ID3=ID4.

The advantage of this configuration is that the differential output signal is converted to a single
ended output signal with no extra components required. In this circuit, the output voltage or current is
taken from the drains of M2 and M4. The operation of this circuit is as follows. If a differential voltage,
VID=VG1-VG2, is applied between the gates, then half is applied to the gate-source of M1 and half to the
gate-source of M2. The result is to increase ID1 and decrease ID2 by equal increment, ∆I. The ∆I increase ID1
is mirrored through M3-M4 as an increase in ID4 of ∆I. As a consequence of the ∆I increase in ID4 and the
∆I decrease in ID2 , the output must sink a current of 2∆I. The sum of the changes in ID1 and ID2 at the
common node VC is zero. That is, the node VC is at an ac ground, see Figure 2(b). From Eq(4) and Eq(5)
for pure differential input signal means the common-mode signal VIC is zero. That is, the input signals are
VG1=VID/2 and VG2=-VID/2. This is shown in Figure 2(a). The transconductance of the differential amplifier
is given by:

∆I O 2∆I ∆I ∆I
g mD = = = = = g m1
∆VID ∆VID ∆VID / 2 Vgs1

That is, the differential amplifier has the same transconductance as a single stage common source
amplifier.

5
G1 D1 D3=G3=G4 D2 D4
+

gm1(v id/2)
+ +
vgs3 =

g ds1

g ds3

g m3
V1=vid/2 vgs4 V2=vo
gm2 (v id/2) gm4v gs4 g ds4
- - g ds2
-
S1 S3 S2 S4
(a)

G1 D2 D4
+ +
V1=vid/2 V2=vo
2g m1 (v id/2)
- g ds2 g ds4 -
S1 S2 S4
(b)

G1 D2 D4
+ +
V1=vid
V2=vo
gm1v id
- g ds2 g ds4 -
S1 S2 S4

(c)

Figure 3. Differential Amplifier Operating in Purely Differential Input Signal: (a) Original Equivalent
Circuit, (b) Reduction to Two-port Network, and (c) Changing Input Port Variable to V1=Vid .

The derivation of the small signal equivalent circuit is shown in Figure 2. The simplification is
based on the symmetry of the circuit. In Figure 2(b), each transistor equivalent circuit is drawn. Figure 3(a)
redraws the equivalent circuit in Figure 2(b) in a form suitable for two-port analysis. The further reduction
is obtained after the two-port parameters are obtained.

From Figure 3(a), the following two-port variables and load are obtained.

YL = 0
V1 = VID /2
and
V2 = VO

I1 = 0 --(20)

## I 2 = -g m2 V1 + g m4 Vgs4 + (g ds2 + g ds4 )V2 --(21)

6
g m1
Vgs4 = - V1 --(22)
g ds1 + g ds3 + g m3

## Substitute eq(22) to eq(21)

g m1g m4
I 2 = -g m2 V1 - V1 + (g ds2 + g ds4 )V2
g ds1 + g ds3 + g m3
g m1g m4
= - (g m2 + )V1 + (g ds2 + g ds4 )V2 --(23)
g ds1 + g ds3 + g m3
= -2g m1V1 + (g ds2 + g ds4 )V2

## The resulting Y-parameter matrix is:

 0 0 
Y=
- 2g m1 g ds2 + g ds4 

## The dc voltage gain is,

V2 VO y 21 2g m1
A VD02 = = =− =
V1 Vid / 2 y 22 + YL g ds2 + g ds4

Instead of half differential input, dc gain with respect to full differential input is desired. That is,

V2 VO g m1 g m2
A VDO = = = = --(24)
V1 Vid g ds2 + g ds4 g ds2 + g ds4

7
VDD
(3)

M3 M4
w=25.8u w=25.8u
(5)
l=5.4u l=5.4u

I
IB=220uA
ID3
ID4 (6) O
M1 ID1 ID2 M2 +
w=9.6u w=9.6u
l=5.4u l=5.4u
VSS VSS Vo
VG1 (1) (2) VG2

-
(8) VC
VGS1 VGS2

ISS=220uA
(9)

M6 M5
w=21.6u w=21.6u
l=1.2u l=1.2u
(4) VSS

## Figure 4. The Complete Differential Amplifier Schematic Diagram

Figure 3(c) is the resulting two-port equivalent circuit. Except for the polarity this gain equation is identical
to that of the single NMOS inverter with PMOS current load. Figure 4 shows the complete differential
amplifier implemented using a pair of inverter amplifier with PMOS current load, and 200uA current
souce. The PSpice netlist is given below:

* Filename="diffvid.cir"
* MOS Diff Amp with Current Mirror Load
*DC Transfer Characteristics vs VID
VID 7 0 DC 0V AC 1V
E+ 1 10 7 0 0.5
E- 2 10 7 0 -0.5
VIC 10 0 DC 0.65V
VDD 3 0 DC 2.5VOLT
VSS 4 0 DC -2.5VOLT
M1 5 1 8 8 NMOS1 W=9.6U L=5.4U
M2 6 2 8 8 NMOS1 W=9.6U L=5.4U
M3 5 5 3 3 PMOS1 W=25.8U L=5.4U
M4 6 5 3 3 PMOS1 W=25.8U L=5.4U
M5 8 9 4 4 NMOS1 W=21.6U L=1.2U
M6 9 9 4 4 NMOS1 W=21.6U L=1.2U
IB 3 9 220UA
.MODEL NMOS1 NMOS VTO=1 KP=40U
+ GAMMA=1.0 LAMBDA=0.02 PHI=0.6
+ TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10
+ U0=550 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9
.MODEL PMOS1 PMOS VTO=-1 KP=15U
+ GAMMA=0.6 LAMBDA=0.02 PHI=0.6

8
+ TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10
+ U0=200 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9
.DC VID -2.5 2.5 0.05V
.TF V(6) VID
.PROBE
.END

The operating point current is determined by the source current ISS, which is split between the two PMOS
current loaded inverters. IDSQ1=IDSQ2=ISS/2, and similarly IDSQ3=IDSQ4=ISS/2. For the given differential
amplifier ISS=220uA. The voltage gain is computed as follows:

## β N1 = β N2 = K N1 ( WN1 / L N1 ) = (40E - 6)(9.6u/(5.4u - 2 * 0.5u)) = 87.3uA/V 2

β P3 = β P4 = K P3 ( WP3 / L P3 ) = (15E - 6)(25.8u/(5.4u - 2 * 0.5u)) = 87.95uA/V 2

## g m1 = g m2 = 2 β N1 I DSQ1 = 2(87.3E - 6)(110E - 6) = 138.59 umho

g m3 = g m4 = 2 β P3 I DSQ3 = 2(87.95E - 6)(110E - 6) = 139.1 umho

## g ds2 = λ DS2 I DSQ2 = λ N I DSQ1 = .02(110E - 6) = 2.2 umho

g ds4 = λ DS4 I DSQ4 = λ P I DSQ1 = .02(110E - 6) = 2.2 umho
g ds5 = λ DS5 I DSQ = λ P I DSQ5 = .02(220E - 6) = 4.4 umho

g m1 138.59E - 6
A VD ≈ = = 31.5
g ds2 + g ds4 2.2E - 6 + 2.2E - 6

9
The low frequency input resistance Rin = ∞. The output resistance Rout = 1/(gds2+gds4)= 1/(2.2E-6+2.2E-6)
=.2272M, see Figure 3(d), and the computation above. These calculations agree well with Pspice
simulation results of:

## **** SMALL-SIGNAL CHARACTERISTICS

V(6)/VID = 3.347E+01

## 3. Determination of the input common-mode range

10
VDD

Vgs3 Vgs4

VSD3 VSD4
M3
M4

VDG1
+
VG1 M1 M2 VG2
VSS VSS Vo
+ +
VIC VIC -
VGS1 VC
VGS2

ISS
M5
VGG
VDS5

VSS

S3 S4
g ds3

g ds4
g m3

gm4v gs4

D3 D4

D1 D2 +

g ds1
Vo
gm1v gs1 g ds2 gm2v gs2
VC
S1 -
S2

g ds5

Figure 5. Differential Amplifier with Purely Common-mode Input Signal: (a) Schematic Diagram,
and (b) Small Signal Equivalent Circuit.

The input common-mode range is the range of common-mode voltage Vic=VG1=VG2 in which all
the transistors are operating in saturation region. To determine this a purely common-mode input is applied
at both inputs, see Figure 5.

## 3.1 Maximum VG1 or VG2 Determination

As VG1 approaches VDD transistor M1 and M2 go into the triode region. VG1(max) is the value
of the input when it occurs. This can be determined from Figure 5 by writing the KVL equation from VDD
toward VG1.

11
VG1 = VDD − VSD3 − VDG1
= VDD − VSG3 − VDG1 , since D = G

2 | I DS3 |
VSG3 = (| VGS3 | − | VTP3 |)+ | VTP3 |= + | VTP3 |
β P3

2 | I DS3 |
VG1 = VDD − − | VTP3 | − VDG1
β P3

From Figure 5(a), VDG1 can be determined in term of the commonly known transistor voltages of M1.

## VDG1 = VDS1 - VGS1

or
VDS1 = VGS1 + VDG1

## VGS1 − VTN1 ≤ VDS1 = VGS1 + VDG1

That is,

− VTN1 ≤ VDG1

The minimum value of VDG1 is achieved when transistor M1 is on the threshold of saturation. That is,

− VTN1 = VDG1

The maximum input voltage is obtained when − VTN1 = VDG1 . That is,

2 | I DS3 |
VG1 (max) = VDD − − | VTP3 | + VTN1
β P3
--(25)
2 | I DS3 | I SS
= VDD − = VDD −
β P3 β P3

## 3.2 Minimum VG1 or VG2 Determination

12
As VG1 approaches VSS, M1 becomes cutoff. The minimum input voltage VG1 is determined when
M5 is no longer in saturation. This is obtained by writing the KVL equation from VSS to VG1.

## VGS5 − VTN5 ≤ VDS5

M5 is at verge of saturation when, VGS5 − VTN5 = VDS5 = VDS5(SAT)
That is, the minimum input voltage occurs when, VGS5 − VTN5 = VDS5(SAT) .

## VG1 (min) = VSS + (VGG − VSS − VTN5 ) + (VGS1 - VTN1 ) + VTN1

2I DS1
= VGG − VTN5 + + VTN1 --(27)
β N1
2I DS1 I SS
= VGG + = VGG +
β N1 β N1

## Ignoring the bulk bias effect.

Using the SPICE parameters for the differential amplifier implemented in Figure 4.
From Eq(25),
I SS
VG1 (max) = VDD −
β P3
β P3 = K P ( W3 / L 3 ) = (15E - 6)(25.8u/(5.4u - 2 * 0.5u)) = 87.95 uA/V 2
220E - 6
VG1 (max) = 2.5 − = 2.5 − 1.58 = 0.92 V
87.95E - 6
and from Eq(27),

I SS 220E - 6
VG1 (min) = + VGG = − 1.2 = 1.58 − 1.2 = 0.38 V
β N1 87.3

To guarantee that the differential amplifier stays on the linear region of operation, set common-mode signal
at half way the common-mode range. That is, VIC=[VG1(max)+VG1(min)]/2=[0.92+.38]/2=0.65.

4. Low Frequency Small Signal Equivalent Circuit With Pure Common-Mode Input
Signal

13
G1 D1 D3=G3=G4 D2 D4
+
+ + + +

gds3 +g m3
vgs3

gm4 v gs4
vgs1

g ds1
vgs4
gm1v gs1 gm2v gs2 g ds4
- g ds2
Vic
vo
S1 D5 Vc S2
g ds5

- - - -

S3 S5 S4

(a)

G1 D1 D3=G3=G4 D2 D4
+
+ +
gds3 +g m3
+

g ds4 +g m4
vgs3
vgs1
g ds1

## gm1v gs1 gm2v gs2

- g ds2
Vic
vo
S1 D5 Vc S2
g ds5
- - -

S3 S5 S4

(b)

G1 D1 I2 D3
g ds3 +gds4+g m3 +g m4

+ +
g ds1 +g ds2

2gm1v gs1
Vgs1
YL
V1=Vic VC
V2=vo
S1 D5 I2
g ds5
- -

S5 S3

(c)

Figure 6. Small Signal Equivalent Circuit: (a) Original Small Signal Equivalent Circuit, (b) Accounting for
Source Values and Polarities, and (c) Two-port Conversions.

Figure 5(a) shows the schematic when a purely common-mode input is applied at both inputs that
is, VG1=VG2 =VIC . If VIC increases both ID1 and ID2 increases. Their sum at the common node VC also
increases. Figure 5(b) shows that VC is not at ac ground, unlike the pure differential input signal case
shown in Figure 2(b). Due to signal symmetry when both inputs are the same, VDS3=VDS4. Since both G
and S of M3 and M4 are connected to each other, means VGS3=VGS4. M3 is diode connected with G and D
connected, means VGS3=VDS3. From these expressions, VDS4=VGS4 can be deduced. That is the voltage

14
across D and S of M4 can be labelled as VGS4, see Figure 6(a). The current source of M4 is therefore
reduced to conductance gm4, see Figure 6(b). Since VDS3=VDS4, the D3 and D4 can be connected together.
Figure 6(c) shows the final equivalent circuit after combining all components that are in parallel.

From Figure 6(c), the following two-port variables and load are obtained.

## YL = g ds3 + g ds4 + g m3 + g m4 = 2g ds3 + 2g m3

assuming g ds3 = g ds4 g m3 = g m4
V1 = VIC
and
V2 = VO

## The two-port current equations are derived to obtain the Y parameters.

I1 = 0
I 2 = (g ds1 + g ds2 )(V2 - VC ) + 2g m1 (V1 - VC )
= 2g m1V1 + (g ds1 + g ds2 )V2 - (g ds1 + g ds2 + 2g m1 )VC
1
VC = I2
g ds5
1
I 2 = 2g m1V1 + (g ds1 + g ds2 )V2 - (g ds1 + g ds2 + 2g m1 ) I2
g ds5
2g m1g ds5 (g ds1 + g ds2 )g ds5
I2 = V1 + V2
g ds1 + g ds2 + g ds5 + 2g m1 g ds1 + g ds2 + g ds5 + 2g m1

## The Y-parameter matrix is:

 0 0 
Y=  2 g g
m1 ds5 ( g ds1 + g ds2 )g ds5 
 g + g + g + 2g g ds1 + g ds2 + g ds5 + 2g m1 
 ds1 ds2 ds5 m1

 0 0 
= 2 g g
m1 ds5 2 g ds1 g ds5 
 2g + g + 2g 2g ds1 + g ds5 + 2g m1 
 ds1 ds5 m1

## The dc common-mode voltage gain is,

15
2g m1g ds5

− y 21 2g ds1 + g ds5 + 2g m1
A VC0 = =
y 22 + YL 2g ds1g ds5
+ 2(g ds3 + g m3 )
2g ds1 + g ds5 + 2g m1
− 2g m1g ds5
=
2g ds1g ds5 + 2(g ds3 + g m3 )(2g ds1 + g ds5 + 2g m1 )
g m1 g g
− − m1 − m1
g m3 g m3 g m3 −1
= ≈ ≈ ≈
g ds1 2g + 2g m1 1 + 2g m1rds5 2g m1rds5 2g m3 rds5
+ 1 + ds1
g m3 g ds5
assuming g m3 >> g ds3 .

* Filename="diffvic.cir"
* MOS Diff Amp with Current Mirror Load
*DC Transfer Characteristics vs VIC
VID 7 0 DC 0V
E+ 1 10 7 0 0.5
E- 2 10 7 0 -0.5
VIC 10 0 DC 0V
VDD 3 0 DC 2.5VOLT
VSS 4 0 DC -2.5VOLT
M1 5 1 8 8 NMOS1 W=9.6U L=5.4U
M2 6 2 8 8 NMOS1 W=9.6U L=5.4U
M3 5 5 3 3 PMOS1 W=25.8U L=5.4U
M4 6 5 3 3 PMOS1 W=25.8U L=5.4U
M5 8 9 4 4 NMOS1 W=21.6U L=1.2U
M6 9 9 4 4 NMOS1 W=100.8U L=3.6U
M7 9 9 3 3 PMOS1 W=3.6U L=3.6U
.MODEL NMOS1 NMOS VTO=1 KP=40U
+ GAMMA=1.0 LAMBDA=0.02 PHI=0.6
+ TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10
+ U0=550 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9
.MODEL PMOS1 PMOS VTO=-1 KP=15U
+ GAMMA=0.6 LAMBDA=0.02 PHI=0.6
+ TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10
+ U0=200 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9
.OP
.DC VIC -2.5 2.5 0.05V
.TF V(6) VIC
.PROBE
.END

16
1 1
A VCO = − =− = −0.01582
2g m3 rds5 2(139.1E - 6)(.2272E6)

## **** SMALL-SIGNAL CHARACTERISTICS

17
V(6)/VIC = -1.459E-02

## OUTPUT RESISTANCE AT V(6) = 2.386E+05

The goal of differential amplifier is to amplify the difference signal and to reject common-mode signal. A
figure of merit called common-mode rejection ration (CMRR) is defined as:

A VD 31.5
CMRR = = = 1991.15
A VC - 0.01582

18
VDD

C gs3 C gs4
M3 M4

C db3 C db4

Cgd4
C gd1
C db2
C gd2
VSS C db1 VSS CL
VG1 VG2
+ +
M1 VC M2
VGS1 VGS2

ISS

VSS
(a)
VDD

## M3 M4 C1=Cgd1+Cdb1+C db3 +Cgs3+Cgs4

C2=Cgd2+Cdb2 +Cdb4+CL
C3=Cgd4

(5) (6)

C3

(1) C1 (2) C2
VSS VSS
VG1 VG2
+ +
M1 VC M2
VGS1 (8)
VGS2

ISS

VSS
(b)

Figure 7. Parasitic Capacitances of Differential Amplifier Operating in Purely Differential Input Signal: (a)
Parasitic Capacitances of each Transistor, (b) Lumped Parasitic Capacitances.

Figure 7(a) shows all the parasitic capacitances of the differential amplifier with purely
differential input signals. Since both inputs are voltage sources, they are at ac ground when considering the
effects of gate capacitances. Figure 7(b) shows that there are basically three capacitances. These are:

## C1 = C gd1 + C db1 + C db3 + C gs3 + C gs4

C 2 = C gd2 + C db2 + C db4 + C L
C 3 = C gd4

19
C3
G1 D1 D3=G3=G4 D2 D4

gds1 +gds3+g m3
+ +

gds2 +g ds4
vid/2 vo
C2
C1
gm1(v id/2) gm2(v id/2) gm4v gs4
- -
S1 S3 S2 S4
=
C1=C gd1+Cdb1+C db3+C gs3+C gs4
C2=C gd2+Cdb2 +Cdb4+CL
C3=Cgd4

(a)

G1 D1 D3=G3=G4 D2 D4
Y3
+ I3 +
+
V1=Vid/2 Y1 V Y2 V2=VO
gs4
gm1(v id/2) - gm1(v id/2) gm4v gs4
- -
S1 S3 S2 S4
g m1 =g m2
(b)

Figure 8. High Frequency Small Signal Equivalent Circuit: (a) Small Signal Equivalent Circuit Showing
Lumped Capacitances, (b) Small Signal Equivalent Circuit Combining Capacitance and Resistance to

NOTE C3 is not a miller capacitance, it is connected between the outputs of the two inverter amplifiers,
and not between an output and an input terminals of an amplifier. C3 in this case is normally small and can
be ignored. Figure 8(b) shows that the three admittances are given by:

## Y1 = g ds1 + g ds3 + g m3 + sC1

Y2 = g ds2 + g ds4 + sC 2
Y3 = sC 3 = sC gd4

The two-port Y parameters are to be determined. Figure 8(b) shows that the two-port variables are:

YL = 0
V1 = Vid / 2
and
V2 = VO

20
I1 = 0
I 2 = Y3 (V2 - Vgs4 ) - g m1V1 + g m4 Vgs4 + Y2 V2
= -g m1V1 + (Y2 + Y3 )V2 + (−Y3 + g m4 )Vgs4
At node D3
I 3 + g m1V1 - Y3 (V2 - Vgs4 ) = 0
I 3 = Y1 Vgs4
Y1 Vgs4 + g m1V1 - Y3 (V2 - Vgs4 ) = 0
Solve for Vgs4
− g m1 Y3
Vgs4 = V1 + V2
Y1 + Y3 Y1 + Y3
− g m1 Y3
I 2 = -g m1V1 + (Y2 + Y3 )V2 + (−Y3 + g m4 )( V1 + V2 )
Y1 + Y3 Y1 + Y3
- g m1Y1 - g m1g m4 Y Y + Y1 Y3 + Y2 Y3 + g m1Y3
= V1 + 1 2 V2
Y1 + Y3 Y1 + Y3

## The Y-parameter matrix is:

 0 0 
Y =  m1 1 - g m1g m4
- g Y Y1 Y2 + Y1 Y3 + Y2 Y3 + g m1Y3 
 Y1 + Y3 Y1 + Y3 
 

For differential amplifier the assumption that Y3 or C3 is approximately 0 is valid. That is,

 0 0

Y = − g - g m1g m4 
 m1 Y2 
 Y1 

## The differential gain is given by:

21
g m1g m4 g
g m1 + g m1 (1 + m4 )
V2 − y 21 Y1 Y1
A VD2 = = = =
V1 y 22 + YL Y2 Y2
g m4
g m1 (1 + )
g ds1 + g ds3 + g m3 + sC1 g m1 (g ds1 + g ds3 + g m3 + g m4 + sC1 )
= =
(g ds2 + g ds4 + sC 2 ) (g ds1 + g ds3 + g m3 + sC1 )(g ds2 + g ds4 + sC 2 )
 C1 
(g ds1 + g ds3 + g m3 + g m4 )1 + s 
 g m1   g ds1 + g ds3 + g m3 + g m4 
=  
 g ds2 + g ds4  (g + g + g )1 + s C1 
1 + s
C2 

m3 
g ds2 + g ds4 
ds1 ds3
 g ds1 + g ds3 + g m3 
 C1 
1 + s 
 g m1   g ds1 + g ds3 + g m3 + g m4 
= 2 
g
 ds2 + g ds4   C1  C2 
1 + s 1 + s 
 g ds1 + g ds3 + g m3  g ds2 + g ds4 

The differential gain when the input voltage V1 is changed to VID is:

 C1 
1 + s 
VO  g m1   g ds1 + g ds3 + g m3 + g m4 
A VD = = 
Vid  g ds2 + g ds4  1 + s C1  C2 
   1 + s 
 g ds1 + g ds3 + g m3  g ds2 + g ds4 
s
(1 − )
= A VDO z
s s
(1 − )(1 − )
p2 p1
where :
g + g ds4
p1 = − ds2
C2
g ds1 + g ds3 + g m3 g
p2 = − ≈ − m3
C1 C1
g ds1 + g ds3 + g m3 + g m4 2g
z=− ≈ − m3
C1 C1

p1 << p2 << z

NOTE the differential voltage gain has pole-zero doublets. That is, the zero z is double that of the non-
dominant pole p2. The dominant (lowest frequency) pole p1 occurs at the output node. The above transfer
function can also be obtained by noting that each pole correspond to a node in the differential amplifier.

22
Each node is at a finite impedance with respect to ground. That is, each node there is a resistance Rn (or
conductance) and capacitance Cn to ground. To determine which poles are dominant (or more significant),
the impedance levels must be monitored. The parasitic capacitances Cn are of approximately the same
magnitude, but Rn usually vary considerably. When the resistance (conductance) is high (low), a dominant
pole is generated. The impedance levels are summarized in the follwing table:

## Node(From Netlist) Resistance Capacitance Pole

1 0 (ac ground) X
2 0 (ac ground) X
5 R5=1/(gds1+gds3+gm3) C1 p2=1/(R5C1)*
6 R6=1/(gds2+gds4) C2 p1=1/(R6C2)
8 0 (ac ground) X

## The derivation shows that the pole p2 create a zero doublet.

* Filename="diffreq.cir"
* MOS Diff Amp with Current Mirror Load
*DC Transfer Characteristics vs VID
VID 7 0 DC 0V AC 1V
E+ 1 10 7 0 0.5
E- 2 10 7 0 -0.5
VIC 10 0 DC 0.65V
VDD 3 0 DC 2.5VOLT
VSS 4 0 DC -2.5VOLT
M1 5 1 8 8 NMOS1 W=9.6U L=5.4U
M2 6 2 8 8 NMOS1 W=9.6U L=5.4U
M3 5 5 3 3 PMOS1 W=25.8U L=5.4U
M4 6 5 3 3 PMOS1 W=25.8U L=5.4U
M5 8 9 4 4 NMOS1 W=21.6U L=1.2U
M6 9 9 4 4 NMOS1 W=100.8U L=3.6U
M7 9 9 3 3 PMOS1 W=3.6U L=3.6U
.MODEL NMOS1 NMOS VTO=1 KP=40U
+ GAMMA=1.0 LAMBDA=0.02 PHI=0.6
+ TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10
+ U0=550 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9
.MODEL PMOS1 PMOS VTO=-1 KP=15U
+ GAMMA=0.6 LAMBDA=0.02 PHI=0.6
+ TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10
+ U0=200 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9
.AC DEC 100 1HZ 100000GHZ
.PROBE
.END

23
6. Common-Mode Frequency Response

24
VDD

M3
M4

## VG1 M1 VSS VSS M2 VG2

Vo
+ C sb1 C sb2 +
VIC VIC -
VGS1 VC
VGS2
Cgd5
Cdb5
VGG M5

VSS
VDD

M3
M4

+
VG1 M1 VSS VSS M2 VG2
Vo
+ +
VIC VIC -
VGS1 VC
VGS2

M5 CS
VGG

## VSS C S=C sb1+C sb2+C db5+Cgd5

Figure 9. Differential Amplifier Operating in Pure Common-Mode Input Signal: (a) All Parasitic
Capacitances at Common Node Vc, (b) Total Capacitances Across the Drain and Source of M5.

From the expression of the dc common-mode gain, it is primarily a function of gm3 and rds5. The
first order frequency response analysis can be simplified by ignoring all parasitic capacitances except the
capacitance CS across rds5, see Figure 9. That is rds5 is replaced by zds5 in the the common-mode gain
expression to account for frequency dependency.

25
rds5
z ds5 = (rds5 //C S ) =
1 + srds5 C S
−1 −1 − (1 + srds5 C S )
A VC = = =
2g m3 z ds5 rds5 2g m3 rds5
2g m3
1 + srds5 C S
where :
C S = C sb1 + C sb2 + C db5 + C gd5

* Filename="diffreqc.cir"
* MOS Diff Amp with Current Mirror Load
*DC Transfer Characteristics vs VIC
VID 7 0 DC 0V
E+ 1 10 7 0 0.5
E- 2 10 7 0 -0.5
VIC 10 0 DC 0.65V AC 1V
VDD 3 0 DC 2.5VOLT
VSS 4 0 DC -2.5VOLT
M1 5 1 8 8 NMOS1 W=9.6U L=5.4U
M2 6 2 8 8 NMOS1 W=9.6U L=5.4U
M3 5 5 3 3 PMOS1 W=25.8U L=5.4U
M4 6 5 3 3 PMOS1 W=25.8U L=5.4U
M5 8 9 4 4 NMOS1 W=21.6U L=1.2U
M6 9 9 4 4 NMOS1 W=100.8U L=3.6U
M7 9 9 3 3 PMOS1 W=3.6U L=3.6U
.MODEL NMOS1 NMOS VTO=1 KP=40U
+ GAMMA=1.0 LAMBDA=0.02 PHI=0.6
+ TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10
+ U0=550 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9
.MODEL PMOS1 PMOS VTO=-1 KP=15U
+ GAMMA=0.6 LAMBDA=0.02 PHI=0.6
+ TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10
+ U0=200 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9
.AC DEC 100 1HZ 100000GHZ
.PROBE
.END

26
The differential-mode voltage gain decreases with increasing frequency but common-mode voltage
increases. Therefore, CMRR decreases with increasing frequency.

## 7. Designing Differential Amplifier With Specified CMR

Given a common-mode range of –0.75 <= VIC <=0.75 , VGG=-1, ISS=IDS5=100uA, Lmin=5.4u,
∆V = VGS − VTN = 0.5 . Determine the size of each transistor in the differential amplifier circuit, see
Figure 4.

## 1. Determine the (W/L)5 to sink 100uA.

β N5 KN  W 
I DS5 = (VGS5 - VTN5 ) 2 =
  (VGS5 - VTN5 )
2

2 2  L 5
W 2I DS5 2I DS5
  = 2
=
 L  5 K N (VGS5 - VTN5 ) K N (VGG - VSS - VTN5 ) 2
2(100E - 6)  108u 
= 2
= 20 =  
(40E - 6)[-1 - (-2.5) - 1]  5.4u 

## 2. Determine (W/L)1 =(W/L)2 from VIC(min)=VG1(min) specification

From Eq(26),

27
VIC = VG1 (min) = VSS + VDS5(SAT) + VGS1 ≥ −0.75
VGS1 ≥ −0.75 − VSS − VDS5(SAT) = −0.75 − (−2.5) − 0.5 = 1.25
W W 2I DS1 2(50E - 6)  216u 
  =  = 2
= 2
= 40 =  
 L 1  L  2 K N (VGS1 - VTN ) (40E - 6)(1.25 - 1)  5.4 u 

## 3. Determine (W/L)3=(W/L)4 from VIC(max)=VG1(max) specification

From Eq(25),

2 | I DS3 |
VIC (max) = VG1 (max) = VDD −
β P3
β P3 W KP
| I DS3 |= (VDD - VG1 (max)) 2 =
  (VDD - VG1 (max))
2

2  L 3 2
W 2 | I DS3 | 2(50E - 6)  11.75u 
  = 2
= 2
= 2.177 =  
 L  3 K P (VDD - VG1 (max)) (15E - 6)(2.5 - 0.75)  5.4u 

The above is simulated using PSpice. The results agree well with the calculations.

* Filename="diffcmr.cir"
* MOS Diff Amp with Current Mirror Load
*DC Transfer Characteristics vs VIC
VID 7 0 DC 0V
E+ 1 10 7 0 0.5
E- 2 10 7 0 -0.5
VIC 10 0 DC 0V
VDD 3 0 DC 2.5VOLT
VSS 4 0 DC -2.5VOLT
M1 5 1 8 8 NMOS1 W=216U L=5.4U
M2 6 2 8 8 NMOS1 W=216U L=5.4U
M3 5 5 3 3 PMOS1 W=11.75U L=5.4U
M4 6 5 3 3 PMOS1 W=11.75U L=5.4U
M5 8 9 4 4 NMOS1 W=108U L=5.4U
VGG 9 0 DC -1V
.MODEL NMOS1 NMOS VTO=1 KP=40U
+ GAMMA=1.0 LAMBDA=0.02 PHI=0.6
+ TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10
+ U0=550 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9
.MODEL PMOS1 PMOS VTO=-1 KP=15U
+ GAMMA=0.6 LAMBDA=0.02 PHI=0.6
+ TOX=0.05U LD=0.5U CJ=5E-4 CJSW=10E-10
+ U0=200 MJ=0.5 MJSW=0.5 CGSO=0.4E-9 CGDO=0.4E-9
.DC VIC -2.5 2.5 0.05V
.TF V(6) VIC
.PROBE
.END

28
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