2017 International Conference on circuits Power and Computing Technologies [ICCPCT]

Multilevel inverter with reduced number of switches

Amol K. Koshti
PG Student
Department of Electrical Engineering
RIT, Islampur, 415414, India
amolkoshti463@gmail.com
A.R. Thorat
Assistant Professor
Department of Electrical Engineering
(HOP), RIT, Islampur, 415414, India
arun.thorat@ritindia.edu
P C Tejasvi. L.Bhattar
Assistant Professor
Department of Electrical Engineering
GCE, Karad,415124 India
bhattar.pctejasvi@gmail.com

Abstract— Multilevel inverters have been deliberated for an To meet the high power industry requirements for high
increasing number of application due to their high power voltage application IGBTS can be used but, it results in the
capability. This paper discusses about a multilevel inverter high voltage stress. IGBTS can be used for high voltage
topology with reduced number of switches, where sinusoidal application but unable to operate at high frequency and
pulse width modulation (SPWM) is used to produce a seven MOSFET can be used for high frequency application, but
level output voltage. Also an L-C Filter is used at the output of not available in high rating as that of the IGBT.
the inverter to suppress the ripples in the output and produce
the pure sinusoidal output voltage. Harmonics and switching There are three fundamental topologies of the multilevel
losses can be reduced by this topology. And reduction of Inverter.1) Diode clamped multilevel inverter
switches also reduces the cost. Multilevel inverters are used in
industry for medium and high voltage application. The main 2) Flying capacitor multilevel inverter
disadvantage of this multilevel inverter is that it require
3) Cascaded multilevel inverter(13)
complex gate driving circuit.
After that several topologies of the multilevel inverter
Keywords—Multilevel inverter (MLI), spwm, existing have been emerged so that output voltage waveform can be
Multi-level inverter topologies,THD improved.
II. POWER LEVEL
I. INTRODUCTION A. Circuit Configuration
Inverter is a power electronic device which has the ability Fig shows novel topology of the multilevel inverter, it
to convert DC power into AC power. Initially, inverters were consist of single voltage source connected to the capacitor
used to drive only lightning loads when grid gets voltage divider formed by connecting C1,C2,C3 in series.
disconnected. But, nowadays multilevel inverters are under These capacitors are connected to the intermediate stage of
the research and development in industry and found to be the H-bridge inverter formed by the four capacitor and four
more successful. Even though it is successful lot of diode. And this working design results in seven level output
technological advancement taken place with various new voltage (1).
topologies (3,4,8). The main reason behind using this
multilevel topology is that we convert DC into AC with fast
switching of DC signal which gives multiple levels of output
voltage and these levels turns out to be the staircase wave
which is nearly similar to sine wave (13).
In present industries scenario, there is tremendous use of
power equipment which causes harmonic pollution which
has become serious issue in power system so limit the
harmonics pollutions certain IEEE standards are applied
IEEE (1) standard 1547 and UL 1741. Multilevel inverters
have successfully established their place in industry therefore
it can be considered as the mature technology. Now these can
be commercialized as the modified product and can be used
in the industry application like compressors, extruders,
pumps, fan, grinding mills, rolling mills, conveyors, crushes,
mine hoists, reactive power compensation, high-voltage
direct current (HVDC) transmission, hydro pumped storage,
wind energy conversion.
Fig1: Seven level inverter topology

978-1- 5090-4967- 7/17/$31.00 © 2017 IEEE

 2017 International Conference on circuits Power and Computing Technologies [ICCPCT]

IV) Capacitor C3 supplies energy to the load through the

switch S7, S6 and S2 and produces the output voltage
B. Modes of Operation V0=-Vdc/3

I) Capacitor C1, supplies energy to the load through

S1, S5 and S8 which produces the output voltage
level of Vdc/3

V) Capacitor C3,C2 supplies energy to the load through

S3, S7 and S6 and S2 to produce the output voltage
Of V0=-2Vdc/3

II) Capacitor C1 and C2 now supplies energy to the load

at the end of the H-bridge inverter through the
intermediate bridge through the S1,S5,S8 and S4 to
produce the output voltage of 2Vdc/3.

VI) Capacitor C1,C2 and C3 supplies energy to the load

to produce the output voltage of V0=-Vdc. Through
the S1, S7,S6 and S2.

III) Now, capacitor C1,C2 and C3 supplies energy to the

load through H-bridge inverter through intermediate
bridge formed by the four diode and four MOSFETS
through the S1,S5,S8 and S2 to produce the output
voltage of V0=Vdc.

VII) To produce the output voltage of V0=0, S7 and S5

Are turned on as shown below.
Above circuit diagrams shows functioning for positive
Sequence. And for negative sequence is given below.
 2017 International Conference on circuits Power and Computing Technologies [ICCPCT]

A M P L IT U D E
0

-1

-2
IIISWITCHING TABLE

Output Switching Combinations -3

0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02

voltage(V) S1 S2 S3 S4 S5 S6 S7 S8 TIME

Fig 2-Sine wave comparison with triangular carrier waves

Vdc/3 on off off off on off off on

2Vdc/3 on off off off on on off on The results obtained from the comparison of these two
waves are given below.
Vdc on on off off on off off on
1) If Vsin< 0 and Vsin>Vtri2 then S2 is turned on
-Vdc/3 off on off off off on on off 2) If Vsin>Vtri4 then S4 is turned on
3) If Vsin<Vtri8 then S7 is turned on
-2Vdc/3 off on on off off on on off
4) If Vsin>Vtri8 then S8 is turned on
-Vdc on on off off off on on off 5) Vsin>0 and Vsin<Vtri1 then S1 is turned on

0 off off off off on off on off 6) Vsin< Vtri3 then S3 is turned on
7) Vsin>Vtri6 then S5 is turned on
8) Vsin< Vtri6 then S6 is turned on.
1

0.5

IV. APPLICATION OF SPWM 0

0.5

Sinusoidal pulse width modulation is such a technique where 0

number of triangular carrier waves can be compared with the 1

reference sinusoidal wave and intersection of these two 0.5

0
waves results in the pulse width and these pulse widths are 1

given to the respective switches and according to the 0.5

requirement of the output. The no of triangular carrier waves 0

used are depends upon the no of switches used in the circuit 1

(11). 0.5

The figure below shows no of triangular carrier waves are 1

placed to compare with reference sine wave. 0.5

0
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
Time

Fig3: SPWM output Result

 2017 International Conference on circuits Power and Computing Technologies [ICCPCT]

TABLE 1:. COMPARISON TABLE VII. MATLAB RESULTS

Proposed Diode- Capacitor- Cascaded- 500

400
clamped clamped multicell 300

200
Input 1 1 1 3 100

A m p lit u d e
Sources 0

-100
Input 3 6 2 3 -200

capacitors -300

-400

Clamped 0 0 5 0 -500
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08
Capacitors Output Voltage

Power 8 12 12 12 4

Switches 3

Diode 4 10 0 0 1

A m p lit u d e
0

-1

-2

-3
Above table compares the proposed topology with the -4

available three topologies and shows that same level of -5

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08
out- put can be generated using proposed topology. Third Output Current

row in above table shows that power switches Fig 5: waveform of output voltage and current without
Requirement for existing three topologies it requires 12 Filter
Switches and for the proposed topology it requires 8
Switches for the same level of output. It means four
Switches are reduced.

VI. MATLAB SIMULATIONS

Fig 6 :Voltage THD without filter

Fig5 shows FFT analysis of the output voltage and current

waveforms and fig6 shows the voltage THD at the output
side.

Fig 4: simulation of proposed topology

 2017 International Conference on circuits Power and Computing Technologies [ICCPCT]

400

300 VIII.CONCLUSION
200

100 The topology of this MLI uses less switches than that of the
A m p litu d e

0
existing three types of multilevel inverter so the main idea
-100
of this topology is to reduce the number of power switches
-200
and produce same level of output as compared to the
-300

-400
traditional multilevel inverter which can be proved for seven
4
Output Voltage level inverter.Reducing the number of switching devices the
3
cost can be reduced and switching losses can be
2 laminated.This
topology is simulated in MATLAB and results can be
A m p li t u d e

0 obtained.
-1

-2

-3

-4
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08
Output Current
IX.REFERENCES
Fig 7: Output voltage and current after connecting filter
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