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# Current Mirrors BJT Current Mirror

• Used extensively in analogue integrated circuits for biasing, and as • Basic BJT Current Mirror:

IREF I

IREF I QREF

QREF

## • For matched devices:

-1
• For matched devices (K = KREF, Vt = VtREF), I = IREF and the I = IREF.(1 + 2/) (4.2)
OUTPUT CURRENT “MIRRORS” the INPUT CURRENT
Base currents lead to a small discrepancy between I and IREF, which
• More generally, FETs fabricated monolithically will have the same is known as the FINITE  ERROR
Vt, but may have different K values depending on their geometries:
• For transistors identical apart from junction area:
 I = IREF.(K/KREF) (4.1a)
I  IREF.(A/AREF) (4.3)
= IREF. (W/L) (4.1b)
(W/L)REF
• Multiple sources from a single reference - notation:
where we have used K = (Cox e/2).(W/L)

## • Multiple current sources can be derived from a single reference:

IREF I1 I2 I3

IREF I1 I2 I3
QREF

QREF

EE1&ISE1 Analogue Electronics 2008/2009 - Part 4 ASH 1 EE1&ISE1 Analogue Electronics 2008/2009 - Part 4 ASH 2
Widlar Current Sink Wilson Current Mirror

## • Good for generating small currents A clever circuit!

IREF I
INPUT SIDE OUTPUT SIDE
IREF I
Q3

QREF

RE
Q1 Q2

## • Reduced finite  error:

We can easily make exp(-REI /VT) << 1, so circuit can generate small 2 -1
output currents from a relatively large reference I  IREF.(1 + 2/ ) (4.5)

Avoids using large resistor values, so useful in IC design • Increased small-signal output resistance:

Ro  ro/2
• RE also increases the small-signal output resistance:
(proof is very messy!)
Ro  [1 + gm(RE//rbe)] ro

## (cf basic current mirror, where Ro = ro)

EE1&ISE1 Analogue Electronics 2008/2009 - Part 4 ASH 3 EE1&ISE1 Analogue Electronics 2008/2009 - Part 4 ASH 4
Differential Amplifiers The Differential Pair
Preamble
VCC
• Consider Op-Amp as an example:
RC RC

## VCC VOUT1 VOUT2

+I/P + v+ vo
Ro
O/P vd Ri Avd ~ VIN1 Q1 Q2 VIN2
-I/P - v-
VE
VEE
Op-Amp CCT Symbol Commonly used Macromodel I

## • Ideally, open-cct output voltage is given by:

• If transistors are matched, then:
vo = A(v+ - v-)
IC1 = I/[1 + exp(-VD/VT)] (4.6a)
• But in practice:
IC2 = I/[1 + exp(VD/VT)] (4.6b)
vo = Ad(v+ - v-) + Acm(v+ + v-)/2
where VD = (VIN1 - VIN2) is the DIFFERENTIAL I/P VOLTAGE
where:

IC2 /I IC1 /I

## • Why are differential amplifiers useful?

0.5
• Differential input allows greater flexibility in CCT design
(see CCTs & Signals Course)

## • Rejection of common mode voltage is important in signal

conditioning VD /VT
-10 -8 -6 -4 -2 0 2 4 6 8 10

EE1&ISE1 Analogue Electronics 2008/2009 - Part 4 ASH 5 EE1&ISE1 Analogue Electronics 2008/2009 - Part 4 ASH 6
Differential Pair Differential Pair with Active Load
Small-Signal Analysis (NB this is as hard as it gets!)
VCC

Q3 Q4
RC RC
vout1 vout2 VOUT

gmvbe1 gmvbe2
rbe ro ro rbe VIN1 Q1 Q2 VIN2
vd /2 ~ ~ vd /2
ve

I
NB: Common Mode I/P signal voltage = 0
Differential I/P signal voltage = vd
• SSEC:

## • Under these conditions ve = 0 (this follows from symmetry), and each

“half-circuit” can be treated as a C-E stage
Q3, Q4 1/gm ro
ic1  ic1

vout
• SINGLE-ENDED DIFFERENTIAL GAIN gmvbe1 gmvbe2
(output taken between Q1’s collector and ground) rbe ro ro rbe vd /2
vd /2 ~ ~
ve
Ad = vout1 /vd = -gm(ro//RC)/2 (4.7a)
Q1 Q2
NB: Factor of 2 appears here because each side sees only half of the
differential input voltage
• Current mirror provides a high load resistance for Q2, AND allows us to
combine signal currents from Q1 and Q2 into a single output
• DOUBLE-ENDED DIFFERENTIAL GAIN
• Assuming ve = 0 (now only approximately true), the SINGLE-ENDED
(output taken between collectors)
DIFFERENTIAL GAIN is given by:
(vout1 - vout2) /vd = -gm(ro//RC) (4.7b)
Ad = vout /vd = gm(ro//ro) = gmro/2

## NB: Ad = VA/2VT, so if VA = 100 V, Ad  2000 !!

EE1&ISE1 Analogue Electronics 2008/2009 - Part 4 ASH 7 EE1&ISE1 Analogue Electronics 2008/2009 - Part 4 ASH 8
Common-Collector Amplifier Emitter Follower - a Closer Look
or Emitter Follower
VCC

VCC
Source

IIN RS
vS ~ O/P
IOUT
VIN
VOUT RS + rbe
Ro = ______
(1 + )
RS rbe
ib  ib Ro
• Characterised by: vS ~ vS ~

•  UNITY VOLTAGE GAIN:

VOUT = VIN - VBE • New output resistance is simply the total resistance in base circuit
divided by (1 + )
 VIN - 0.7 (when transistor active)
This is the RESISTANCE REFLECTION RULE
• HIGH CURRENT GAIN:

IOUT = ( + 1)IIN
• Alternatively:

Ro = re + RS/(1 + )

## re is the small-signal resistance seen when looking into the emitter

with the base grounded

## • Key Point: Effective output resistance of the source is reduced

EE1&ISE1 Analogue Electronics 2008/2009 - Part 4 ASH 9 EE1&ISE1 Analogue Electronics 2008/2009 - Part 4 ASH 10
Push-Pull Output Stages Push-Pull Output Stages
Class B Class AB

+VCC +VCC

Q1 Q1
VIN VOUT
VIN VOUT
Q2

Q2
-VCC

-VCC
• Q1 “PUSHes” current into load when VIN > +0.7 V

• Q2 “PULLs” current from load when VIN < -0.7 V • Bias sources ensure at least one transistor is conducting at all times, so
cross-over distortion is virtually eliminated
BUT:
• Bias current at VIN = 0 can be relatively small, so quiescent power
• When |VIN| < 0.7, both transistors are OFF ! dissipation can be low
 CROSS-OVER DISTORTION • Emitter resistors provide bias stabilisation, and prevent thermal
runaway

EE1&ISE1 Analogue Electronics 2008/2009 - Part 4 ASH 11 EE1&ISE1 Analogue Electronics 2008/2009 - Part 4 ASH 12
Class AB Output Stages Class AB Output Stages
Practical Circuits (1) Practical Circuits (2)
+VCC
+VCC
I1 R1
I1 I3
R1
Q3
Q3
Q1
Q1 R3
R3 VIN -VCC VOUT IOUT
VIN VOUT
+VCC
Q2
Q4
Q4
R2
R2
-VCC
-VCC
 VBEs of Q1, Q2 provide bias sources for output transistors, as for
 Diode-connected transistors Q1, Q2, in conjunction with R1 and R2, previous configuration. HOWEVER, Q1 and Q2 now also provide
provide bias sources for output transistors Q3, Q4. current gain, reducing input current requirements (and hence loading
NB: Q1, Q2 could be replaced by diodes of preceding stage)

 Assuming Q1/Q2 and Q3/Q4 are COMPLEMENTARY (i.e. matched)  Quiescent analysis for VIN = 0 is same as for previous configuration
PAIRS, VOUT = 0 when VIN = 0 from symmetry. In this case, comparing
upper (or lower) half of circuit with Widlar current sink (see page 3), Output voltage swing (both configurations):
quiescent currents satisfy:
 Maximum voltage at output corresponds to situation where current in
I3exp(I3R3/VT) = NI1 (4.9) Q1 has dropped to essentially zero, and all of I1 flows into base of Q3.
Output current in this case satisfies:
when VIN = 0. Here N = IS3/IS1 is ratio of saturation currents in output
stage and bias stage transistors IOUT [RLoad + R3 + R1/(1+)] + VBE3 = VCC

## Minimum output voltage obtained by similar analysis in lower half of

circuit

EE1&ISE1 Analogue Electronics 2008/2009 - Part 4 ASH 13 EE1&ISE1 Analogue Electronics 2008/2009 - Part 4 ASH 14
Class A Output Stage A Multistage Amplifier
+VCC

+12 V
VIN
Q1 2.5 k
4 k
20 k 20 k
VOUT IOUT Q5

I Q3 Q4
VIN+
Q1 Q2 Q6
-VCC

 Both output transistors (Q1 and current source) conduct all the time VIN-

VOUT
 No cross-over distortion (good)
 High power dissipation (not so good!) 28.25 k
12.7 k 4 k
Q8 Q9
Output voltage swing (assuming no thermal limiting): Q7 See Note

-12 V

##  Lower limit given by VOUT = -IRLoad unless limited by output voltage

range of current source

EE1&ISE1 Analogue Electronics 2008/2009 - Part 4 ASH 15 EE1&ISE1 Analogue Electronics 2008/2009 - Part 4 ASH 16
ANALOGUE ELECTRONICS
PROBLEMS 4

1. Figure Q1 shows a current-steering circuit with an input reference current IREF and N
output currents I1, I2 ..... IN. Assuming matched transistors, and neglecting the effects of
small-signal output resistance, show that the output currents are given by:

I1 = I2 = . . = IN = IREF/[1 + (N + 1)/]

For  = 100, find the maximum number of outputs if the finite beta error must not exceed
10 %.

IREF I1 I2 IN

QREF

Figure Q1

2. (a) The circuit below (Widlar Current Sink) is to be used to generate a constant current of
I = 20 µA. If the maximum allowable resistor value is 10 k, calculate the values of R1
and R2 that will give the correct output current with minimum power dissipation. (Neglect
base currents)

(b) What value of R1 would be required if the circuit were a simple current mirror (i.e.
one in which R2 = 0)?

12 V

R1 I

Q1 Q2

R2

## EE1&ISE1 Analogue Electronics 2008/2009 - Problems 4 ASH 1

3. Show that for a Wilson Current Mirror (see page 4.4 of lecture notes) the output current I
is given by:

## I = IREF [1 + 2/(2 + 2)]-1

where IREF is the input current. Hence show that the finite beta error (IREF - I) is smaller
than that of a simple current mirror by a factor of roughly .

4. Figure Q4 shows a BJT differential amplifier, biased with a simple current mirror. By
assuming that base currents are negligible, and by making any other reasonable
assumptions, determine the values of the nodal voltages VE, VOUT1 and VOUT2 under the
following conditions: (a) VIN1 = VIN2 = 0, and (b) VIN1 = 1 V, VIN2 = -1 V.

If a common-mode voltage VIN is applied to both inputs, over what range can VIN vary
while maintaining all four transistors in the active region of operation?

+12 V

20 k 20 k

VOUT1 VOUT2

VIN1 Q1 Q2 VIN2

VE

28.25 k

Q3 Q4

-12 V

Figure Q4

5. Draw a small-signal macromodel for the amplifier in Figure Q4, assuming single-ended
operation, and assign values to the small-signal parameters Ad (differential gain), Ri
(differential input resistance) and Ro (output resistance). Assume a  value of 100.

## EE1&ISE1 Analogue Electronics 2008/2009 - Problems 4 ASH 2

6. (a) For the circuit in Figure Q6, calculate the emitter bias current at VBIAS values of 2 V, 5
V and 8 V. In each case, assume the base current is negligible.

(b) For the same three values of VBIAS, calculate the output resistance of the
source/follower combination (i.e. everything except the load), and hence determine the
the linearity of the emitter follower configuration?

+10 V

Source
10 k
vS ~

VBIAS 1 k

Figure Q6

7. Show that the small-signal voltage gain of a common-emitter amplifier with emitter and
collector resistors RE and RC may be written as:

Av = - RC/(re + RE)

## where re = VT/IE is the small-signal emitter resistance of the transistor.

NOTE: this expression for Av is particularly useful; it tells us that the voltage gain is
roughly equal to the ratio of the total resistance in the collector circuit (RC) to the total
resistance in the emitter circuit (re + RE).

8. (a) Figure Q8 overleaf shows the circuit of a simple operational amplifier. By neglecting
base currents, and assuming VBE  0.7, determine the values of all the quiescent voltages
and currents when VIN+ = VIN- = 0.

(b) By dividing the circuit into four stages, and constructing a small-signal macromodel
for each stage, determine the overall differential gain of the amplifier. Assume  = 100
for all transistors.

NB: you should already have the necessary macromodel parameters for the first stage
from Question 5.

## EE1&ISE1 Analogue Electronics 2008/2009 - Problems 4 ASH 3

+12 V

2.5 k
4 k
20 k 20 k
Q5

Q3 Q4
VIN+
Q1 Q2 Q6

VIN-

VOUT

28.25 k
12.7 k 4 k
Q8 Q9
Q7 See Note

-12 V
Note: Q9 has 4x the area of Q7 and Q8, so IC9 = 4IC8

Figure Q8

1 N = 10
2 (a) R1 = 10 k, R2 = 5.04 k; (b) R1 = 565 k
4 (a) VE = -0.7 V, VOUT1 = VOUT2 = 8 V; (b) VE = 0.3 V, VOUT1 = 4 V, VOUT2 = 12 V;
Common Mode Voltage Range -10.6 V  VIN  +8 V
5 |Ad| = 79.2, Ri = 25.25 k, Ro = 20 k
6 (a) IE = 1.3, 4.3, 7.3 mA for VBIAS = 2, 5 and 8 V
(b) Ro = 118.2, 104.8, 102.4  and vL/vS = 0.894, 0.905, 0.907
8 (a) IE1 = IE2 = 0.2 mA, IE3 = IE4 = 0.8 mA, IE5 = 1 mA, IE6 = 3 mA
(b) Stage 1: Diff amp with parameters as in Q5
Stage 2: Diff amp with |Ad| = 63.4, Ri = 6.31 k, Ro = 4 k
 Stage 3: C-E amp with Av = -4.98, Ri = 255 k, Ro = 12.7 k
Stage 4: Emitter follower; Ro (w/o 4 k) = 134  when driven by Stage 3