PICTURE-IN-PICTURE PROCESSOR
(Part 1 )
Opinion is divided on the subject. Some say it's extremely
useful, while others hold that it is only for restless TV addicts.
Picture-in-picture (PIP) is a feature found on only the most
expensive of television sets. The set-top PIP processor
described here adds double viewing to any TV set having a
SCART socket with video and RGB inputs. The second video
source can be a video tape recorder, a satellite TV tuner, a
camera, or even a video disk player.
Design by W. Sevenheckd.
T HE fans claim that PIP is not just
high-tech fancy stuff. b u t a n ex-
tremely useful extension of the TV set's
features. For example. by using PIP.
you never get back too late to a film
which was interrupted for a commer-
cial break. That is. assuming that you
started zapping across the other chan-
nels when the film was suddenly inter-
rupted for the latest on washing
powder or toothpaste. When one of the
other channel happens to be interest-
ELEKTOR ELECTRONICS OCTOBER 1995
ing too. you may well forget about your
film after a few minutes. With the PIP
processor that can not happen be-
cause the small inset picture tells you
exactly when the commercials end and
the channel is safe to return to. Switch
from inset to large screen. and you are
back with your film again.
The use of the inset picture is not
restricted to TV signals only. It is pos-
sible, for instance, to 'PIP' a camera
signal for surveyance applications, for
instance. to watch the children's bed-
rooms, the driveway. etc.
The external PIP processor de-
scribed here requires two video signal
sources. That is not a n unusual re-
quirement. because top-of-the range
TV sets also have two built-in TV tuner
sections to enable their PIP system to
work. Fortunately, many owners of a
TV without a PIP already have their
second TV tuner: the one inside the
video cassette recorder (VCR). The PIP
processor described here is simply in-
serted in the SCART link between the
VCR and the TV set. It offers all fea-
tures offered by a very sophisticated
and highly integrated PIP processor IC.
In contrast with high-end TV sets of-
fering PIP. the inset picture may be po-
sitioned a t any location on the screen.
while the size. brightness. colour set-
tings and frame are also freely pro-
grammable to suit your preferences.
The only condition is that your TV set
has a SCAHT socket with RGB and
Fast Blanking inputs.
Block d i a g r a m
The block diagram in Fig. 1 shows
that combining two video sources is
not a t all simple. The main problem is
to keep the two pictures synchronized
to each other. his function is per-
formed by the 'heart' of the circuit, the
PIP processor type
~ ~ ~ 9 1 8 and 8 - the
3 ~associated A-D
converter type S ~ A 9 1 8 7 - z x(both from
Siemens Components). Apart from the
synchronization, the PIP IC core also
ensures that the 'small' picture is inset
a t the proper position in the large
(main) picture.
The core of the circuit requires a
composite video (CVBS) signal sup-
plied by the PIP. a s well a s synchro-
nization signals supplied by the two
video sources. These functions are car-
ried out by a number of 'smaller' ICs: a
PAL decoder type TDA4510, a base-
band delay circuit type TDA4661. and

Fig. 1. Block diagram of the PIP processor. The core is formed by the Siemens SDA9188-3X which compresses the inset picture, and enables
it to appear synchronized in the 'parent' picture.
two horizontal/vertical synchroniza-
tion separators type TDA2579B. The
RGB outnut sienals arrive a t the RGB
U
pins of the SCART connector on the TV
set via a type TEA51 14A RGB switch-
.. rirruit.
inu
. - - - - - ~ - The
-- -~- ~ status
~~~ information
supplied by the PIP is also used a s a
switching signal.
A microcontroller type 87C51 trans-
lates commands received from a 'local'
keyboard or a n infrared remote control
into t2C format, and also determines
the mode of operation of the PIP core.
Data is stored in a non-volatile pro-
gram memory formed by a n EEPROM
type 24C02. The status signal gener-
ated by the PIP processor also controls
a n analogue multiplexer (MUX,
74HCT4053). which determines the
parent picture/inset picture assign-
ment of the two video sources. The
parent picture is the main, large. pic-
ture. The inset picture is the small pic-
ture (sometimes called PIP by
convenience). In video recorder play-
back mode. the T V picture becomes
the inset picture, and the VCR picture,
ELEKTOR ELECTRONICS OCTOBER 1995
PICTURE-IN-PICTURE PROCESSOR (PART I )
the parent picture. All settings can he
checked with the aid of ten LEDs.
~ h ,.ideo signal paths
The full circuit diagram of the PIP
processor is given in'kig. 2. While the
audio pins of the SCAKT sockets are
simply interconnected, the video sig-
nals arc routcd to the PIP processor via
pin 20 of K, (video recorder) and pin 20
of K2 (TV set]. and first anive a t the
video multiplexer (MUXI. The video
switch type TDA2014A is only used a s
a huffer/splitter. The analogue multi-
plexer type 74HCT4053 switches ei-
ther the VCR signal or the TV signal to
the input buffer, pin 3. This signal is
buffered and re-appears a t pin 2. The
VCR signal. on the other hand. is am-
plified by a factor of 2 [independent of
the position of the MUXI. and fed to
the video input of the TV set (pin 19 of
SCART socket KZ).The video signal at
the output (pin 2 of IC1)is displayed a s
the inset picture. It is routed in vari-
ous directions: to a colour carrier trap.
RIO-CI5-L4:to one of the sync separa-
tors. IC6: and to a voltage divider. Rjz-
RI3. followed by a filter. LZ-CLZ.The
latter serves to extract the chromi-
nance (colour] information and the
colour burst from the composite video
signal.
The chrominance signal arrives at a
type TDA4510 PAL decoder IC.
Traditionally. this IC is accompanied
by a glass-based delay line to store the
chrominance information of the previ-
ous line. allowing a special circuit to
add the information contained in two
successive lines. and so correct any
colour errors. In the PAL system, the
delay line delays the (R-Y) and -(B-Y)
components modulated onto the 4.43-
MHz subcarrier. for adding to the non-
delayed signal. This addition is critical
in respect of phase position and level.
Here. the TDA4510 uses a n elec-
tronic equivalent of the 'old' glass
delay line. a baseband delay circuit
type TDA4661. The two colour differ-
ence signal outputs. pins 1 and 4 of
[C4. supply demodulated difference
Fig. 2. Circuit diagram of the PIP processor.

ELEKTOR E1,ECTRONICS OCTORER 1995

 PICTURE-IN-PICTURE PROCESSOR (PART 1) m
The PIP-plus chip set
Briefly recapitulating. the following
l SCART SOCKET PIN
FUNCTIONS
- -- - -1 0.4V - B u m m e signals are available a t the inputs of
clrm~
the PIP chip set:

- luminance (brightness) of the inset:

4.5 V - Horizomal - colour difference of the inset:
blanking - sandcastle signal of the inset:
2.5 V -Vertical - vertical sync pulses of the inset:
- blanking
0 V -N m a l
pimre
-
-
sandcastle signal of the parent:
vertical sync of the parent.
1
2
Output
Input
Audio, right channel
Audio, right channel
3 Output Audio, left channel
The analogue signals (luminance and 4 Ground Audio
chrominance) need to be digitized be- 5 Ground Blue
fore they can be processed by the PIP 6 Input Audio, left channel
950078-1-14
processor. The A-to-D conversion is 7 Input Blue
the main function of the SDA9187. 8 Function switch
which was developed specially for that 9 Ground Green
application. As indicated by the block 10
Fig. 3. The sandcastle pulse contains timing diagram of this IC (Fig. 4). the lumi- l1 Input Green
information about the colour burst. HN sync nance signal (YIN) and colour differ- 12 lnput V-Sync
pulses and the picture itself. ence signals (UIN and VIN) are 13 Ground Red
clamped and then applied to three 14 Ground Fast blanking
analogue-to-digital converters with a 15 Input Red
resolution of 6 bits. The clamping lev- 16 Input Fast Blanking (H-Sync)
els (i.e.. the drive margin of the sig- 17 Ground CVBS output
signals (hence 'baseband') to ICE,. nals) are determined by the voltage 18 Ground CVBS input
which copies them into an analogue difference between VREFH and VREFL 19 Output CVBS
shift register. After propagating (black level). The luminance informa- 20 Input CVBS
through the shift register. the 64-PS tion is available a s a six-bit wide word 21 Ground Pluglsocket screening
delayed signal and the non-delayed representing a value between 0 and
signal are added in the IC to give the
traditional -(R-Y) and -(B-Yl compo-
nents. The shift register is clocked by a
PLL circuit contained in the TDA4661.
The line frequency extracted from the -
'sandcastle' pulse is used a s the refer-
ence frequency for the PLL.
The video signal is also applied to
pin 5 of ICs. The TDA2579B has many
applications. of which only two are
used here. The main function of ICs is
to generate the so-called sandcastle
pulse (Fig. 3).whose position is deter-
mined by the centre of the horizontal
synchronization pulse contained in the
video input signal. The sandcastle
pulse is a three-level waveform which
supplies timing references on four
states:

0 V: normal picture reference level

2.5 V: vertical synchronization
4.5 V: horizontal blanking
10.4 V: burst-gate clamp

The sandcastle pulse supplied by ICs

synchronizes the PAL propagation time
demodulator (i.e.. PAL decoder plus
delay line). a s well a s the A-D con-
verter for the inset picture. Pin 3 of ICs
supplies narrow pulses which depend
on the vertical synchronization pulse.
These pulses are also fed to the PIP
processor.
The second TDA2579B (IClz) sup-
plies the same information Isandcastle
and vertical sync) derived from the
parent video signal, and also drives the
PIP core. Fig. 4. Internal clrcult of the SDA9187-Zx, which serves, among others, to dlgltize the ana-
logue luminance and chrominance signals (brightness and colour, respectively).
ELEKTOR ELECTRONICS OCTOBER 199:
 ISC
FIX& ~ o m l o avalve
l
( PLL
" connect&)
l
BLN
Y
A"'1que
Input
U
Analogue
Fig. 5. Timing dlagram for the various analogue and digital signals.
63. If necessary, this signal may be de-
layed to compensate propagation delay
differences in the decoder that pre-
cedes the ADC. The levels of pins M O .
YDI and M 2 here set a delay of
296 ns, which corresponds to four pe-
nods of the LL3 clock.
The SDA9187-2X h a s a PLL-based
horizontal synchronization section
consisting of a horizontal timer, a
phase comparator and a VCO. The
VC0 generates a clock of 13.5 MHz
which is phase locked to the video
input signal. This clock is fed to the
PIP IC (line-locked PIP system clock.
LL3) a s well a s to the ADC. the delay
line and the colour difference multi-
plexer. The horizonal scaler divides the
LL3 signal by 864. and applies it to the
phase comparator a s a 'horizontal' ref.
erence. The external horizontal sync
signal is derived from the sandcastle
pulse with the aid of a level detector.
and is blended in with the LL3 signal
a s regards the pulse width (345 LL3
periods). The frequency and phase
sensitive digital phase comparator pro-
duces up/down current pulses which
are turned into the VC0 control volt-
age by smoothing in a n RC network.
The horizonal timer also determines
the start and the width of the clamp
pulses. a s well a s the position of the
blanking pulses. BLN. which. in turn.
determine the length of the brightness
information. The BLN signal has to be
given the same delay a s the Y signal.
When the blanking signal is high. the
parent picture is synchronously re-
placed by the inset picture.
If desired. the colour difference sig-
nals may be inverted by using the
CNEG input. This results in a n in-
verted inset picture. This feature. al.
ELEKTOR ELECTRONICS OCTOBER 1995
though interesting. is not used here.
The digitized colour difference sig-
nals U and V leach having values be-
tween -32 and +31) arrive a t a
multiplexer which captures each
fourth U and V sample, and copies it in
half byte (nibble) format to outputs
UVO through W3.
Figure 5 shows the complex rela-
tions between the information repre-
senting chrominance. luminance and
horizontal/vertical synchronization a t
the inputs and outputs.
The components that make u p the
video signal of the inset source are ap-
plied to the PIP processor in digitized
form. The resolution of the digitized
input signals is six bits a t a sampling
rate of 13.5 MHz (luminance) or
3.375 MHz (chrominance]. The proces-
sor combines the (till then non-syn-
chronized) picture sources in such a
 PICTURE-IN-PICTURE PROCESSOR (PART 1) B
9 3 8
SELECT "ooa "5%
A

fmning
Occirnalian elanking
A A

I l
I 'm

-J
1

BLNl VS1 U
1 HSP VSP U P OX2 S D I SCL
(SAND) (0x1)
1 2 17 10 11 12 13 15 16
950078-1-13

Fig. 6. Archltecture of the heart of the PIP processor, the SDA9188-3X from Siemens.

way that a size-reduced inset is dis- instability too. though less serious. when the system is used with 100-Hz
played in a corner of the 'normal' pic- The inset piclure is synchronized to scan (LL1.5Pl. These frequencies need
ture. Apart from the picture size the parent picture with the aid of the to be generated by a n internal PLL. be-
reduction (based on compression horizontal and vertical sync signals cause a n external clock. LL3P. would
using horizontally and vertically oper- SAND and VSP. The clock speed of only be usable in a n all-digital envi-
ating filters). the SDA9188-3X also LL3P equals 13.5 MHz. or 27 M H Z ronment [of the parent source). The
stores the inset in a n integrated pic-
ture memory with a total size of
89x212x9=169.812 bits. It also takes
care of outputting this picture again a t
%th or %sth of the original size.
The colour of the frame around the
inset picture is programmable. The
same goes for the position of the inset
on the screen.
The output signals of the SDA9188-
3X are available a s analogue RGB or
chrominance/luminance signals IIY. 0 0 0
-(B-V. -(R-VI. The digital-to-analogue l/9 Picture 0 0 0 0
conversion is wideband for all compo- 1/16 Picture
nents, and has a resolution of six bits.
The SDA9188-3X is capable of pro-
cessing two picture formats:
50 Hz/625 lines and 6 0 HzJ525 lines.
The ability of the chip to "se 100-Hz
scanning (or 120 Hz) allows it to be
used in systems for standards conver-
sion. A frame frequency of 5 0 Hz [or
6 0 Hz) may also be used. with auto-
matic adjustment of the number of
lines.
Problems may occur if the parent and
inset pictures have different raster fre-
quencies. With an unfavourable and un-
stable phase position of the sync signal
and the parent clock. the inset picture
may 'jump' by one line or one pixel, re-
sulting in instability. Likewise. poor sync
signals in the inset channel may cause Fig. 7. Principle of 9-to-1 or 16-to-1 pixel compression technique.

EI.EKTOR ELECTRONICS OCTOBER 1995

 The vast number of options offered
Picture size N standard No. of pixels No. of lines by the registers in the PIP core call for
(lineslraster)
- - - - -- - -
Y U
- -
v a microcontroller. The 87C51 is oper-
ated in a n 'absolute minimum' envi-
119 625 212 53 8 53 88 ronment here. The power-up reset
pulse for the complete processor hard-
1/16 625 160 40 40 66
ware is furnished by &7-C58. A 10-
MHz quartz crystal. XQ. clocks the
Table 1. Organization of the inset picture memory. controller at 10 MHz. To prevent them
from vanishing forever when the power
is switched off, the register contents
are copied into a 256-bvte 12ccompat-
ible EEPROM. which is a non-volatile
Start Ac k Ack Ack memory component.
Register contents may be modified
S 0010 1110 A 0000 XXXX A XXXX XXXX A P by using the RC5 compatible infrared
remote control, or the three function
Chip address Register address Data word Stop keys on the PIP processor itself.
Obviously the three presskeys have
multiple functions to give access to all
Table 2. Format of the I2C commands sent to the SDA9188-3): PIP processor. available options. Apart from generat-
ing the necessary I ~ C commands for
the PIP IC core. the 87C51 also unrav-
els and translates the RC5 codes re-
ceived from the infrared remote
frequency of the internal clock signal a current through a pull-down resis- control. The infrared receiver is based
is calculated as fT=864xfsAND.tor. b,. b2 and b3 (OUTl=R. on the SFH506-36 detector from
Horizontal and vertical sync signals OUT2=G. OUT3=B). The output cur- Siemens. and is accommodated on a
BLNl and VSI, a s well a s LL31 also rent may be changed by modifying the separate printed circuit board together
serve to keep the inset picture syn- resistors, or by programming the with the three presskeys that form the
chronized to t h e parent picture. The processor. 'local' keyboard. This sub-board is
interface between the inset and the The output signals of the PIP connected to the main board vi a short
parent picture is formed by a n inte- processor then arrive at the length of flatcable. LED D , , lights
grated picture memory. in which data TEA51 14A, before they leave the cir- when a valid (RC5 compatible) infra-
is clocked in a t the rate of the inset. cuit via SCART connector KZ. The red signal is received. The other ten
and clocked out at the rate of the par- TEA51 14A only serves to amplify the LEDs (D, through Dlo) indicate the
ent. Output signal SELECT (output RGB signals about 2 times, and to status of the microcontroller in pro-
signals of SDA9 188-3x valid) controls clamp them a t about 2 V,,,. The gramming mode. (950078-1)
a n electronic switch in the TV set BLANKING signal switches the RGB
which frames the size-reduced inset outputs off when there is no inset pic-
into the parent picture. ture in the relevant picture lines. The The programming. construction and set-
Of particular interest in the block BLANKING signal is connected ting up of the PIP processor will be dis-
diagram [Fig. 6) is the data reduction through to the corresponding connec- cussed in next month's second a n d
of the inset picture. The data rate a t tions on KZvia pins 9/10. final instalment.
the inputs YS4 through YS4 and UVSO The power supply of the PIP proces-
through UVS3 is 13.5 MHz. To reduce sor is conventional. and based on fixed
the amount of data to be stored. nine voltage + l 2 V and +5 V regulators. Ra3
(PIP size 'Ath) or sixteen (PIP size %sth) and Rgq limit the dissipation of the
pixels are averaged horizontally and 7812 and 7805 to reasonable values.
vertically. and then processed into a The 'power' LED on the front panel
single pixel in the inset (Fig. 7 ) . The provides a n on/off indication.
number of ~ i x e l sand lines that make
u p the insef picture depends on the TV 1 2 ~ and the
standard of the inset source. and the
Dicture size. The size of the oicture
microcon+ro~ler
memory is. of course. based on the The PIP IC core obtains all configura-
maximum number of pixels and lines tion information via its 12C interface.
a s shown in Table 1. The PIP processor itself Is found at ad-
Ai ihe parent side of the IC. behind dress 00101 110 = 2EH.When power is
the picture memory. the data rate of applied, a n automatic reset is issued.
the chrominance signal is quadrupled and the SDA and SCL lines are freed.
to match that of the luminance infor- All bits in the ten registers, except bit
mation. This is done to eliminate PL27 (bit d 3 in register 01 are then set
cross-colour effects after the D-A con- to 0. while PL27 is set to 1. The
version, a s well a s to prepare for the SDA9188-3x is switched to 'slave'
digital RGB conversion. The rate-up mode. and operates only when the
conversion is achieved by linear (U-V) inset clock. LL31, is present.
interpolation. A digital RGB matrix 1% commands and data sent to the
converts the Y. U and V levels read SDA9188-3X have the general format
from the RAM into RGB data. which shown in Table 2. All registers incre-
are then applied to three 6-bit D-A ment automatically to the next one
converters. Each of these DACs sends after a byte has been written.
E1,EKTOR ELECTRONICS OCTOBER 199.5