Lecture 0 - Course Presentation

Lecture 0: Logic
synthesis & VHDL.

Course presentation
Francisco Rodríguez-Ballester (prodrig@disca.upv.es)
Computing Engineering Dept.
Universitat Politècnica de València, Spain
Outline
(c) 2006-2018 Francisco Rodríguez-Ballester (prodrig@disca.upv.es)
 Syllabus
 Course roadmap
 Lectures
 Orthogonal concepts
 Course materials
 References
 How are we going to learn VHDL?
Logic synthesis & VHDL course: Lecture 0 - Course presentation, spring 2018
Syllabus
 Instructor: Francisco Rodríguez-Ballester

(“Paco”)
 Office: D1-265
 E-mail address: prodrig@disca.upv.es
 Grading plan:
 40% lab assignments + 60% final exam
Course roadmap
 Lectures
 Introduction
 Programmable logic devices (FPGAs)
 VHDL language and its design flows
 VHDL language main elements

 Orthogonal concepts
 Labs
 Simulation, Synthesis, or Simulation & Synthesis
Course roadmap – Lectures
 VHDL language main elements

 Data types
 Data objects: constants, variables, and signals
 Attributes (meta-information)
 Libraries and packages
 Design units
 Design types: structural, behavioural, and dataflow
Course roadmap – Lectures (2)
 Design unit
A “box” representing a digital circuit with inputs
and outputs
 A design unit is composed of
 Interface, VHDL entity
 Just the name and set of inputs, outputs, and
parameters of the box
 Implementation, VHDL architecture
 The internal circuit details
Course roadmap – Lectures (3)
 Orthogonal concepts
 FiniteState Machines (FSMs)
 Parametric, reusable designs
 Functional verification
 Testbenches in VHDL
 Stimulate a VHDL design unit in order to test its
functionality
 Creating and testing designs on actual hardware
Course materials
 Everything available online

 Course moodle site at http://ent.esigelec.fr
 Login & search for “VHDL and logic synthesis” course
 Enroll now!
 Moodle site used to upload your assignments also

 Lecture handouts
 VHDL syntax reference (“cheat sheet”)
 Get used to it, you’ll use it during the exam!
References
 Books
 ‘The designer’s guide to VHDL’ by P. J. Ashenden
 Initial version available online in PDF format:
 http://tams-www.informatik.uni-hamburg.de/research/vlsi/vhdl/
click “Documentation”, then “VHDL Cookbook”
 Any modern book on logic design has at least a
chapter devoted VHDL (if not the whole book)
 ‘VHDL’ by Douglas L. Perry
 ‘HDL chip design’ by Douglas J. Smith
References (2)
 Internet resources
 Wikipedia
 http://en.wikipedia.org/wiki/VHDL
 VHDL Primer (Univ Pennsylvania)
 http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.h
tml
 Xilinx (http://www.xilinx.com)
 Manufacturer of the FPGA device and the development
software used in the lab
How are we going to learn VHDL?
 We are not going to examine every detail of

each language element, because…
 The number of language constructs is huge
 Don’t have enough time!
 Many accessible references on Internet
 Very interesting circuits can be designed with a
small subset of the language
How are we going to learn VHDL? (2)
 Use the cheat sheet from day one!

 Don’t get frustrated if you get tons of errors
writing your first designs
 The compiler is your friend
 Your instructor will be happy to help you
 Mastering the language takes time
 Use your time and brain to understand good
design principles and apply best practices
 Many VHDL solutions exists for any given

problem
 Using one or another is usually just a question of
personal taste
 You may find different code snippets on the
Internet for the same designs I’m going to present
 All of them are probably ok
 How can you tell they are ok? Test them!
 So …
 Focus on acquiring a good ground
 Design methodology
 Concepts
 Think before you type, then think again! Twice!

 Examples/templates are used to introduce
new concepts/language elements
 And then, syntax is briefly/informally described

Lecture 0 - Course Presentation

Încărcat de

Informații document

Drepturi de autor

Formate disponibile

Partajați acest document

Partajați sau inserați document

Opțiuni de partajare

Vi se pare util acest document?

Este necorespunzător acest conținut?

Drepturi de autor:

Formate disponibile

Lecture 0 - Course Presentation

Încărcat de

Drepturi de autor:

Formate disponibile

Lecture 0: Logic

synthesis & VHDL.

 Instructor: Francisco Rodríguez-Ballester

 VHDL language main elements

 VHDL language main elements

 Everything available online

 Moodle site used to upload your assignments also

 We are not going to examine every detail of

 Use the cheat sheet from day one!

 Many VHDL solutions exists for any given

 Think before you type, then think again! Twice!

S-ar putea să vă placă și