Documente Academic
Documente Profesional
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EC-6612
CONTENT
1 Design of simple counter, FSM, Adder (8-bit), Multiplier (4-bit) and Simulate.
2 To Synthesis, P&R and post P&R simulation of the components simulation of counter
and find Critical paths and static timing analysis results to be identified
3 Implementation of the Hardware device by using Chip Scope Pro
IC Design Experiments – CADENCE tool
4 Design of simple Differential amplifier, calculate gain and CMRR
5 Layout generation, parasitic Extraction and post layout Simulation
6 Synthesis and Simulate the counter and find Identification of critical paths, power
consumption.
7 Floor plan, Power plan, routing, placement, Static timing analysis(STA) and Critical path
for counter
VLSI DESIGN LAB
EX: NO: 1 Design of simple counter, FSM, Adder (8-bit), Multiplier (4-bit)
AIM:
Tools Required:
Procedure:
coding: ( counter)
module cnt(
input clk,
input rst,
output reg [3:0] count
);
always @ (posedge clk)
begin
if (rst)
count <= "0000";
else
count <=count+1;
end
endmodule
Simulation output:
reg [1:0]state_reg,state_next;
if (rst)
state_reg<=s0;
else
state_reg <= state_next;
always @ *
case (state_reg)
s0: if(a)
if(b)
state_next =s2;
else
state_next =s1;
else
state_next =s0;
s1:if (a)
state_next =s0;
else
state_next = s1;
s2:state_next = s0;
default:state_next =s0;
endcase
endmodule
coding:(adder)
input [7:0]a;
input [7:0]b;
input cin;
output [7:0]sum;
output carry;
reg [7:0]sum;
reg carry;
reg [7:0]c;
always @ (a or b or cin)
begin
end
end module
Simulation output:
coding: (multiplier-4)
module HA(sout,cout,a,b);
output sout,cout;
input a,b;
assign sout=a^b;
assign cout=(a&b);
endmodule
module FA(sout,cout,a,b,cin);
output sout,cout;
input a,b,cin;
assign sout=(a^b^cin);
assign cout=((a&b)|(a&cin)|(b&cin));
endmodule
module multiply4bits(product,inp1,inp2);
output [7:0]product;
input [3:0]inp1;
input [3:0]inp2;
assign product[0]=(inp1[0]&inp2[0]);
wire x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17;
HA HA1(product[1],x1,(inp1[1]&inp2[0]),(inp1[0]&inp2[1]));
FA FA1(x2,x3,inp1[1]&inp2[1],(inp1[0]&inp2[2]),x1);
FA FA2(x4,x5,(inp1[1]&inp2[2]),(inp1[0]&inp2[3]),x3);
HA HA2(x6,x7,(inp1[1]&inp2[3]),x5);
HA HA3(product[2],x15,x2,(inp1[2]&inp2[0]));
FA FA5(x14,x16,x4,(inp1[2]&inp2[1]),x15);
FA FA4(x13,x17,x6,(inp1[2]&inp2[2]),x16);
Simulation output:
AIM:
To Synthesis, P&R and post P&R simulation of the components simulation of counter and find
Critical paths and static timing analysis results to be identified.
Procedure:
design:
module cnt(
input clk,
input rst,
output reg [3:0] count
);
always @ (posedge clk)
begin
if (rst)
count <= "0000";
else
count <=count+1;
end
endmodule
Aim:
Procedure:
Xilinx provides Chip Scope Pro software to view hardware simulation (to view the current status of
the hardware signals in a FPGA board in PC). We can run the Chip Scope Pro for current project
and also configure the FPGA through Chip Scope Pro. An FPGA may get inputs from the outside
environment like switches or binary signals from external hardware and the Project output is
changed depending on the input. When we change the input in hardware we get the output changes
in hardware which is also updated in Chip Scope Pro simulation window. Thus we can view the real
time changes of hardware signals in software. Refer Xilinx website to know more details about
Chip Scope Pro.
Working procedure of Chip Scope Pro is given in the following section. Counter function is taken
as an example to view the hardware simulation. Create a new project file and give the Verilog
Coding, UCF file. Save the files and select New Source from Project menu. New Source Wizard
window will open, here select Chip Scope Definition and Connection File. Give the file name and
file location to store the file then click ‘Next’ and ‘Finish.
Now cnt.cdc file is added in the source window. Double click cnt.cdc file and Chip Scope Pro
Clock input signal does not come under the Trigger ports. Other input and output signals are
considered as trigger signals and we must set the Data registration parameters such as memory
depth and data width of the trigger data and clock edge are selected here.
Net Connections section shows the Clock port and Trigger ports. Double click the ports one by one
to make net connections. First select Clock port
Shows the connected net for the ports. Now click ‘Return to Project Navigator’ to run Chip Scope
pro application and click ‘Yes’ to save the project.
Run Analyze Design Using Chip Scope Pro in Process window. Then the Chip Scope Pro will open
shown
Power-ON the Spartan-6 Project Board to make the connection between PC and Board via JTAG
cable. Select the type of cable we are using for the experiment. Xilinx JTAG USB cable is used.
Select it from JTAG Chain menu. Parameters of the JTAG cable are shown in the following
window. Check it and select OK. Two devices (FPGA & PROM) in the Board are detected and click
OK to finish the initial steps
Device detection
Right click the FPGA device and select ‘Configure’ to select the operating files for the current
project
Select .bit file and .cdc file from the directory and click OK.
likewise add the bit file also, After selecting the files open the trigger window by right click the
‘Trigger setup’option in Project window. Then open‘Waveform’window to view the hardware
waveforms for this experiment. The Trigger window and waveform window. In this experiment we
are using one trigger input (Reset).
Trigger Setup
Waveform setup
Set the reset signal as low in Spartan-6 Project Board and we get 4-bit counter output in LEDs.
Hardware values are displayed in the Chip Scope Pro Waveform Window and it is updated at every
changes. Set the reset signal as high in Spartan-6 Project Board. Counter operation will be stopped
in hardware and also in waveform window. Chip Scope Pro is the only tool to view and analyze the
hardware signals of FPGA by viewing the hardware signals in software.
AIM:
To design the simple Differential Amplifier by using cmos and calculate the gain and CMRR.
Procedure:
Transistor M1 M2 M3 M4 M5 M6
Type Pmos Pmos Nmos Nmos Nmos Nmos
Width 15u 15u 3u 3u 4.5u 4.5u
Length 1u 1u 1u 1u 1u 1u
Launch → ADE L
Next go to ADEL Window Results → Direct plot → AC dB20 and it direct to schematic window,
click the output nets from the schematic and press escape. The following waveform appears as
shown below
Gain waveform
tools → calculator
Common gain:
CMRR
Aim:
Draw the layout 0f Differential Amplifier, extract parasitic component and post layout
Simulation.
Procedure:
Step-1:
launch → layout XL
DRC
LVS
create a new file in the test bench name, type → config and ok.
view → Schematic
click → OK
do the simulation process as usually and check the power and propagation time delay
and then compare to normal simulation output.
AIM:
To Synthesis and Simulate the counter and find Identification of critical paths, power
consumption.
Procedure:
In the terminal
Welcome to cadence Tool Suit
#cd NCO/rclabs/rtl
# gedit countervi.v
module counter(
input clk,
input rst,
output reg [3:0] count
);
always @ (posedge clk)
begin
if (rst)
count <= "0000";
else
count <=count+1;
end
endmodule
compile
Simulation:
Synthesize:
#rc -gui
The failed component should be zero then only we proceed the synthesize process
completely
CRITICAL PATH:
now the netlist will written in the terminal, also write the constraints file in new
name
EX.NO.7 Floor plan, Power plan, routing, placement, clock routing for counter
AIM:
Design the Floor Plan, Power plan, Routing, Placement, Static timing analysis (STA) and
Critical path for counter
Procedure:
# encounter
fill all the data that needed for the design click → ok
Powerplan:
Placement:
click → ok
The STA is static the analysis of the design is carried out statically and does not
depend upon the data values being applied at the input pins. This is in contrast to
simulation based timing analysis where a stimulus is applied on input signals,
resulting behavior is observed and verified, then time is advanced with new input
stimulus applied, and the new behavior is observed and verified and so on. a design
along with a set of clock definitions and the definition of the external environment
of the design, the purpose of static timing analysis is to validate if the design
can operate at the rated speed. That is, the design can operate safely at the specified
frequency of the clocks without any timing violations. Some examples of timing checks
are setup and hold checks. A setup check ensures that the data can arrive at a flip-flop
within the given clock period. A hold check ensures that the data is held for at least
a minimum time so that there is no unexpected pass-through of data through a flip-flop:
that is, it ensures that a flip-flop captures the intended data correctly. These
checks ensure that the proper data is ready and available for capture and latched
in for the new state.
CTS is the process of insertion of buffers or inverters along the clock paths of ASIC
design in order to achieve zero/minimum skew or balanced skew. The goal of CTS is
to minimize skew and insertion delay. Apart from these, useful skew is also added
in the design by means of buffers and inverters. Clock is propagated after placement
because the exact physical location of cells and modules are needed for the clock’s
propagation which in turn impacts in dealing with accurate delay and operating
frequency and clock is propagated before routing because when compared to logical
routes, clock routs are given more priority. This is because, clock is the only signal
switches frequently which in acts as source for dynamic power dissipation.
Though wide range of clock routing algorithm are available, EDA tool chooses the
optimized algorithm automatically and it only shows the critical paths after
propagating the tree. If a design results in negative slack, increasing the clock
timing is an easy way but changing the clock period changes the operating frequency.
Solving the negative slack without changing the clock period is possible by up-sizing
or down-sizing the cell in critical paths.
In the Generate clock spec select all clkbuf and clkinv and click → add and ok
now the clk buffers that are place inside the standard cell, now the next step is
to route the clkbuf and clkinv .
Post-CTS:
To find the time delay inside the nets type the command in encounter terminal report_timing
encounter 1> report_timing
CRITICAL PATH:
Critical path is the path having the more time delay inside the circuit is called
critical path.
TYPE COMMAND IN ENCOUNTER TERMINAL.