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PIC16C770/771
• Operating speed: DC - 20 MHz clock input RA5/MCLR/VPP 4 17 RA6/OSC2/CLKOUT
DC - 200 ns instruction cycle VSS 5 16 VDD
Memory AVSS 6 15 AVDD
A/D A/D RA2/AN2/VREF-/VRL 7 14 RB7/T1OSI/P1D
Device Program Data Pins Resolution Channels
RA3/AN3/VREF+/VRH 8 13 RB6/T1OSO/T1CKI/P1C
x14 x8
RB0/AN4/INT 9 12 RB5/SDO/P1B
PIC16C717 2K 256 18, 20 10 bits 6 10 11 RB4/SDI/SDA
RB1/AN5/SS
PIC16C770 2K 256 20 12 bits 6
PIC16C771 4K 256 20 12 bits 6 Peripheral Features:
• Interrupt capability (up to 10 internal/external • Timer0: 8-bit timer/counter with 8-bit prescaler
interrupt sources)
• Timer1: 16-bit timer/counter with prescaler,
• Eight level deep hardware stack can be incremented during sleep via external
• Direct, indirect and relative addressing modes crystal/clock
• Power-on Reset (POR) • Timer2: 8-bit timer/counter with 8-bit period
• Power-up Timer (PWRT) and register, prescaler and postscaler
Oscillator Start-up Timer (OST) • Enhanced Capture, Compare, PWM (ECCP)
• Watchdog Timer (WDT) with its own on-chip RC module
oscillator for reliable operation - Capture is 16 bit, max. resolution is 12.5 ns
• Selectable oscillator options: - Compare is 16 bit, max. resolution is 200 ns
- INTRC - Internal RC, dual speed (4MHz and - PWM max. resolution is 10 bit
37KHz) dynamically switchable for power sav- - Enhanced PWM:
ings - Single, Half-Bridge and Full-Bridge output
- ER - External resistor, dual speed (user modes
selectable frequency and 37KHz) dynami- - Digitally programmable deadband delay
cally switchable for power savings • Analog-to-Digital converter:
- EC - External clock - PIC16C770/771 12-bit resolution
- HS - High speed crystal/resonator - PIC16C717 10-bit resolution
- XT - Crystal/resonator
• On-chip absolute bandgap voltage reference
- LP - Low power crystal
generator
• Low-power, high-speed CMOS EPROM
• Programmable Brown-out Reset (PBOR)
technology
circuitry
• In-Circuit Serial Programming™ (ISCP)
• Programmable Low-Voltage Detection (PLVD)
• Wide operating voltage range: 2.5V to 5.5V circuitry
• 15 I/O pins with individual control for: • Master Synchronous Serial Port (MSSP) with two
- Direction (15 pins) modes of operation:
- Digital/Analog input (6 pins) - 3-wire SPI™ (supports all 4 SPI modes)
- PORTB interrupt on change (8 pins) - I2C™ compatible including master mode
- PORTB weak pull-up (8 pins) support
- High voltage open drain (1 pin)
• Program Memory Read (PMR) capability for look-
• Commercial and Industrial temperature ranges up table, character string storage and checksum
• Low-power consumption: calculation purposes
- < 2 mA @ 5V, 4 MHz
- 22.5 µA typical @ 3V, 32 kHz
- < 1 µA typical standby current
PIC16C717
RA4/T0CKI 3 RA7/OSC1/CLKIN
PIC16C717
RA5/MCLR/VPP 4 17 RA6/OSC2/CLKOUT
RA5/MCLR/VPP 4 15 RA6/OSC2/CLKOUT
VSS(1) 5 16 VDD(2)
VSS 5 14 VDD
VSS(1) 6 15 VDD(2)
RA2/AN2/VREF-/VRL 6 13 RB7/T1OSI/P1D
RA2/AN2/VREF-/VRL 7 14 RB7/T1OSI/P1D
RA3/AN3/VREF+/VRH 7 12 RB6/T1OSO/T1CKI/P1C
11 RA3/AN3/VREF+/VRH 8 13 RB6/T1OSO/T1CKI/P1C
RB0/AN4/INT 8 RB5/SDO/P1B
RB0/AN4/INT 9 12 RB5/SDO/P1B
RB1/AN5/SS 9 10 RB4/SDI/SDA
RB1/AN5/SS 10 11 RB4/SDI/SDA
Key Features
PICmicroTM Mid-Range Reference Manual PIC16C717 PIC16C770 PIC16C771
(DS33023)
Addr MUX
Instruction reg PORTB
Direct Addr 7 Indirect RB0/AN4/INT
8 Addr RB1/AN5/SS
FSR reg RB2/SCK/SCL
RB3/CCP1/P1A
RB4/SDI/SDA
STATUS reg
Internal 8 RB5/SDO/P1B
4MHz, 37KHz RB6/T1OSO/T1CKI/P1C
and ER mode RB7/T1OSI/P1O
3 MUX
Instruction
Decode &
Control Power-up
Timer
ALU
Timing Oscillator
Generation Start-up Timer 8
OSC1/CLKIN
OSC2/CLKOUT Power-on
VDD, VSS Reset W reg
Watchdog
Timer
Brown-out
Reset
Master
Enhanced CCP
Synchronous
(ECCP1)
Serial Port (MSSP)
Addr MUX
Instruction reg PORTB
7 Indirect
Direct Addr RB0/AN4/INT
8 Addr
RB1/AN5/SS
FSR reg RB2/SCK/SCL
RB3/CCP1/P1A
STATUS reg RB4/SDI/SDA
Internal 8 RB5/SDO/P1B
4MHz, 37KHz RB6/T1OSO/T1CKI/P1C
and ER mode RB7/T1OSI/P1O
3 MUX
Instruction
Decode &
Control Power-up
Timer
ALU
Timing Oscillator
Generation Start-up Timer 8
OSC1/CLKIN
OSC2/CLKOUT Power-on
VDD, VSS Reset W reg
Watchdog
Timer
Brown-out
Reset
Master
Enhanced CCP
Synchronous
(ECCP1)
Serial Port (MSSP)
Stack Level 1
Stack Level 2 3FFFh
Bank 0
00h(3) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
04h(3) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
05h PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx 0000 uuuu 0000
06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xx00 uuuu uu00
07h — Unimplemented — —
08h — Unimplemented — —
09h — Unimplemented — —
(1,3)
0Ah PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
0Bh(3) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 — ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
17h CCP1CON PWM1M1 PWM1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000
18h — Unimplemented — —
19h — Unimplemented — —
1Ah — Unimplemented — —
1Bh — Unimplemented — —
1Ch — Unimplemented — —
1Dh — Unimplemented — —
1Eh ADRESH A/D High Byte Result Register xxxx xxxx uuuu uuuu
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE CHS3 ADON 0000 0000 0000 0000
Bank 1
80h(3) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
82h(3) PCL Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000
(3)
83h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu
84h(3) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
85h TRISA PORTA Data Direction Register 1111 1111 1111 1111
86h TRISB PORTB Data Direction Register 1111 1111 1111 1111
87h — Unimplemented — —
88h — Unimplemented — —
89h — Unimplemented — —
8Ah(1,3) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
8Bh(3) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
8Ch PIE1 — ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000
8Fh — Unimplemented — —
90h — Unimplemented — —
91h SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000
94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
95h WPUB PORTB Weak Pull-up Control 1111 1111 1111 1111
96h IOCB PORTB Interrupt on Change Control 1111 0000 1111 0000
98h — Unimplemented — —
99h — Unimplemented — —
9Ah — Unimplemented — —
9Bh REFCON VRHEN VRLEN VRHOEN VRLOEN — — — — 0000 ---- 0000 ----
9Ch LVDCON — — BGST LVDEN LVV3 LVV2 LVV1 LVV0 --00 0101 --00 0101
9Eh ADRESL A/D Low Byte Result Register xxxx xxxx uuuu uuuu
9Fh ADCON1 ADFM VCFG2 VCFG1 VCFG0 0000 0000 0000 0000
Bank 2
100h(3) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
105h — Unimplemented — —
106h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xx00 uuuu uu00
107h — Unimplemented — —
108h — Unimplemented — —
109h — Unimplemented — —
(1,3) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
10Ah
10Bh(3) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
10Ch PMDATL Program memory read data low xxxx xxxx uuuu uuuu
10Dh PMADRL Program memory read address low xxxx xxxx uuuu uuuu
10Eh PMDATH — — Program memory read data high --xx xxxx --uu uuuu
10Fh PMADRH — — — — Program memory read address high ---- xxxx ---- uuuu
110h-
— Unimplemented — —
11Fh
Bank 3
180h(3) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
182h(3) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
186h TRISB PORTB Data Direction Register 1111 1111 1111 1111
187h — Unimplemented — —
188h — Unimplemented — —
189h — Unimplemented — —
18Ah (1,3) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
18Bh(3) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
18Dh-
— Unimplemented — —
18Fh
Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the sec-
ond operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of
the source register.
Note 1: Individual weak pull-up on RB pins can be enabled/disabled from the weak pull-up PORTB Register
(WPUB).
REGISTER 2-3: INTERRUPT CONTROL REGISTER (INTCON: 0Bh, 8Bh, 10Bh, 18Bh)
Note 1: Individual RB pin interrupt on change can be enabled/disabled from the Interrupt on Change PORTB register (IOCB).
Data
Memory(1)
Note: Setting a pin to an analog input disables digital inputs and any pull-up that may be present. The corre-
sponding TRIS bit should be set to input mode when using pins as analog inputs.
3.2 PORTA and the TRISA Register these pins as analog input/output, the ANSEL register
must have the proper value to individually select the
PORTA is a 8-bit wide bi-directional port. The corre- analog mode of the corresponding pins.
sponding data direction register is TRISA. Setting a
TRISA bit (=1) will make the corresponding PORTA pin Note: Upon reset, the ANSEL register configures
an input, i.e., put the corresponding output driver in a the RA<3:0> pins as analog inputs. All
hi-impedance mode. Clearing a TRISA bit (=0) will RA<3:0> pins will read as ’0’.
make the corresponding PORTA pin an output, i.e., put Pin RA4 is multiplexed with the Timer0 module clock
the contents of the output latch on the selected pin. input to become the RA4/T0CKI pin. The RA4/T0CKI
Reading the PORTA register reads the status of the pin is a Schmitt Trigger input and an open drain output.
pins, whereas writing to it will write to the port latch. All Pin RA5 is multiplexed with the device reset (MCLR)
write operations are read-modify-write operations. and programming input (VPP) functions. The RA5/
Therefore, a write to a port implies that the port pins are MCLR/VPP input only pin has a Schmitt Trigger input
read, this value is modified, and then written to the port buffer. All other RA port pins have Schmitt Trigger input
data latch. buffers and full CMOS output buffers.
Pins RA<3:0> are multiplexed with analog functions, Pins RA6 and RA7 are multiplexed with the oscillator
such as analog inputs to the A/D converter, analog input and output functions.
VREF inputs, and the on-board bandgap reference out-
The TRISA register controls the direction of the RA
puts. When the analog peripherals are using any of
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
TRIS Mode
D Q N
WR
TRIS VSS VSS
CK Q
RD
TRIS
Analog Select
Schmitt
D Q
Trigger
WR
ANSEL
CK Q
Q D
EN
RD
PORT
WR
TRIS VSS VSS
CK Q
RD
TRIS
Analog Select
D Q Schmitt
Trigger
WR
ANSEL
CK Q
Q D
EN
RD
PORT
WR
Port
CK Q
TRIS Latch
D Q N
WR
TRIS
CK Q VSS
VSS
RD Schmitt Trigger
TRIS
Input Buffer
Q D
EN
RD
PORT
To MCLR Circuit
MCLR Filter
Program Mode
HV Detect
Data VSS
Bus
RD
TRIS VSS
Schmitt
Trigger
Q D
EN
RD PORT
0
VDD
Data D Q VDD
Bus
WR Q P
CK
PORTA INTRC or ER VSS
Data Latch
D Q
N
WR CK Q
TRISA INTRC or ER without CLKOUT
INTRC or ER with CLKOUT
TRIS Latch
VSS
Schmitt Trigger
Input Buffer
RD TRISA
Q D
EN
RD PORTA
To OSC2 Oscillator
Circuit VDD
To Chip Clock Drivers
Schmitt Trigger
Data D Q VDD Input Buffer
Bus
EC Mode
WR Q P
CK
PORTA
Data Latch
D Q
WR N
TRISA CK Q
TRIS Latch
INTRC VSS
INTRC
RD TRISA
Schmitt Trigger
Input Buffer
Q D
EN
RD PORTA
Input Output
Name Function Description
Type Type
RA0 ST CMOS Bi-directional I/O
RA0/AN0
AN0 AN A/D input
RA1 ST CMOS Bi-directional I/O
RA1/AN1/LVDIN AN1 AN A/D input
LVDIN AN LVD input reference
RA2 ST CMOS Bi-directional I/O
AN2 AN A/D input
RA2/AN2/VREF-/VRL
VREF- AN Negative analog reference input
VRL AN Internal voltage reference low output
RA3 ST CMOS Bi-directional I/O
AN3 AN A/D input
RA3/AN3/VREF+/VRH
VREF+ AN Positive analog reference input
VRH AN Internal voltage reference high output
RA4 ST OD Bi-directional I/O
RA4/T0CKI
T0CKI ST TMR0 clock input
RA5 ST Input port
RA5/MCLR/VPP MCLR ST Master clear
VPP Power Programming voltage
RA6 ST CMOS Bi-directional I/O
RA6/OSC2/CLKOUT OSC2 XTAL Crystal/resonator
CLKOUT CMOS FOSC/4 output
RA7 ST CMOS Bi-directional I/O
RA7/OSC1/CLKIN OSC1 XTAL Crystal/resonator
CLKIN ST External clock input/ER resistor connection
05h PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx 0000 uuuu 0000
85h TRISA PORTA Data Direction Register 1111 1111 1111 1111
9Dh ANSEL ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ’0’. Shaded cells are not used by PORTA.
3.3 PORTB and the TRISB Register enables the weak pull-up resistors. The weak pull-up is
automatically turned off when the port pin is configured
PORTB is an 8-bit wide bi-directional port. The corre- as an output. The pull-ups are disabled on a Power-on
sponding data direction register is TRISB. Setting a Reset.
TRISB bit (=1) will make the corresponding PORTB pin
Each of the PORTB pins, if configured as input, also
an input, i.e., put the corresponding output driver in a
has an interrupt on change feature, which can be indi-
hi-impedance mode. Clearing a TRISB bit (=0) will
vidually selected from the IOCB register. The RBIE bit
make the corresponding PORTB pin an output, i.e., put
in the INTCON register functions as a global enable bit
the contents of the output latch on the selected pin.
to turn on/off the interrupt on change feature. The
selected inputs are compared to the old value latched
EXAMPLE 3-2: INITIALIZING PORTB on the last read of PORTB. The "mismatch" outputs are
BCF STATUS, RP0 ;
OR’ed together to generate the RB Port Change Inter-
CLRF PORTB ; Initialize PORTB by
; clearing output
rupt with flag bit RBIF (INTCON<0>).
; data latches This interrupt can wake the device from SLEEP. The
BSF STATUS, RP0 ; Select Bank 1 user, in the interrupt service routine, can clear the inter-
MOVLW 0xCF ; Value used to rupt in the following manner:
; initialize data
; direction a) Any read or write of PORTB. This will end the
MOVWF TRISB ; Set RB<3:0> as inputs mismatch condition.
; RB<5:4> as outputs b) Clear flag bit RBIF.
; RB<7:6> as inputs
MOVLW 03 ; Set RB<1:0> as analog A mismatch condition will continue to set flag bit RBIF.
inputs Reading PORTB will end the mismatch condition and
MOVWF ANSEL ; allow flag bit RBIF to be cleared.
BCF STATUS, RP0 ; Return to Bank 0 The interrupt on change feature is recommended for
Each of the PORTB pins has an internal pull-up, which wake-up on key depression operation and operations
can be individually enabled from the WPUB register. A where PORTB is only used for the interrupt on change
single global enable bit can turn on/off the enabled pull- feature. Polling of PORTB is not recommended while
ups. Clearing the RBPU bit, (OPTION_REG<7>), using the interrupt on change feature.
Note 1: For the WPUB register setting to take effect, the RBPU bit in the OPTION_REG Register must be cleared.
2: The weak pull up device is automatically disabled if the pin is in output mode (TRIS = 0).
Note 1: The interrupt enable bits GIE and RBIE in the INTCON Register must be set for individual interrupts to be
recognized.
WPUB Reg
Data Bus
D Q
WR
WPUB
CK Q VDD
RBPU
P weak
pull-up
PORTB Reg VDD
D Q
VDD
WR
PORT
CK Q
P
TRIS Reg N
D Q
WR
TRIS VSS
CK Q
RD
TRIS VSS
Analog Select
D Q
WR
ANSEL
CK Q
TTL
IOCB Reg
D Q Schmitt
WR Set Trigger
IOCB RBIF
CK Q Q D
...
From Q1
EN
RB<7:0> pins
Q D
Q D
Q3
EN
EN EN
RD
PORT
To A/D Converter
WPUB Reg
Data Bus
D Q
WR
WPUB
CK Q VDD
Spec. Func En. RBPU VDD
SDA, SDO, SCK, CCPL, P1A, P1B P weak
pull-up
PORTB Reg 1 VDD
D Q 0
P
WR
PORT
CK Q
N
TRIS Reg
D Q VSS
WR
TRIS VSS
CK Q
RD
TRIS
TTL
IOCB Reg
Schmitt
D Q Trigger
WR Set
IOCB RBIF
CK Q Q D
...
From Q1
EN
RB<7:0> pins
Q D
Q D
Q3
EN
EN EN
RD
PORT
D Q P
VDD
WR PORTB
CK Q
Data Latch
D Q
WR TRISB N
CK Q
RD TRISB TTL
Input
T1OSCEN Buffer
RD PORTB
IOCB Reg
D Q
WR
IOCB
CK Q
TMR1 Clock
Serial programming clock
Schmitt
From RB7 Trigger
TMR1 Oscillator
Q D
Q1
EN
Set RBIF
...
Q D
From RD Port
RB<7:0> pins EN Q3
Note: The TMR1 oscillator enable (T1OSCEN = 1) overrides the RB6 I/O port and P1C functions.
D Q P
WR PORTB CK Q
Data Latch
D Q
WR TRISB CK Q N
RD TRISB
T10SCEN
TTL
RD PORTB Input
Buffer
IOCB Reg
D Q
WR
IOCB
CK Q
Schmitt Trigger Q1
EN
Set RBIF
...
From Q D
RB<7:0> pins
RD Port
EN Q3
Note: The TMR1 oscillator enable (T1OSCEN = 1) overrides the RB7 I/O port and P1D functions.
Input Output
Name Function Description
Type Type
RB0 TTL CMOS Bi-directional I/O(1)
RB0/AN4/INT AN4 AN A/D input
INT ST Interrupt input
RB1 TTL CMOS Bi-directional I/O(1)
RB1/AN5/SS AN5 AN A/D input
SS ST SSP slave select input
RB2 TTL CMOS Bi-directional input(1)
RB2/SCK/SCL SCK ST CMOS Serial clock I/O for SPI
SCL ST OD Serial clock I/O for I2C
RB3 TTL CMOS Bi-directional input(1)
RB3/CCP1/P1A CCP1 ST CMOS Capture 1 input/Compare 1 output
P1A CMOS PWM P1A output
RB4 TTL CMOS Bi-directional input(1)
RB4/SDI/SDA SDI ST Serial data in for SPI
SDA ST OD Serial data I/O for I2C
RB5 ST CMOS Bi-directional I/O(1)
RB5/SDO/P1B SDO CMOS Serial data out for SPI
P1B CMOS PWM P1B output
RB6 TTL CMOS Bi-directional I/O(1)
T1OSO XTAL Crystal/Resonator
RB6/T1OSO/T1CKI/P1C
T1CKI ST TMR1 clock input
P1C CMOS PWM P1C output
RB7 TTL CMOS Bi-directional I/O(1)
RB7/T1OSI/P1D T1OSI XTAL TMR1 crystal/resonator
P1D CMOS PWM P1D output
Note 1: Bit programmable pull-ups.
06h, 106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xx00 uuuu uu00
86h, 186h TRISB PORTB Data Direction Register 1111 1111 1111 1111
81h, 181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
95h WPUB PORTB Weak Pull-up Control 1111 1111 1111 1111
96h IOCB PORTB Interrupt on Change Control 1111 0000 1111 0000
9Dh ANSEL ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
bit 7-0: PMD<7:0>: The value of the program memory word pointed to by PMADRH and PMADRL after a
program memory read command.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Program
Memory PC PC+1 PMADRH,PMADRL PC+3 PC+4 PC+5
ADDR
RD bit
PMDATH
PMDATL
register
Data Bus
FOSC/4 0
PSout 8
1
Sync with
1 Internal TMR0
clocks
RA4/T0CKI Programmable 0 PSout
pin Prescaler
T0SE (2 TCY delay)
3
Set interrupt
PS2, PS1, PS0 PSA flag bit T0IF
T0CS on overflow
Note 1: T0CS, T0SE, PSA, PS<2:0> (OPTION_REG<5:0>).
2: The prescaler is shared with Watchdog Timer (refer to Figure 5-2 for detailed block diagram).
8
M 1
0
RA4/T0CKI U M
X SYNC
Pin U 2 TMR0 reg
1 0
X Cycles
T0SE
T0CS
PSA Set flag bit T0IF
on Overflow
0
M 8-bit Prescaler
U
Watchdog 1 X 8
Timer
8 - to - 1MUX PS<2:0>
PSA
0 1
WDT Enable Bit
MUX PSA
WDT
Time-out
TMR1CS = 1
1 = Do not synchronize external clock input
0 = Synchronize external clock input
TMR1CS = 0
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1: TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RB6/T1OSO/T1CKI /P1C(on the rising edge)
0 = Internal clock (FOSC/4)
bit 0: TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
T1CKI
(Initially high)
T1CKI
(Initially low)
First falling edge
of the T1ON enabled
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
0Bh,8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
10Bh,18Bh
0Ch PIR1 — ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000
8Ch PIE1 — ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as ’0’. Shaded cells are not used by the Timer1 module.
The output of TMR2 (before the postscaler) is fed to the 4 PR2 reg
Synchronous Serial Port module which optionally uses
it to generate shift clock.
Note 1: TMR2 register output can be software selected
by the SSP Module as a baud clock.
0Bh,8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
10Bh,18Bh
0Ch PIR1 — ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000
8Ch PIE1 — ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
92h PR2 Timer2 Period Register 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented read as ’0’. Shaded cells are not used by the Timer2 module.
When the Capture mode is changed, a false capture Note: Clearing the CCP1CON register will force
interrupt may be generated. The user should keep bit the CCP1 compare output latch to the
CCP1IE (PIE1<2>) clear to avoid false interrupts and default low level. This is not the port data
should clear the flag bit CCP1IF following any such latch.
change in operating mode.
8.2.2 TIMER1 MODE SELECTION
8.1.4 ECCP PRESCALER
Timer1 must be running in Timer mode or Synchro-
There are four prescaler settings, specified by bits nized Counter mode if the ECCP module is using the
CCP1M<3:0>. Whenever the ECCP module is turned compare feature. In Asynchronous Counter mode, the
off or the ECCP1 module is not in capture mode, the compare operation may not work.
prescaler counter is cleared. This means that any reset
8.2.3 SOFTWARE INTERRUPT MODE
will clear the prescaler counter.
Switching from one capture prescaler to another may When generate software interrupt is chosen, the CCP1
generate an interrupt. Also, the prescaler counter will pin is not affected. Only an ECCP interrupt is generated
not be cleared, therefore the first capture may be from (if enabled).
a non-zero prescaler. Example 8-1 shows the recom-
mended method for switching between capture pres-
calers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
Value on Value on
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other
BOR resets
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TRISB PORTB Data Direction Register 1111 1111 1111 1111
TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1register xxxx xxxx uuuu uuuu
T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
CCPR1L Capture/Compare/PWM register1 (LSB) xxxx xxxx uuuu uuuu
CCPR1H Capture/Compare/PWM register1 (MSB) xxxx xxxx uuuu uuuu
CCP1CON PWM1M1 PWM1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as ’0’. Shaded cells are not used by Capture and Timer1.
CCP1/P1A RB3/CCP1/P1A
TRISB<3>
CCPR1H (Slave)
P1B RB5/SDO/P1B
OUTPUT TRISB<5>
Comparator R Q
CONTROLLER
RB6/T1OSO/T1CKI/
P1C
P1C
TMR2 (Note 1)
S TRISB<6>
P1D RB7/T1OSI/P1D
Comparator
Clear Timer, TRISB<7>
CCP1 pin and
latch D.C.
PR2 P1DEL
Note: 8-bit timer TMR2 is concatenated with 2-bit internal Q clock or 2 bits of the prescaler to create 10-bit time-base.
log ---------------
F OSC
F PWM
= ----------------------------- bits
log ( 2 ) V+ Using PWM to
Drive a Power
PIC16C717/770/771 Load
L
O
A
Note: If the PWM duty cycle value is longer than D
Duty Cycle
(2)
P1A
td
td
P1B(2)
(1) (1)
(1)
td = Deadband Delay
Note 1: At this time, the TMR2 register is equal to the PR2 register.
2: Output signals are shown as asserted high.
PIC16C717/770/771
FET
DRIVER
+
P1A V
-
+ -
LOAD
FET
DRIVER
+
P1B V
-
V-
V+
+ -
LOAD
FET FET
DRIVER DRIVER
P1B
V-
FORWARD MODE
Period
1
P1A(2) 0
Duty Cycle
1
P1B(2) 0
1
P1C(2) 0
1
P1D(2) 0
(1) (1)
REVERSE MODE
Period
Duty Cycle
1
P1A(2) 0
1
P1B(2) 0
1
P1C(2) 0
P1D(2) 1
0
(1)
(1)
Note 1: At this time, the TMR2 register is equal to the PR2 register.
2: Output signal is shown as asserted high.
V+
PIC16C717/770/771
FET FET
DRIVER DRIVER
P1D
+ -
LOAD
P1C
FET FET
DRIVER DRIVER
P1A
V-
P1B
bit 7-0: P1DEL<7:0>: PWM Delay count for Half-Bridge output mode: Number of FOSC/4 (Tosc•4) cycles
between the P1A transition and the P1B transition.
8.3.6 DIRECTION CHANGE IN FULL-BRIDGE modulated outputs, P1A and P1C signals, will transition
OUTPUT MODE to the new direction TOSC, 4•TOSC or 16•TOSC (for
Timer2 presale T2CKRS<1:0> = 00, 01 and 1x respec-
In the Full-Bridge Output mode, the PWM1M1 bit in the tively) earlier, before the end of the period. During this
CCP1CON register allows user to control the Forward/ transition cycle, the modulated outputs, P1B and P1D,
Reverse direction. When the application firmware will go to the inactive state. See Figure 8-10 for illustra-
changes this direction control bit, the ECCP module will tion.
assume the new direction on the next PWM cycle. The
current PWM cycle still continues, however, the non-
Note 1: The Direction bit in the ECCP Control Register (CCP1CON.PWM1M1) is written anytime during the PWM cycle.
2: The P1A and P1C signals switch TOSC, 4*Tosc or 16*TOSC depending on the Timer2 prescaler value earlier when
changing direction. The modulated P1B and P1D signals are inactive at this time.
P1A 1
0
1
P1B 0 (PWM)
1
P1C 0
P1D 1
0 (PWM)
ton
1
External Switch C 0
toff
1
External Switch D 0
When the ECCP module is used in the PWM mode, the The following steps should be taken when configuring
application hardware must use the proper external pull- the ECCP module for PWM operation:
up and/or pull-down resistors on the PWM output pins. 1. Configure the PWM module:
When the microcontroller powers up, all of the I/O pins
a) Disable the CCP1/P1A, P1B, P1C and/or
are in the high-impedance state. The external pull-up
P1D outputs by setting the respective
and pull-down resistors must keep the power switch
TRISB bits.
devices in the off state until the microcontroller drives
the I/O pins with the proper signal levels, or activates b) Set the PWM period by loading the PR2
the PWM output(s). register.
c) Set the PWM duty cycle by loading the
8.3.8 START-UP CONSIDERATIONS CCPR1L register and CCP1CON<5:4>
bits.
Prior to enabling the PWM outputs, the P1A, P1B, P1C
and P1D latches may not be in the proper states. d) Configure the ECCP module for the desired
Enabling the TRISB bits for output at the same time PWM operation by loading the CCP1CON
with the CCP module may cause damage to the power register. With the CCP1M<3:0> bits select
switch devices. The CCP1 module must be enabled in the active high/low levels for each PWM
the proper output mode with the TRISB bits enabled as output. With the PWM1M<1:0> bits select
inputs. Once the CCP1 completes a full PWM cycle, the one of the available output modes: Single,
P1A, P1B, P1C and P1D output latches are properly Half-Bridge, Full-Bridge, Forward or Full-
initialized. At this time, the TRISB bits can be enabled Bridge Reverse.
for outputs to start driving the power switch devices. e) For Half-Bridge output mode, set the dead-
The completion of a full PWM cycle is indicated by the band delay by loading the P1DEL register.
TMR2IF bit going from a ’0’ to a ’1’. 2. Configure and start TMR2:
a) Clear the TMR2 interrupt flag bit by clearing
the TMR2IF bit in the PIR1 register.
b) Set the TMR2 prescale value by loading the
T2CKPS<1:0> bits in the T2CON register.
c) Enable Timer2 by setting the TMR2ON bit
in the T2CON register.
3. Enable PWM outputs after a new cycle has
started:
a) Wait until TMR2 overflows (TMR2IF bit
becomes a ’1’). The new PWM cycle begins
here.
b) Enable the CCP1/P1A, P1B, P1C and/or
P1D pin outputs by clearing the respective
TRISB bits.
TABLE 8-3: REGISTERS ASSOCIATED WITH PWM
Value on Value on
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other
BOR resets
0Bh, 8Bh, INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
10Bh,
18Bh
0Ch PIR1 — ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000
8Ch PIE1 — ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000
86h, 186h TRISB PORTB Data Direction Register 1111 1111 1111 1111
11h TMR2 Timer2 register 0000 0000 0000 0000
92h PR2 Timer2 period register 1111 1111 1111 1111
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
15h CCPR1L Capture/Compare/PWM register1 (LSB) xxxx xxxx uuuu uuuu
17h CCP1CON PWM1M1 PWM1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000
97h P1DEL PWM1 Delay value 0000 0000 0000 0000
Legend: Legend: x = unknown, u = unchanged, - = unimplemented read as ’0’. Shaded cells are not used by Capture and Timer1.
SDO SDI
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 clock
SCK modes
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Input
Sample
(SMP = 1)
SSPIF
Next Q4 cycle
SSPSR to after Q2↓
SSPBUF
The SS pin allows a synchronous slave mode. The To emulate two-wire communication, the SDO pin can
SPI must be in slave mode with SS pin control be connected to the SDI pin. When the SPI needs to
enabled (SSPCON<3:0> = 0100). The pin must not operate as a receiver, the SDO pin can be configured
be driven low for the SS pin to function as an input. as an input. This disables transmissions from the SDO.
TRISB<1> must be set. When the SS pin is low, The SDI can always be left as an input (SDI function)
transmission and reception are enabled and the since it cannot create a bus conflict.
SDO pin is driven. When the SS pin goes high, the
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDI bit0
(SMP = 0) bit7 bit7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 cycle
SSPSR to after Q2Ø
SSPBUF
SS
optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDI
(SMP = 0) bit0
bit7
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 cycle
after Q2Ø
SSPSR to
SSPBUF
SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF
SDI
(SMP = 0) bit7 bit0
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
Next Q4 cycle
after Q2Ø
SSPSR to
SSPBUF
In master mode, all module clocks are halted and the A reset disables the MSSP module and terminates the
transmission/reception will remain in that state until the current transfer.
device wakes from sleep. After the device returns to
normal mode, the module will continue to transmit/
receive data.
In slave mode, the SPI transmit/receive shift register
operates asynchronously to the device. This allows the
device to be placed in sleep mode and data to be
shifted into the SPI transmit/receive shift register.
When all 8 bits have been received, the MSSP interrupt
flag bit will be set and if enabled will wake the device
from sleep.
TABLE 9-1: REGISTERS ASSOCIATED WITH SPI OPERATION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR MCLR, WDT
0Bh, 8Bh,
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
10Bh,18Bh
0Ch PIR1 — ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000
8Ch PIE1 — ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as ’0’. Shaded cells are not used by the MSSP in SPI mode.
FIGURE 9-7: I2C SLAVE MODE BLOCK Match detect Addr Match
DIAGRAM
Internal SSPADD reg
Data Bus
Read Write Start and Stop bit Set/Clear S bit
and
detect / generate Clear/Set P bit
SSPBUF reg (SSPSTAT reg)
SCL and Set SSPIF
Shift
Clock Two pins are used for data transfer. These are the SCL
pin, which is the clock, and the SDA pin, which is the
SSPSR reg
data. The MSSP module functions are enabled by set-
SDA MSb LSb
ting SSP Enable bit SSPEN (SSPCON<5>).
The MSSP module has six registers for I2C operation.
Match detect Addr Match
They are the:
• SSP Control Register (SSPCON)
SSPADD reg • SSP Control Register2 (SSPCON2)
• SSP Status Register (SSPSTAT)
Start and Set, Reset • Serial Receive/Transmit Buffer (SSPBUF)
Stop bit detect S, P bits • SSP Shift Register (SSPSR) - Not directly acces-
(SSPSTAT reg)
sible
• SSP Address Register (SSPADD)
The SSPCON register allows control of the I 2C opera-
tion. Four mode selection bits (SSPCON<3:0>) allow
one of the following I 2C modes to be selected:
• I 2C Slave mode (7-bit address)
• I 2C Slave mode (10-bit address)
• I 2C Master mode, clock = OSC/4 (SSPADD +1)
Before selecting any I 2C mode, the SCL and SDA pins
must be programmed to inputs by setting the appropri-
ate TRIS bits. Selecting an I 2C mode, by setting the
SSPEN bit, enables the SCL and SDA pins to be used
as the clock and data lines in I 2C mode.
The SSPSTAT register gives the status of the data
transfer. This information includes detection of a
START (S) or STOP (P) bit, specifies if the received
byte was data or address if the next byte is the comple-
tion of 10-bit address, and if this will be a read or write
data transfer.
9.2.1.3 SLAVE TRANSMISSION A MSSP interrupt is generated for each data transfer
byte. The SSPIF flag bit must be cleared in software,
When the R/W bit of the incoming address byte is set and the SSPSTAT register is used to determine the sta-
and an address match occurs, the R/W bit of the tus of the byte transfer. The SSPIF flag bit is set on the
SSPSTAT register is set. The received address is falling edge of the ninth clock pulse.
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit, and the SCL pin is held low. As a slave-transmitter, the ACK pulse from the master-
The transmit data must be loaded into the SSPBUF receiver is latched on the rising edge of the ninth SCL
register, which also loads the SSPSR register. Then the input pulse. If the SDA line was high (not ACK), then the
SCL pin should be enabled by setting bit CKP (SSP- data transfer is complete. When the not ACK is latched
CON<4>). The master must monitor the SCL pin prior by the slave, the slave logic is reset and the slave then
to asserting another clock pulse. The slave devices monitors for another occurrence of the START bit. If the
may be holding off the master by stretching the clock. SDA line was low (ACK), the transmit data must be
The eight data bits are shifted out on the falling edge of loaded into the SSPBUF register, which also loads the
the SCL input. This ensures that the SDA signal is valid SSPSR register. Then the SCL pin should be enabled
during the SCL high time (Figure 9-10). by setting the CKP bit.
SCL S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
Data in SCL held low
sampled while CPU
responds to SSPIF
SSPIF
BF (SSPSTAT<0>)
cleared in software From SSP interrupt
SSPBUF is written in software service routine
CKP (SSPCON<4>)
Receive First Byte of AddressR/W = 0 Receive Second Byte of Address Receive First Byte of Address R/W=1 Transmitting Data Byte ACK
SDA 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK 1 1 1 1 0 A9 A8 ACK D7 D6 D5 D4 D3 D2 D1 D0
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S Sr P
CKP has to be set for clock to be released
SSPIF
(PIR1<3>)
Cleared in software Cleared in software Cleared in software Bus Master
terminates
transfer
BF (SSPSTAT<0>)
Advanced Information
UA (SSPSTAT<1>)
DS41120A-page 81
DS41120A-page 82
Bus Master
Clock is held low until terminates
update of SSPADD has transfer
taken place
Receive First Byte of Address Receive Second Byte of Address Receive Data Byte
R/W = 0 R/W = 1
SDA ACK ACK
1 1 1 1 0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 ACK
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
PIC16C717/770/771
S P
SSPIF
(PIR1<3>)
Cleared in software Cleared in software
BF (SSPSTAT<0>)
FIGURE 9-12: I2C SLAVE-RECEIVER (10-BIT ADDRESS)
SSPBUF is written with Dummy read of SSPBUF Dummy read of SSPBUF Read of SSPBUF
contents of SSPSR to clear BF flag to clear BF flag clears BF flag
Advanced Information
UA (SSPSTAT<1>)
The general call address is one of eight addresses In 10-bit mode, the SSPADD is required to be updated
reserved for specific purposes by the I2C protocol. It for the second half of the address to match, and the UA
consists of all 0’s with R/W = 0 bit is set (SSPSTAT<1>). If the general call address is
sampled when GCEN is set while the slave is config-
The general call address is recognized when the Gen- ured in 10-bit address mode, then the second half of
eral Call Enable bit (GCEN) is enabled (SSPCON2<7> the address is not necessary, the UA bit will not be set,
is set). Following a start-bit detect, 8 bits are shifted and the slave will begin receiving data after the
into SSPSR and the address is compared against acknowledge (Figure 9-13).
SSPADD. It is also compared to the general call
address, fixed in hardware.
FIGURE 9-13: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT MODE)
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S
SSPIF
BF
(SSPSTAT<0>)
Cleared in software
SSPBUF is read
SSPOV ’0’
(SSPCON<6>)
GCEN ’1’
(SSPCON2<7>)
Internal SSPM<3:0>,
Data Bus SSPADD<6:0>
Read Write
SSPBUF Baud
Rate
Generator
SDA Shift
Acknowledge
Generate
SCL
In multi-master mode, the interrupt generation on the The master device generates all of the serial clock
detection of the START and STOP conditions allows pulses and the START and STOP conditions. A trans-
the determination of when the bus is free. The STOP fer is ended with a STOP condition or with a Repeated
(P) and START (S) bits are cleared from a reset or Start condition. Since the Repeated Start condition is
when the MSSP module is disabled. Control of the I 2C also the beginning of the next serial transfer, the I2C
bus may be taken when bit P (SSPSTAT<4>) is set, or bus will not be released.
the bus is idle with both the S and P bits clear. When In Master Transmitter mode, serial data is output
the bus is busy, enabling the SSP Interrupt will gener- through SDA, while SCL outputs the serial clock. The
ate the interrupt when the STOP condition occurs. first byte transmitted contains the slave address of the
In multi-master operation, the SDA line must be moni- receiving device (7 bits) and the Read/Write (R/W) bit.
tored for arbitration to see if the signal level is the In this case, the R/W bit will be logic '0'. Serial data is
expected output level. This check is performed in hard- transmitted 8 bits at a time. After each byte is transmit-
ware, with the result placed in the BCLIF bit. ted, an acknowledge bit is received. START and STOP
The states where arbitration can be lost are: conditions are output to indicate the beginning and the
end of a serial transfer.
• Address Transfer
• Data Transfer In Master receive mode, the first byte transmitted con-
• A Start Condition tains the slave address of the transmitting device
• A Repeated Start Condition (7 bits) and the R/W bit. In this case the R/W bit will be
• An Acknowledge Condition logic '1'. Thus the first byte transmitted is a 7-bit slave
address followed by a '1' to indicate receive bit. Serial
9.2.7 I2C MASTER OPERATION SUPPORT data is received via SDA while SCL outputs the serial
clock. Serial data is received 8 bits at a time. After each
Master Mode is enabled by setting and clearing the byte is received, an acknowledge bit is transmitted.
appropriate SSPM bits in SSPCON and by setting the START and STOP conditions indicate the beginning
SSPEN bit. Once master mode is enabled, the user and end of transmission.
has six options.
The baud rate generator used for SPI mode operation
- Assert a start condition on SDA and SCL. is now used to set the SCL clock frequency for either
- Assert a Repeated Start condition on SDA and 100 kHz, 400 kHz, or 1 MHz I2C operation. The baud
SCL. rate generator reload value is contained in the lower 7
- Write to the SSPBUF register initiating trans- bits of the SSPADD register. The baud rate generator
mission of data/address. will automatically begin counting on a write to the SSP-
- Generate a stop condition on SDA and SCL. BUF. Once the given operation is complete (i.e. trans-
- Configure the I2C port to receive data. mission of the last data bit is followed by ACK), the
- Generate an Acknowledge condition at the end internal clock will automatically stop counting and the
of a received byte of data. SCL pin will remain in its last state
A typical transmit sequence would go as follows:
Note: The MSSP Module, when configured in I2C a) The user generates a Start Condition by setting
Master Mode, does not allow queueing of the START enable bit (SEN) in SSPCON2.
events. For instance, the user is not b) SSPIF is set. The module will wait the required
allowed to initiate a start condition and start time before any other operation takes
immediately write the SSPBUF register to place.
initiate transmission before the START c) The user loads the SSPBUF with address to
condition is complete. In this case, the transmit.
SSPBUF will not be written to, and the
d) Address is shifted out the SDA pin until all 8 bits
WCOL bit will be set, indicating that a write
are transmitted.
to the SSPBUF did not occur.
e) The MSSP Module shifts in the ACK bit from the
slave device, and writes its value into the
SSPCON2 register ( SSPCON2<6>).
f) The module generates an interrupt at the end of
the ninth clock cycle by setting SSPIF.
g) The user loads the SSPBUF with eight bits of
data.
h) DATA is shifted out the SDA pin until all 8 bits
are transmitted.
SDA DX DX-1
BRG decrements
(on Q2 and Q4 cycles)
BRG
03h 02h 01h 00h (hold off) 03h 02h
value
SCL
TBRG
S
SSPEN = 1,
SSPCON<3:0> = 1000
Idle Mode
SEN (SSPCON2<0> = 1)
No
Yes No No BRG
SCL= 0? SDA = 0? Rollover?
Yes Yes
Reset BRG
Force SDA = 0,
Load BRG with
SSPADD<6:0>,
Set S bit.
No No BRG
SCL = 0? rollover?
Yes
Yes
Reset BRG
Force SCL = 0,
Start Condition Done,
Clear SEN
and set SSPIF
1st Bit
SDA
Falling edge of ninth clock Write to SSPBUF occurs here.
End of Xmit
TBRG
SCL TBRG
Sr = Repeated Start
Start
Idle Mode,
B SSPEN = 1,
SSPCON<3:0> = 1000
RSEN = 1
Force SCL = 0
No
SCL = 0?
Yes
Release SDA,
Load BRG with
SSPADD<6:0>
BRG No
rollover?
Yes
Release SCL
(Clock Arbitration)
No
SCL = 1?
Yes
Bus Collision, No
Set BCLIF, SDA = 1?
Release SDA,
Clear RSEN
Yes
C A
B
C
A
Yes
No No No BRG
SCL = 1? SDA = 0? rollover?
Yes Yes
Reset BRG
Force SDA = 0,
Load BRG with
SSPADD<6:0>
Set S
No No BRG
SCL = ’0’? rollover?
Yes Yes
Force SCL = 0,
Reset BRG Repeated Start
condition done,
Clear RSEN,
Set SSPIF.
Transmission of a data byte, a 7-bit address, or either In transmit mode, the ACKSTAT bit (SSPCON2<6>) is
half of a 10-bit address is accomplished by simply writ- cleared when the slave has sent an acknowledge
ing a value to the SSPBUF register. This action will set (ACK = 0), and is set when the slave does not acknowl-
the buffer full flag (BF) and allow the baud rate genera- edge (ACK = 1). A slave sends an acknowledge when
tor to begin counting and start the next transmission. it has recognized its address (including a general call),
Each bit of address/data will be shifted out onto the or when the slave has properly received its data.
SDA pin after the falling edge of SCL is asserted (see
data hold time spec). SCL is held low for one baud
rate generator roll over count (TBRG). Data should be
valid before SCL is released high (see data setup time
spec). When the SCL pin is released high, it is held that
way for TBRG, the data on the SDA pin must remain
stable for that duration and some hold time after the
next falling edge of SCL. After the eighth bit is shifted
out (the falling edge of the eighth clock), the BF flag is
cleared and the master releases SDA allowing the
slave device being addressed to respond with an ACK
bit during the ninth bit time, if an address match occurs
or if data was received properly. The status of ACK is
read into the ACKDT on the falling edge of the ninth
clock. If the master receives an acknowledge, the
acknowledge status bit (ACKSTAT) is cleared. If not,
the bit is set. After the ninth clock the SSPIF is set, and
the master clock (baud rate generator) is suspended
until the next data byte is loaded into the SSPBUF leav-
ing SCL low and SDA unchanged (Figure 9-23).
After the write to the SSPBUF, each bit of address will
be shifted out on the falling edge of SCL until all seven
address bits and the R/W bit are completed. On the fall-
ing edge of the eighth clock, the master will de-assert
the SDA pin allowing the slave to respond with an
acknowledge. On the falling edge of the ninth clock, the
master will sample the SDA pin to see if the address
was recognized by a slave. The status of the ACK bit is
loaded into the ACKSTAT status bit (SSPCON2<6>).
Following the falling edge of the ninth clock transmis-
sion of the address, the SSPIF is set, the BF flag is
cleared, and the baud rate generator is turned off until
another write to the SSPBUF takes place, holding SCL
low and allowing SDA to float.
Idle Mode
Write SSPBUF
Num_Clocks = 0,
BF = 1
Force SCL = 0
Release SDA so
Yes slave can drive ACK,
Num_Clocks
= 8? Force BF = 0
No
Load BRG with
Load BRG with SSPADD<6:0>,
SSPADD<6:0>, start BRG count
start BRG count,
SDA = Current Data bit
BRG No
rollover?
BRG No
rollover?
Yes
Yes Force SCL = 1,
Stop BRG, Stop BRG
Force SCL = 1
Yes
Yes
Read SDA and place into
ACKSTAT bit (SSPCON2<6>)
SDA = No Bus collision detected
Data bit? Set BCLIF, hold prescale off,
Clear XMIT enable Load BRG with
SSPADD<6:0>,
Yes count high time
No No SDA = No
BRG Yes
rollover? SCL = 0? Data bit?
Force SCL = 0,
Yes
Set SSPIF
Yes Reset BRG
Num_Clocks
= Num_Clocks + 1
SDA A7 A6 A5 A4 A3 A2 A1 ACK = 0 D7 D6 D5 D4 D3 D2 D1 D0
while CPU
responds to SSPIF
SSPIF
cleared in software service routine
cleared in software From SSP interrupt
Cleared in software
BF (SSPSTAT<0>)
Advanced Information
After start condition SEN cleared by hardware.
PEN
R/W
FIGURE 9-23: I 2C MASTER MODE TIMING (TRANSMISSION, 7 OR 10-BIT ADDRESS)
Idle mode
RCEN = 1
Num_Clocks = 0,
Release SDA
Force SCL=0,
Load BRG w/
SSPADD<6:0>,
start count
BRG No
rollover?
Yes
Release SCL
(Clock Arbitration)
SCL = 1? No
Yes
Sample SDA,
Shift data into SSPSR
BRG No SCL = 0? No
rollover?
Yes Yes
Num_Clocks
= Num_Clocks + 1
No
Num_Clocks
= 8?
Yes
Force SCL = 0,
Set SSPIF,
Set BF.
Move contents of SSPSR
into SSPBUF,
Clear RCEN.
Bus Master
ACK is not sent terminates
transfer
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SCL S P
Data shifted in on falling edge of CLK Set SSPIF at end
of receive Set SSPIF interrupt
Set SSPIF interrupt at end of acknow-
at end of receive Set SSPIF interrupt ledge sequence
at end of acknowledge
SSPIF sequence
Set P bit
SDA = 0, SCL = 1 Cleared in software Cleared in software Cleared in software Cleared in software Cleared in (SSPSTAT<4>)
while CPU software and SSPIF
responds to SSPIF
Advanced Information
BF
(SSPSTAT<0>) Last bit is shifted into SSPSR and
contents are unloaded into SSPBUF
SSPOV
FIGURE 9-25: I 2C MASTER MODE TIMING (RECEPTION 7-BIT ADDRESS)
ACKEN
PIC16C717/770/771
DS41120A-page 97
PIC16C717/770/771
9.2.13 ACKNOWLEDGE SEQUENCE TIMING the baud rate generator counts for TBRG . The SCL pin
is then pulled low. Following this, the ACKEN bit is
An acknowledge sequence is enabled by setting the automatically cleared, the baud rate generator is turned
acknowledge sequence enable bit, ACKEN off, and the MSSP module then goes into IDLE mode.
(SSPCON2<4>). When this bit is set, the SCL pin is (Figure 9-26)
pulled low and the contents of the acknowledge data
bit is presented on the SDA pin. If the user wishes to 9.2.13.1 WCOL STATUS FLAG
generate an acknowledge, then the ACKDT bit should
be cleared. If not, the user should set the ACKDT bit If the user writes the SSPBUF when an acknowledged
before starting an acknowledge sequence. The baud sequence is in progress, then WCOL is set and the
rate generator then counts for one rollover period contents of the buffer are unchanged (the write doesn’t
(TBRG), and the SCL pin is de-asserted (pulled high). occur).
When the SCL pin is sampled high (clock arbitration),
TBRG TBRG
SDA D0 ACK
SCL 8 9
SSPIF
Idle mode
Set ACKEN
Force SCL = 0
BRG Yes
rollover?
No
No SCL = 0?
Yes
No BRG
rollover?
Yes
SDA = 1?
Yes
No
Force SCL = 1
SDA ACK
P
TBRG TBRG TBRG
SCL brought high after TBRG
Idle Mode,
SSPEN = 1,
SSPCON<3:0> = 1000
Force SDA = 0
SCL doesn’t change
BRG No
rollover?
Yes
No
SDA = 0? Release SDA,
Start BRG
Yes
Start BRG
BRG No
rollover?
BRG No Yes
rollover?
Yes
Clock arbitration occurs when the master, during any While in sleep mode, the I2C module can receive
receive, transmit or repeated start/stop condition, de- addresses or data, and when an address match or
asserts the SCL pin (SCL allowed to float high). When complete byte transfer occurs, wake the processor from
the SCL pin is allowed to float high, the baud rate gen- sleep ( if the SSP interrupt is enabled).
erator (BRG) is suspended from counting until the SCL
pin is actually sampled high. When the SCL pin is sam- 9.2.17 EFFECTS OF A RESET
pled high, the baud rate generator is reloaded with the
A reset disables the MSSP module and terminates the
contents of SSPADD<6:0> and begins counting. This
current transfer.
ensures that the SCL high time will always be at least
one BRG rollover count in the event that the clock is
held low by an external device (Figure 9-30).
SCL
SDA
SDA
BCLIF
SDA
SCL
Set SEN, enable start SEN cleared automatically because of bus collision.
condition if SDA = 1, SCL=1 SSP module reset into idle state.
SEN
SSPIF
SDA = 0, SCL = 1
TBRG TBRG
SDA
FIGURE 9-34: BRG RESET DUE TO SDA COLLISION DURING START CONDITION
SDA = 0, SCL = 1
Set S Set SSPIF
Less than TBRG
TBRG
SDA SDA pulled low by other master.
Reset BRG and assert SDA
SCL s
SCL pulled low after BRG
Timeout
SEN
Set SEN, enable start
sequence if SDA = 1, SCL = 1
BCLIF ’0’
SSPIF
SDA = 0, SCL = 1 Interrupts cleared
Set SSPIF in software.
SDA
SCL
RSEN
BCLIF
Cleared in software
S ’0’ ’0’
TBRG TBRG
SDA
SCL
S ’0’ ’0’
PEN
BCLIF
P ’0’ ’0’
SDA
PEN
BCLIF
P ’0’
SSPIF ’0’
DEVICE
RP RP
RS RS
SDA
SCL
Cb=10 pF to 400 pF
Note: I2C devices with input levels related to VDD must have one common supply line to which the pull-up resistor is also connected.
0Bh, 8Bh,
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
10Bh,18Bh
0Ch PIR1 — ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000
8Ch PIE1 — ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000
0Dh PIR2 LVDIF — — — BCLIF — — CCP2IF 0--- 0--0 0--- 0--0
8Dh PIE2 LVDIE — — — BCLIE — — CCP2IE 0--- 0--0 0--- 0--0
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
91h SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000
94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as ’0’. Shaded cells are not used by the MSSP in I2C mode.
Note 1: These are the minimum trip points for the LVD. See Table 15-3 for the trip point tolerances. Selection of
reserved setting may result in an inadvertent interrupt.
10.1 Bandgap Voltage Reference Each reference, if enabled, can be output on an exter-
nal pin by setting the VRHOEN (high reference output
The bandgap module generates a stable voltage refer- enable) or VRLOEN (low reference output enable) con-
ence of over a range of temperatures and device supply trol bit. If the reference is not enabled, the VRHOEN
voltages. This module is enabled anytime any of the fol- and VRLOEN bits will have no effect on the corre-
lowing are enabled: sponding pin. The device specific pin can then be used
• Brown-out Reset as general purpose I/O.
• Low-voltage Detect Note: If VRH or VRL is enabled and the other ref-
• Either of the internal analog references (VRH, erence (VRL or VRH), the BOR, and the
VRL) LVD modules are not enabled, the band-
Whenever the above are all disabled, the bandgap gap will require a start-up time before the
module is disabled and draws no current. bandgap reference is stable. Before using
the internal VRH or VRL reference, ensure
10.2 Internal VREF for A/D Converter that the bandgap reference voltage is sta-
ble by monitoring the BGST bit in the LVD-
The bandgap output voltage is used to generate two CON register. The voltage references will
stable references for the A/D converter module. These not be reliable until the bandgap is stable
references are enabled in software to provide the user as shown by BGST being set.
with the means to turn them on and off in order to min-
imize current consumption. Each reference can be indi-
vidually enabled.
The VRH reference is enabled with control bit VRHEN
(REFCON<7>). When this bit is set, the gain amplifier
is enabled. After a specified start-up time a stable ref-
erence of 4.096V nominal is generated and can be
used by the A/D converter as a reference input.
The VRL reference is enabled by setting control bit
VRLEN (REFCON<6>). When this bit is set, the gain
amplifier is enabled. After a specified start up time a
stable reference of 2.048V nominal is generated and
can be used by the A/D converter as a reference input.
Each voltage reference is available for external use via
VRL and VRH pins.
LVDCON REFCON
VDD
LVDEN
VRHEN + VRLEN
generates
16 to 1 MUX
RA1/AN1/LVDIN LVDIF
VRH
BODEN
BGAP VRL
LVDEN
The LVD module is enabled by setting the LVDEN bit in If the bandgap reference voltage is previously unused
the LVDCON register. The “trip point” voltage is the by either the brown-out circuitry or the voltage refer-
minimum supply voltage level at which the device can ence circuitry, then the bandgap circuit requires a time
operate before the LVD module asserts an interrupt. to start-up and become stable before a low voltage con-
When the supply voltage is equal to or less than the trip dition can be reliably detected. The low-voltage inter-
point, the module will generate an interrupt signal set- rupt flag is prevented from being set until the bandgap
ting interrupt flag bit LVDIF. If interrupt enable bit LVDIE has reached a stable reference voltage.
was set, then an interrupt is generated. The LVD inter- When the bandgap is stable the BGST (LVDCON<5>)
rupt can wake the device from sleep. The "trip point" bit is set indicating that the low-voltage interrupt flag bit
voltage is software programmable to any one of 16 val- is released to be set if VDD is equal to or less than the
ues, five of which are reserved (See Figure 10-1). The LVD trip point.
trip point is selected by programming the LV<3:0> bits
(LVDCON<3:0>). 10.3.1 EXTERNAL ANALOG VOLTAGE INPUT
Note: The LVDIF bit can not be cleared until the The LVD module has an additional feature that allows
supply voltage rises above the LVD trip the user to supply the trip voltage to the module from
point. If interrupts are enabled, clear the an external source. This mode is enabled when
LVDIE bit once the first LVD interrupt LV<3:0> = 1111. When these bits are set the compar-
occurs to prevent reentering the interrupt ator input is multiplexed from an external input pin
service routine immediately after exiting (RA1/AN1/LVDIN).
the ISR.
Once the LV bits have been programmed for the speci-
fied trip voltage, the low-voltage detect circuitry is then
enabled by setting the LVDEN (LVDCON<4>) bit.
The value that is in the ADRESH and ADRESL regis- The A/D conversion results can be left justified (ADFM
ters are not modified for a Power-on Reset. The bit cleared), or right justified (ADFM bit set).
ADRESH and ADRESL registers will contain unknown Figure 11-1 through Figure 11-2 show the A/D result
data after a Power-on Reset. data format of the PIC16C717/770/771.
Right Justified
MSB LSB
(ADFM = 1)
bit7 bit7
After the A/D module has been configured as desired, 11.2.2 CONFIGURING THE REFERENCE
the selected channel must be acquired before the con- VOLTAGES
version is started. The analog input channels must
have their corresponding TRIS and ANSEL bits The VCFG bits in the ADCON1 register configure the
selected as an input. To determine acquisition time, see A/D module reference inputs. The reference high
Section 11.6. After this acquisition time has elapsed, input can come from an internal reference (VRH) or
the A/D conversion can be started. The following steps (VRL), an external reference (VREF+), or AVDD. The
should be followed for doing an A/D conversion: low reference input can come from an internal refer-
ence (VRL), an external reference (VREF-), or AVSS. If
11.2 Configuring the A/D Module an external reference is chosen for the reference high
or reference low inputs, the port pin that multiplexes
11.2.1 CONFIGURING ANALOG PORT PINS the incoming external references is configured as an
analog input, regardless of the values contained in the
The ANSEL and TRIS registers control the operation
A/D port configuration bits (PCFG<3:0>).
of the A/D port pins. The port pins that are desired as
analog inputs must have their corresponding TRIS bit
set (input). If the TRIS bit is cleared (output), the digital
output level (VOH or VOL) will be converted. The proper
ANSEL bits must be set (analog input) to disable the
digital input buffer.
The A/D operation is independent of the state of the
TRIS bits and the ANSEL bits.
Note 1: When reading the PORTA or PORTB reg-
ister, all pins configured as analog input
channels will read as ’0’.
2: Analog levels on any pin that is defined as
a digital input, including the ANx pins, may
cause the input buffer to consume current
that is out of the devices specification.
CHS<3:0>
VAIN RB1/AN5/SS
(Input voltage) RB0/AN4/INT
RA3/AN3/VREF+/VRH
RA2/AN2/VREF-/VRL
RA1/AN1
AVDD
RA0/AN0
VREF+ VRH
(Reference VRL
voltage +)
A/D VCFG<2:0>
Converter
VREF-
VRL
(Reference
voltage -)
AVSS
VCFG<2:0>
A/D Reference
A/D Clock Source (TAD) Device Frequency
Source
Operation ADCS<1:0> 20 MHz 5 MHz 4 MHz 1.25 MHz
2 TOSC 00 100 ns(2) 400 ns(2) 500 ns(2) 1.6 µs
External VREF or
8 TOSC 01 800 ns(2) 1.6 µs 2.0 µs 6.4 µs
Analog Supply
32 TOSC 10 1.6 µs 6.4 µs 8.0 µs(3) 24 µs(3)
A/D RC 11 2 - 6 µs(1,4) 2 - 6 µs(1,4) 2 - 6 µs(1,4) 2 - 6 µs(1,4)
Internal VRH or 16 TOSC 00 800 ns(2) 3.2 µs(2) 4 µs(2) 12.8 µs
VRL 64 TOSC 01 6.4 µs(2) 12.8 µs 16 µs 51.2 µs
256 TOSC 10 12.8 µs 51.2 µs 64 µs(3) 192 µs(3)
A/D RC 11 16 - 48 µs(4,5) 16 - 48 µs(4,5) 16 - 48 µs(4,5) 16 - 48 µs(4,5)
Legend: Shaded cells are outside of recommended range.
Note 1: The A/D RC source has a typical TAD time of 4 µs for VDD > 3.0V.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: When the device frequency is greater than 1 MHz, the A/D RC clock source is only recommended if the conversion will be
performed during sleep.
5: The resource has a typical TAD time of 32 µs for VDD > 3.0V.
Yes
ADON = 0?
No
Sample
Selected Channel
Yes
GO = 0?
No
A/D Clock
Yes Start of A/D SLEEP Yes Finish Conversion
Conversion Delayed Instruction? GO = 0
= RC? 1 Instruction Cycle ADIF = 1
No No
Wait 2 Tad
TACQ = 5 µs
+ 3.3 µs
+ [(50°C - 25°C)(0.05 µs / °C)]
VSS
8Ch PIE1 — ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000
1Eh ADRESH A/D High Byte Result Register xxxx xxxx uuuu uuuu
9Eh ADRESL A/D Low Byte Result Register xxxx xxxx uuuu uuuu
9Bh REFCON VRHEN VRLEN VRHOEN VRLOEN — — — — 0000 ---- 0000 ----
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE CHS3 ADON 0000 0000 0000 0000
9Fh ADCON1 ADFM VCFG2 VCFG1 VCFG0 — — — — 0000 ---- 0000 ----
05h PORTA PORTA Data Latch when written: PORTA pins when read 000x 0000 000u 0000
06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xx00 uuuu uu00
85h TRISA PORTA Data Direction Register 1111 1111 1111 1111
86h TRISB PORTB Data Direction Register 1111 1111 1111 1111
9Dh ANSEL ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented read as ’0’. Shaded cells are not used for A/D conversion.
CP CP BORV1 BORV0 CP CP — BODEN MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 Register: CONFIG
bit13 12 11 10 9 8 7 6 5 4 3 2 1 bit0 Address 2007h
Note 1: Enabling Brown-out Reset automatically enables the Power-up Timer (PWRT), regardless of the value of bit PWRTE.
Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled.
2: All of the CP bits must be given the same value to enable code protection.
Ranges Tested:
Mode Freq OSC1 OSC2
XT 455 kHz 68 - 100 pF 68 - 100 pF
2.0 MHz 15 - 68 pF 15 - 68 pF
4.0 MHz 15 - 68 pF 15 - 68 pF
HS 8.0 MHz 10 - 68 pF 10 - 68 pF
16.0 MHz 10 - 22 pF 10 - 22 pF
These values are for design guidance only. See
notes at bottom of page.
All resonators used did not have built-in capacitors.
For timing insensitive applications, the ER (External In the INTRC and ER modes, the PIC16C717/770/771
Resistor) clock mode offers additional cost savings. can be configured to provide a clock out signal by pro-
Only one external component, a resistor connected to gramming the configuration word. The oscillator fre-
the OSC1 pin and VSS, is needed to set the operating quency, divided by 4, can be used for test purposes or
frequency of the internal oscillator. The resistor draws to synchronize other logic.
a DC bias current which controls the oscillation fre- In the INTRC and ER modes, if the CLKOUT output is
quency. In addition to the resistance value, the oscilla- enabled, CLKOUT is held low during reset.
tor frequency will vary from unit to unit, and as a
function of supply voltage and temperature. Since the 12.2.7 DUAL SPEED OPERATION FOR ER AND
controlling parameter is a DC current and not a capac- INTRC MODES
itance, the particular package type and lead frame will
not have a significant effect on the resultant frequency. A software programmable dual speed oscillator is avail-
able in either ER or INTRC oscillator modes. This fea-
Figure 12-4 shows how the controlling resistor is con-
ture allows the applications to dynamically toggle the
nected to the PIC16C717/770/771. For Rext values
oscillator speed between normal and slow frequencies.
below 38k ohms, the oscillator operation may become
The nominal slow frequency is 37KHz. In ER mode, the
unstable, or stop completely. For very high Rext values
slow speed operation is fixed and does not vary with
(e.g. 1M), the oscillator becomes sensitive to noise,
resistor size. Applications that require low current
humidity and leakage. Thus, we recommend keeping
power savings, but cannot tolerate putting the part into
Rext between 38k and 1M ohms.
sleep, may use this mode.
FIGURE 12-4: EXTERNAL RESISTOR The OSCF bit in the PCON register is used to control
dual speed mode. See the PCON Register,
Register 2-8, for details.
PIC16C717/770/771 When changing the INTRC or ER internal oscillator
speed, there is a period of time when the processor is
RA6/OSC2/CLKOUT
inactive. When the speed changes from fast to slow, the
processor inactive period is in the range of 100 µS to
RA7/OSC1/CLKIN 300 µS. For speed change from slow to fast, the pro-
cessor is in active for 1.25 µS to 3.25 µS.
REXT
External
Reset
MCLR
SLEEP
WDT Time-out
Module
OST/PWRT
OST
Chip_Reset
10-bit Ripple counter R Q
OSC1
PWRT
Dedicated
Oscillator 10-bit Ripple counter
Enable PWRT
Enable OST
POR BOR TO PD
0 1 1 1 Power-on Reset
0 x 0 x Illegal, TO is set on POR
0 x x 0 Illegal, PD is set on POR
1 0 1 1 Brown-out Reset
1 1 0 1 WDT Reset
1 1 0 0 WDT Wake-up
1 1 u u MCLR Reset during normal operation
1 1 1 0 MCLR Reset during SLEEP or interrupt wake-up from SLEEP
VDD
MCLR
INTERNAL POR
TPWRT
OST TIME-OUT
INTERNAL RESET
VDD
MCLR
INTERNAL POR
TPWRT
OST TIME-OUT
INTERNAL RESET
FIGURE 12-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
OST TIME-OUT
INTERNAL RESET
MCLR
INTERNAL POR
TPWRT (1)
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
LVDIF
LVDIE
BCLIF
BCLIE
0
M Postscaler
1 U
WDT Timer X
8
8 - to - 1 MUX PS<2:0>(1)
PSA
WDT
Enable Bit(2)
To TMR0 (Figure 5-2)
0 1
MUX PSA(1)
WDT
Note 1: PSA and PS<2:0> are bits in the OPTION_REG register. Time-out
2: WDTE bit in the configuration word.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
2007h Config. bits(1) — BODEN MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0
81h,181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Figure 12-1 for the full description of the configuration word bits.
External MCLR Reset will cause a device reset. All To ensure that the WDT is cleared, a CLRWDT instruc-
other events are considered a continuation of program tion should be executed before a SLEEP instruction.
execution and cause a "wake-up". The TO and PD bits
in the STATUS register can be used to determine the
cause of device reset. The PD bit, which is set on
power-up, is cleared when SLEEP is invoked. The TO
bit is cleared if a WDT time-out occurred (and caused
wake-up).
The following peripheral interrupts can wake the device
from SLEEP:
1. TMR1 interrupt. Timer1 must be operating as
an asynchronous counter.
2. CCP capture mode interrupt.
3. Special event trigger (Timer1 in asynchronous
mode using an external clock).
4. SSP (Start/Stop) bit detect interrupt.
5. SSP transmit or receive in slave mode (SPI/I2C).
6. A/D conversion (when A/D clock source is RC).
7. Low-voltage detect.
Other peripherals cannot generate interrupts since dur-
ing SLEEP, no on-chip clocks are present.
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(3) Tost(1)
INT pin
INTF flag
(INTCON<1>)
Note 1: TOST = 1024TOSC (drawing not to scale) This delay applies to LP, XT and HS modes only.
2: GIE = ’1’ assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = ’0’, execution will continue in-line.
3: CLKOUT is not available in these osc modes, but shown here for timing reference.
DECF Decrement f
Syntax: [label] DECF f,d INCF Increment f
Operands: 0 ≤ f ≤ 127 Syntax: [ label ] INCF f,d
d ∈ [0,1] Operands: 0 ≤ f ≤ 127
Operation: (f) - 1 → (destination) d ∈ [0,1]
Status Affected: Z Operation: (f) + 1 → (destination)
Description: Decrement register ’f’. If ’d’ is 0, Status Affected: Z
the result is stored in the W regis- Description: The contents of register ’f’ are
ter. If ’d’ is 1, the result is stored incremented. If ’d’ is 0, the result
back in register ’f’. is placed in the W register. If ’d’ is
1, the result is placed back in reg-
ister ’f’.
MOVWF Move W to f
IORWF Inclusive OR W with f Syntax: [ label ] MOVWF f
Syntax: [ label ] IORWF f,d Operands: 0 ≤ f ≤ 127
Operands: 0 ≤ f ≤ 127 Operation: (W) → (f)
d ∈ [0,1]
Status Affected: None
Operation: (W) .OR. (f) → (destination)
Description: Move data from W register to reg-
Status Affected: Z ister 'f'.
Description: Inclusive OR the W register with
register 'f'. If 'd' is 0 the result is
placed in the W register. If 'd' is 1
the result is placed back in regis-
ter 'f'.
NOP No Operation
Syntax: [ label ] NOP
MOVF Move f Operands: None
Syntax: [ label ] MOVF f,d Operation: No operation
Operands: 0 ≤ f ≤ 127 Status Affected: None
d ∈ [0,1]
Description: No operation.
Operation: (f) → (destination)
Status Affected: Z
Description: The contents of register f are
moved to a destination dependant
upon the status of d. If d = 0, des-
tination is W register. If d = 1, the
destination is file register f itself. d
= 1 is useful to test a file register
since status flag Z is affected.
Description: Subtract (2’s complement method) Description: Exclusive OR the contents of the
W register from register 'f'. If 'd' is 0, W register with register 'f'. If 'd' is
the result is stored in the W regis- 0, the result is stored in the W
ter. If 'd' is 1, the result is stored register. If 'd' is 1, the result is
back in register 'f'. stored back in register 'f'.
14.5 MPLAB-SIM Software Simulator ICEPIC is a low-cost in-circuit emulation solution for the
Microchip Technology PIC16C5X, PIC16C6X,
The MPLAB-SIM Software Simulator allows code PIC16C7X, and PIC16CXXX families of 8-bit one-time-
development in a PC host environment by simulating programmable (OTP) microcontrollers. The modular
the PICmicro series microcontrollers on an instruction system can support different subsets of PIC16C5X or
level. On any given instruction, the data areas can be PIC16CXXX products through the use of
examined or modified and stimuli can be applied from interchangeable personality modules or daughter
a file or user-defined key press to any of the pins. The boards. The emulator is capable of emulating without
execution can be performed in single step, execute until target application circuitry being present.
break, or trace mode.
14.9 MPLAB-ICD In-Circuit Debugger
MPLAB-SIM fully supports symbolic debugging using
MPLAB-C17 and MPLAB-C18 and MPASM. The Soft- Microchip’s In-Circuit Debugger, MPLAB-ICD, is a pow-
ware Simulator offers the flexibility to develop and erful, low-cost run-time development tool. This tool is
debug code outside of the laboratory environment mak- based on the flash PIC16F877 and can be used to
ing it an excellent multi-project software development develop for this and other PICmicro microcontrollers
tool. from the PIC16CXXX family. MPLAB-ICD utilizes the
In-Circuit Debugging capability built into the
14.6 MPLAB-ICE High Performance
PIC16F87X. This feature, along with Microchip’s In-Cir-
Universal In-Circuit Emulator with cuit Serial Programming protocol, offers cost-effective
MPLAB IDE in-circuit flash programming and debugging from the
graphical user interface of the MPLAB Integrated
The MPLAB-ICE Universal In-Circuit Emulator is
Development Environment. This enables a designer to
intended to provide the product development engineer
develop and debug source code by watching variables,
with a complete microcontroller design tool set for
single-stepping and setting break points. Running at
PICmicro microcontrollers (MCUs). Software control of
full speed enables testing hardware in real-time. The
MPLAB-ICE is provided by the MPLAB Integrated
MPLAB-ICD is also a programmer for the flash
Development Environment (IDE), which allows editing,
PIC16F87X family.
“make” and download, and source debugging from a
single environment.
24CXX/
25CXX/
HCSXXX
PIC14000
MCP2510
PIC16C5X
PIC16C6X
PIC16C7X
PIC16C8X
PIC17C4X
MCRFXXX
TABLE 14-1:
PIC16F62X
PIC16F8XX
PIC16C7XX
PIC16C9XX
PIC17C7XX
PIC18CXX2
PIC12CXXX
PIC16CXXX
MPLAB Integrated
Development Environment
á
á
á
á
á
á
á
á
á
á
á
á
MPLAB C17 Compiler
á á
á á
MPLAB C18 Compiler
Software Tools
MPASM/MPLINK
á
á
á á
á á
á á á
PICMASTER/PICMASTER-CE
á á á
á á á
á á á
ICEPIC Low-Cost
Emulators
In-Circuit Emulator
á á á á
á á á á
á á á á
á á á á
á á á á
á á á á
á á á á
á á á á
MPLAB-ICD In-Circuit Debugger * *
á
á
á
PICSTARTPlus
Low-Cost Universal Dev. Kit **
á
á
á
á
á
á
á
á
á
á
á
á
á
á
PRO MATE II
Universal Programmer **
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
á
Programmers Debugger
SIMICE
á
PICDEM-1 †
DEVELOPMENT TOOLS FROM MICROCHIP
á á
á
á
á
PICDEM-2 † †
á
á á
á
Advanced Information
PICDEM-3
á
PICDEM-14A
á
PICDEM-17
á
* Contact the Microchip Technology Inc. web site at www.microchip.com for information on how to use the MPLAB-ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77
** Contact Microchip Technology Inc. for availability date.
† Development tool is available on select devices.
PIC16C717/770/771
DS41120A-page 153
PIC16C717/770/771
NOTES:
6.0
5.5
5.0
4.5
VDD
(Volts)
4.0
3.5
3.0
2.5
0 4 10 20 25
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
6.0
5.5
5.0
4.5
VDD
(Volts)
4.0
3.5
3.0
2.5
0 4 10 20 25
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
6.0
5.5
5.0
4.5
VDD
(Volts)
4.0
3.5
3.0
2.5
0 4 10 20 25
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS 3. TCC:ST (I2C specifications only)
2. TppS 4. Ts (I2C specifications only)
T
F Frequency T Time
Lowercase letters (pp) and their meanings:
pp
cc CCP1 osc OSC1
ck CLKOUT rd RD
cs CS rw RD or WR
di SDI sc SCK
do SDO ss SS
dt Data in t0 T0CKI
io I/O port t1 T1CKI
mc MCLR wr WR
Uppercase letters and their meanings:
S
F Fall P Period
H High R Rise
I Invalid (Hi-impedance) V Valid
L Low Z Hi-impedance
I2C only
AA output access High High
BUF Bus free Low Low
TCC:ST (I2C specifications only)
CC
HD Hold SU Setup
ST
DAT DATA input hold STO STOP condition
STA START condition
VDD/2
RL
CL CL
Pin Pin
VSS VSS
RL = 464Ω
CL = 50 pF for all pins except OSC2
15 pF for OSC2 output
Q4 Q1 Q2 Q3
OSC1
10 11
CLKOUT
13 12
19 18
14 16
I/O Pin
(input)
17 15
20, 21
OSC1
1 3 3 4 4
2
CLKOUT
Parameter
No.
Sym Characteristic Min* Typ(1) Max* Units Conditions
FIGURE 15-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O Pins
VDD BVDD
35
VDD
RA4/T0CKI
40 41
42
RC0/T1OSO/T1CKI
45 46
47 48
TMR0 or
TMR1
RB3/CCP1/P1A
(Capture Mode)
50 51
52
RB3/CCP1/P1A
(Compare or PWM Mode)
53 54
Enable Bandgap
TBGAP
Bandgap stable
VDD
VLVD
BSF ADCON0, GO
1/2 TCY
134
131
Q4
130
A/D CLK
A/D DATA 11 10 9 8 3 2 1 0
ADIF
GO DONE
SAMPLING STOPPED
SAMPLE 132
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
BSF ADCON0, GO
134
131
Q4
130
A/D CLK
A/D DATA 11 10 9 8 3 2 1 0
ADIF
GO DONE
SAMPLING STOPPED
SAMPLE 132
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
BSF ADCON0, GO
1/2 TCY
134
131
Q4
130
A/D CLK
A/D DATA 9 8 7 6 3 2 1 0
ADIF
GO DONE
SAMPLING STOPPED
SAMPLE 132
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
BSF ADCON0, GO
134
131
Q4
130
A/D CLK
A/D DATA 9 8 7 6 3 2 1 0
ADIF
GO DONE
SAMPLING STOPPED
SAMPLE 132
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
XXXXXXXX PIC16C717/JW
XXXXXXXX
YYWWNNN 9905017
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
* Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask
rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with
your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
XXXXXXXXXXX PIC16C770
XXXXXXXXXXX 20I/SS
YYWWNNN 9917017
XXXXXXXX PIC16C770/JW
XXXXXXXX
YYWWNNN 9905017
E1
n 1 α
E A2
c L
A1
B1
β
B p
eB
E1
W2 D
n 1
W1
A A2
c L
A1
eB B1
B p
E
p
E1
2
B n 1
h
α
45°
c
A A2
φ
β L A1
E1
n 1 α
A A2
c L
A1
β B1
eB B p
E
E1
p
2
B n 1
h
α
45°
c
A A2
φ
β L A1
E1
p
B 2
n 1
c
A A2
L A1
β
Program Memory 2K 2K 4K
Packages 18-pin PDIP, 18-pin windowed 20-pin PDIP, 20-pin windowed 20-pin PDIP, 20-pin windowed
CERDIP, 18-pin SOIC, CERDIP, 20-pin SOIC, CERDIP, 20-pin SOIC,
20-pin SSOP 20-pin SSOP 20-pin SSOP
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________ FAX: (______) _________ - _________
Application (optional):
Would you like a reply? Y N
Questions:
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
8. How would you improve our software, systems, and silicon products?
* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of
each oscillator type (including LC devices).
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
All rights reserved. © 1999 Microchip Technology Incorporated. Printed in the USA. 11/99 Printed on recycled paper.
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by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products
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