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Counters and Counter Applications

An important application of flip-flops is in the design digital counters. These devices generate binary
numbers in a specified count sequence when triggered by an incoming clock waveform. On each
trigger, the counter advances to the next number in the sequence. After reaching the final state in the
sequence, the counter then recycles. Counters may be used to count up or down, to cycle through
memory addresses in microprocessors applications, to generate waveforms of particular patterns and
frequencies, and to activate other logic circuits in a complex process.

Asynchronous Counters
The term asynchronous refers to events that do not have a fixed time relationship with each other and
generally do not occur at the same time. An asynchronous counter is one in which the flip-flops with in
the counter do not change states at exactly the same time because they do not have a common clock
pulse.

2-Bit Asynchronous Binary Counter


The figure below shows a 2 – bit counter for asynchronous operation. Note that the clock is applied at
the clock input of the first flip-flop which is always the least significant bit.

3 bit asynchronous counter

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4 bit asynchronous counters

Asynchronous Decade Counters ( MOD 10 Counter)


The modulus of a counter is the number of unique states through which the counter will sequence. The
maximum possible number of states (maximum modulus of a counter is 2 n . Where n is the number of flip-flops
in the counter. Counters can be designed to have a number of states in their sequence that is less than the
maximum of 2n. This type of sequence is called truncated sequence. Decade counters have 10 count sequences
from 0 to 9. That is when the sequence reaches 1010 we need to reset all the flip-flops. So that we reset the
flip-flops using NAND gate with input from those that have 1 in 1010 sequence.

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Asynchronous modulo 12 counter
This counter has 12 count sequences from 0 through 11 and we need to recycle the count when it reaches 1100

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Synchronous Counter Operation
The term synchronous refers to events that have a fixed time relationship with each other. A
synchronous counter is one in which all the flip-flops in the counter are clocked at the same time by a
common clock pulse. Note that in all the designs shown below the right most flip-flop is used for the
least significant bit.

Before proceeding with specific counter design technique, let’s begin with a general definition of a
sequential circuit or state machine. A general sequential circuit consists of a combinational logic
section and a memory section as shown in the figure below. In a clocked sequential circuit, there is a
clock input to the memory section.

The information stored in the memory section, as well as the inputs to the combinational logic

( I 0 , I1 , I 2 ,. . . , I m ) is required for proper operation of the circuit. At any given time, the memory is in a
state called present state and will advance to the next state on a clock pulse as determined by
Y0 , Y1 , Y2 ,. . . , Yp
conditions on the excitation lines ( ). The present state of the memory is represented by
Q0 , Q1 , Q2 ,. . . , Qx I 0 , I1 , I 2 ,. . . , I m
the state variables ( ). These state variables along with the inputs ( ),
Q , Q , Q ,. . . , Qn
determine the system outputs ( 0 1 2 ). Not all sequential circuits have input and output
variables as in the general model just discussed. However, all have excitation variables and state
variables. Counters are a special case of clocked sequential circuits. Now we shall see a generalized
procedure in the design of synchronous counters.

Step 1: State Diagram

The first step in the design of a counter is to create a state diagram. A state diagram shows the
progression of states through which the counter advances when it is clocked. As an example the figure
shown below is the state diagram for BCD counting sequence. The state diagram can be developed
using binary values or actual decimal values. The state diagrams shown below indicate this.
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Step 2: Flip-flop Excitation (transition) table

Counters can be designed using J-K flip-flop or D-flip-flops. So knowing the excitation table of both
QN
these flip-flops is a must in the design of synchronous counters. In the excitation table represents

current state and QN +1 represents the next state. J, K and D are the inputs corresponding to the output

transitions QN � QN +1 . In the table X represents “don’t care”.

Output Transitions J-K FF inputs D-FF input


Q Q J K D
Current State ( N ) Next State ( N +1 )
0 0 0 X 0
0 1 1 X 1
1 0 X 1 0
1 1 X 0 1

To design the counter, the transition table is applied to each of the flip-flops in the counter. The next
step will then be to prepare the complete next state table of the counter for each flip-flop.

Step 3: Complete Next State Table

Once the sequential circuit is defined by the state diagram, the next step is to derive the complete
next state table which lists each state of the counter (Present State), next state and control inputs of
the flip-flops. The next state is the state that the counter goes to from its present state upon
application of a cock pulse. The next state table is derived from the state diagram in step 1 and the
transition table in step 2. As an example let us prepare the complete next state table of the gray-code
counter listed in step 1. The 3 bit gray code counter requires 3 flip-flops for the complete design so we
will have 3 current state and 3 next state variables.

Current State Next State J-K flip-flop inputs D- FF inputs


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Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0 D2 D1 D0
0 0 0 0 0 1 0 X 0 X 1 X 0 0 1
0 0 1 0 1 1 0 X 1 X X 0 0 1 1
0 1 1 0 1 0 0 X X 0 X 1 0 1 0
0 1 0 1 1 0 1 X X 0 0 X 1 1 0
1 1 0 1 1 1 X 0 X 0 1 X 1 1 1
1 1 1 1 0 1 X 0 X 1 X 0 1 0 1
1 0 1 1 0 0 X 0 0 X X 1 1 0 0
1 0 0 0 0 0 X 1 0 X 0 X 0 0 0

Step 4: Karnaugh Map

Once the complete next state table is developed K-map can be used to determine the logic required
for each J and K inputs if we are using J-K flip-flops for the design or D inputs if we are using D-flip-
flops. From the above next state table let us build the K-map for each control inputs.

Using J-K flip-flop

Using D-flip-flop

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Step 5: Logic Expression for each flip-flop inputs

From the K-maps in step 4 write the logic expressions for the J and K or D inputs depending on the
type of flip-flop you are using for your counter design.

Using the J-K flip-flop: the resulting Boolean expressions from each K-map are:

J 0 = Q 2Q1 + Q2 Q1 = Q2 �Q1 K 0 = Q2 Q1 + Q2Q1 = Q2 �Q1

J1 = Q2Q0 K1 = Q2Q0

J 2 = Q1 Q0 K 2 = Q1 Q0

Using D-flip-flop: the resulting Boolean expressions obtained from the K-map are:

D2 = Q2Q0 + Q1 Q0 D1 = Q2Q0 + Q1 Q0 D0 = Q2 Q1 + Q2Q1 = Q2 �Q1


, ,

Step 6: Counter Implementation

The final step is to implement the combinational logic from the Boolean expressions obtained in step 5
for the J and K inputs if we are using J-K flip-flop for our design or D inputs if we use D-flip-flops.

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Example 1

Design a 2 bit synchronous counter with the following count sequence:

01230...
Step 1: State diagram

Develop the state diagram of count sequence 0  1  2  3  0  . . .

Step2: Transition table of the J-K or D flip-flop

Prepare the transition table for the flip-flop type you are going to use for your design

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Step 3: Complete Next Table

Current State Next State J-K flip-flop inputs D FF inputs


Q1 Q0 Q1 Q0 J1 K1 J0 K0 D1 D0

Step 4: Karnaugh map

Develop the K-map for all the J, K and D inputs listed above

Step 5: Logic Expression for each flip-flop inputs

For J-K flip-flop:

For D-flip-flop:

Step 6: Implementation of the Circuit

Implement the counter circuit using combinational logic based on the logic expression in step 6
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Using J-K flip-flop:
U4
1
Key = Space
U1 U2 U5
SET SET
J Q J Q

CLK CLK
DCD_HEX
K ~Q K ~Q
RESET RESET

JK_FF JK_FF
U3

40 Hz

Using D-flip-flop:

Example 2

Design a synchronous counter with the following irregular binary count sequence:

12571...
Step 1: State diagram: Develop the state diagram of count sequence 0  1  2  3  0  . . .

Step2: Transition table of the J-K or D flip-flop: Prepare the transition table for the flip-flop type you
are going to use for your design

Step 3: Complete Next State Table

Current State Next State J-K flip-flop inputs D- FF inputs

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Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0 D2 D1 D0

Step 4: Karnaugh Map

Using J-K flip-flop

Using D-flip-flop

Step 5: Logic Expression for each flip-flop inputs

From the K-maps in step 4 write the logic expressions for the J and K or D inputs depending on the
type of flip-flop you are using for your counter design.

Using the J-K flip-flop: the resulting Boolean expressions from each K-map are:
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J 0 =1 K 0 = Q2 J1 = K1 =1 J 2 = K 2 = Q1 K 2 = Q1 Q0

Using D-flip-flop: the resulting Boolean expressions obtained from the K-map are:

Step 6: Counter Implementation

Using J-K flip-flop:

Using D- flip-flop:

Example 3

Design a synchronous 3 bit UP / DOWN counter with natural binary counting sequence using J-K flip-
flops.

Step 1: State diagram: Develop the state diagram. Assuming Y=0 for UP and Y=1 for DOWN
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Step2: Transition table of the J-K or D flip-flop: Prepare the transition table for the flip-flop type you
are going to use for your design

Step 3: Complete Next Table

Select Current State Next State J-K flip-flop inputs

Y Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0
0 0 0 0 0 0 1
0 0 0 1 0 1 0
0 0 1 0 0 1 1
0 0 1 1 1 0 0
0 1 0 0 1 0 1
0 1 0 1 1 1 0
0 1 1 0 1 1 1
0 1 1 1 0 0 0
1 0 0 0 1 1 1
1 0 0 1 0 0 0
1 0 1 0 0 0 1
1 0 1 1 0 1 0
1 1 0 0 0 1 1
1 1 0 1 1 0 0
1 1 1 0 1 0 1
1 1 1 1 1 1 0

Step 4: Karnaugh Map

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Step 5: Logic Expression for each flip-flop inputs

From the K-maps in step 4 write the logic expressions for the J and K or D inputs depending on the
type of flip-flop you are using for your counter design.

Using the J-K flip-flop: the resulting Boolean expressions from each K-map are:

J 0 = K 0 =1 J1 = K1 = SQ0 + SQ0 = S �Q0 J 2 = K 2 = Y Q1 Q0 + SQ1Q0


Step 6: Counter Implementation
S
1
Key = Space
U11
NOT

U4

U9
AND3
1

Key = Space U1 U2 U3
SET U7 SET U6 SET
J Q J Q J Q

CLK CLK CLK


XOR2 OR2
K ~Q K ~Q K ~Q
RESET RESET RESET

JK_FF U5 JK_FF
JK_FF

U10 AND3

40 Hz

Example 4

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Design a synchronous counter which counts in the following sequence

When Y = 0  count sequence is 001000110101001 . . .

When Y=1  count sequence is 001111100011001 . . .

Step 1: State diagram: Develop the state diagram.

Step2: Transition table of the J-K:

Prepare the transition table for the flip-flop type you are going to use for your design

Step 3: Complete Next Table

Select Current State Next State J-K flip-flop inputs

Y Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0
0 0 0 1 0 0 0
0 0 0 0 1 1 0
0 1 1 0 1 0 1
0 1 0 1 0 0 1
1 0 0 1 1 1 1
1 1 1 1 1 0 0
1 1 0 0 0 1 1
1 0 1 1 0 0 1

Step 4: Karnaugh Map

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Step 5: Logic Expression for each flip-flop inputs

From the K-maps in step 4 write the logic expressions for the J and K or D inputs depending on the
type of flip-flop you are using for your counter design.

Using the J-K flip-flop: the resulting Boolean expressions from each K-map are:

J 0 = Q2 K 0 = Y �Q2 J1 = Q0 + Y , K1 = 1 J 2 = Q0 + Y Q1 , K 2 = Q1
,

Step 6: Counter Implementation


S U7
1
Key = Space U6
AND2

OR2

U8 U1 U2 U3
XNOR2 SET U4 SET SET
J Q J Q J Q

CLK CLK CLK


OR2
K ~Q K ~Q K ~Q
RESET U9 RESET RESET

JK_FF 0 JK_FF JK_FF


U10 Key = Space

40 Hz

Example 5
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Design a synchronous BCD counter following count sequence with self-correcting capability and the
don’t care counts occur in the sequence determined by the state diagram shown below.

Example 6
Design a synchronous counter with the following count sequence with self-correcting capability.

Example 7
Design a synchronous counter with the following count sequence with self-starting capability

Example 8

Design a synchronous counter with the following state diagram

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3 bit synchronous counters using JK flip-flop

U8

AND2 U4
1
U1 U6 U2 U5
Key = Space
SET SET SET
J Q J Q J Q
CLK CLK CLK
DCD_HEX
K ~Q K ~Q K ~Q
RESET RESET RESET

JK_FF JK_FF JK_FF

U3

40 Hz

2 bit synchronous UP/DOWN Counter

4 bit Synchronous Counter

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Counter ICs
74LS93 is an example of a specific integrated circuit asynchronous counter. The logic diagram for this 4 bit
asynchronous counter is shown below. As we can see from the figure below, the IC consists of a 3 – bit counter
and a single flip-flop. This arrangement is used for flexibility. It can be used as a divide by 2 circuit if the single
flip-flop is used. Or it can be used as a modulo-8 counter if the three bit counter portion is used.

The following figure shows how the 74LS93 4 bit counter can be configured as a modulo – 16 and decade
counters

Example 1: Show how the 74LS93 counter IC can be wired as a modulo 12 and modulo 5 counter.

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Example 2: show how the 74LS93 asynchronous IC can be used as a modulo 13 and modulo 14 counter

Exercise: Show how the 74LS93 asynchronous IC can be used as modulo 7 and modulo 9 counter.

Cascading Counters

Counters can be connected in cascade to achieve higher modulus operation. In essence, cascading means that
the last stage output of one counter drives the input of the next counter.Most counter chips are 4-bit counters,
with a modulus of 16 or less. To get larger moduli, you can cascade two or more counter chips together. When
you cascade counters, their moduli multiply, not add. For example: If you cascade a MOD-10 counter with a
MOD-16 counter, you get a MOD-160 counter. The connections for cascading counters differ depending on
whether the counters are asynchronous or synchronous.

For synchronous counter, cascading can be achieved if the terminal count(TC) of the previous counter is
connected to the count enable input (CTEN). The figure below shows the cascade connection of two decade
synchronous counters.

Cascaded counters are often used to divide a high frequency clock signal to obtain to obtain highly accurate
pulse frequencies. The following modulo 1000 cascaded counter configuration can divide the 1MHz frequency
to 100KHz, 10KHz and 1KHz at the respective outputs as shown in the figure below.

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