IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 49, NO.

6, JUNE 2002 379

Palmo: Pulse-Based Signal Processing for

Programmable Analog VLSI
Konstantinos Papathanasiou, Member, IEEE, Thomas Brandtner, Student Member, IEEE, and Alister Hamilton

Abstract—This paper presents novel signaling and circuit tech-
niques for the implementation of programmable analog and mixed
signal very large scale integration (VLSI). The signaling technique
uses pulsewidth modulated digital signals to convey analog signal
information between programmable analog cells. A circuit for a
generic programmable analog cell is introduced and is analyzed for
harmonic distortion performance. The equivalence of the cell to a
switched-capacitor (SC) Miller integrator is proven. Voltage- and
current-mode (CM) implementations of the generic programmable
analog cell are introduced; an elegant-fast current controlled com-
parator is presented, and results from working analog VLSI im-
plementations provided.
Index Terms—Field programmable analog array (FPAA), mixed
signal very large scale integration (VLSI), palmo, programmable
analog VLSI, pulse-based signal processing.
I. INTRODUCTION
working VLSI implementations of these circuits are presented
demonstrating the validity of the technique.
II. PRINCIPLES OF OPERATION
A. Signaling Mechanism
The programmable analog signal processing technique
we have developed uses time rather than voltage or current,
to encode analog signal information to be carried between
programmable analog cells. It makes use of a noise robust
digital signal to encode analog information by modulating the
width of a digital pulse or pulses. This sampled data approach
produces a pulse to encode the analog information at every
sample epoch. Variants of it have been seen elsewhere [5]–[7].
Since analog signals may have either positive or negative
polarities, we have extended this basic concept to include a

T HE field programmable analog array (FPAA) has made a

recent appearance in the market place in a variety of forms
[1]–[4]. This variety is due to the wide range of circuit specifi-
sign clock whose frequency is matched to the sample clock. A
pulse occurring when the sign clock is high encodes a positive
analog quantity, while a pulse occurring when the sign clock
cations and circuit realization techniques that face the analog
is low encodes a negative one.
circuit designer. The analog domain is much more diverse than
Fig. 1 illustrates our pulse-based signaling methodology. Two
the digital one and implementing generic field programmable
pulsewidth modulated (PWM) signal strategies are shown, the
analog parts is a considerable challenge.
choice of which depends on circuit implementation issues. The
In this paper, an entirely new range of signaling techniques
signal PWM (a) represents the sampled analog quantity as de-
and programmable circuits that are ideally suited to a pro-
scribed earlier. In signal PWM (b), the sampled analog quan-
grammable analog and mixed signal very large scale integration
tity is represented by the sum of the pulsewidths in any period
(VLSI) environment are presented in detail.
of the sign clock. Either signaling mechanism may be used to
A pulse-based signaling technique used for communicating
connect programmable analog cells together. The signal inputs
analog signals around the programmable device is presented.
to these programmable analog cells are digital PWM signals,
A generic programmable analog cell is described and the
as are signal outputs from these cells. Thus, standard digital
equivalence of a Miller integrator implemented using this
techniques may be used to route PWM signals between pro-
cell to the switched-capacitor (SC) implementation is demon-
grammable analog cells in a completely flexible way. Although
strated. The sources of total harmonic distortion (THD) within
we use a digital signaling method, the analog signal information
the programmable analog cell are presented and analyzed.
conveyed by the PWM signal is not quantized in a digital sense,
Voltage- and current-mode (CM) circuit implementations of the
but continuously variable with the width of the PWM pulse or
programmable analog cell are introduced. Finally, results from
pulses.
This use of pulses to encode analog signal quantities has led to
Manuscript received November 21, 2000; revised June 11, 2002. This work our name for this technique—Palmo, from the Hellenic
was supported by the U.K. Engineering and Physical Sciences Research Council
(EPSRC) under Grant GR/L36031. This paper was recommended by Associate which means pulse beat, pulse palpitation, or series of pulses.
Editor R. Geiger.
K. Papathanasiou was with the Department of Electronics and Electrical En-
gineering, University of Edinburgh, Edinburgh EH9 3JL, U.K. He is now with
B. Palmo Cell
RF Magic, San Diego, CA 92121 USA. The programmable analog cell we have chosen to implement
T. Brandtner was with the Department of Electronics and Electrical Engi-
neering, University of Edinburgh, Edinburgh EH9 3JL, U.K. He is now with the is an analog integrator. Integrators with controllable gain are
RF Group, Infineon Technologies Development Center, A-8010 Graz, Austria. versatile building blocks which may be used directly to im-
A. Hamilton is with the Department of Electronics and Electrical En- plement filters, but which may also implement analog mem-
gineering, University of Edinburgh, Edinburgh EH9 3JL, U.K. (e-mail:
Alister.Hamilton@ee.ed.ac.uk). ories (by integrating a single input) or scaling functions and,
Digital Object Identifier 10.1109/TCSII.2002.802341. therefore, may be used in different sampled data applications,
1057-7130/02$17.00 © 2002 IEEE
380 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 49, NO. 6, JUNE 2002

Fig. 1. Pulsed-based signal representations, PWM (a) and PWM (b), of a sampled analog signal. The magnitude of the analog signal is encoded in the width of
the pulse or pulses at each sample epoch. The sign of the analog signal is encoded in the relationship between the pulses and the state of the sign clock. Pulses
occurring while the sign clock is high represent positive analog signals, while those occurring while the sign clock is low represent negative analog signals.

(a) (b) (c)

Fig. 2. Typical Palmo programmable analog integrator cell. (a) Palmo unipolar signal integrator. (b) Palmo bipolar signal integrator. (c) Complete Palmo cell.

analog-to-digital (A/D) converters or as a delay ( ) in digital been added to the circuit of Fig. 2 to set or to a reference
signal processing algorithms. voltage ( ).
The Palmo cells make use of the digital PWM signals de- As we shall see, control over the signal and ramp circuits
scribed earlier and analog functionality to implement such an gives accurate programmable control over the overall gain ( )
integrator (Fig. 2). The input pulse [Fig. 2(a)] controls the of the Palmo integrator cell.
switch . When this switch is closed the capacitor ( ) is
charged by constant current ( ) to a voltage C. Miller Integrator
, where denotes the duration of the input pulse In this section, we demonstrate the equivalence of a Palmo
representing the magnitude of the analog signal. A complemen- integrator implementation of a Miller integrator to the SC active
tary structure is added to discharge the capacitor [Fig. 2(b)] if the RC filter implementation. In doing so, we also demonstrate how
input signal is negative. Digital circuitry may be used to route the gain of the Palmo cell may be programmed.
the input pulses to either or control line depending upon In the SC active RC filter implementation of the Miller in-
the sign of the input signal. tegrator a SC replaces the resistor, R [8]–[11] and the transfer
The accumulated charge on , representing the result of the function is
integration process, may be converted back to a pulsed PWM
signal to produce the output signal from the Palmo cell. To
(1)
achieve this an identical circuit [Fig. 2(c)] is used to generate
a ramp signal (Fig. 3). The , signals which control the
ramp generating circuit are derived from the digital signals that In a differential Miller integrator, the effect of a signal on
generate the sign clock. A comparator detects when the two volt- the non inverting input is apparent at the output after a delay
ages ( and ) meet and the exclusive OR of the comparator of one clock period; while a signal on the inverting input is ap-
output and the sign clock generates a signed PWM output from parent after a one-half clock period delay. The charge accumu-
the Palmo cell. A typical waveform diagram showing the sig- lated on the integrating capacitor ( ) of a Palmo Miller inte-
nals within the Palmo cell for the PWM (b) signals of Fig. 1 is grator [Fig. 2(c)] during one cycle is
shown in Fig. 3 for both positive and negative accumulated sig-
nals on the integrating node, . Two reset switches have also (2)
PAPATHANASIOU et al.: PALMO: PULSE-BASED SIGNAL PROCESSING FOR ANALOG VLSI
(a)
Fig. 3. Signals within the Palmo cell used to produce PWM (b) output signals. (a) Positive value on signal integrator output. (b) Negative value on signal integrator
output.
(a)
Fig. 4. Harmonic distortion due to comparator delays. (a) Ideal output signal,
(c) Resultant distorted output signal.
The voltage ( ) on the integrating capacitor at the end of an
integrating cycle is given by the following equations:
where and are the widths of the pulses on the
inverting and noninverting inputs to the integrator. The voltage
( ) accumulated on the integrating capacitor [Fig. 2(c)] is
compared with the ramp ( ) in order to regenerate the pulsed
output. When the voltage becomes equal to the voltage , Fig. 2(c) [24], [25].
the comparator output will change state, defining the end of the
pulsewidth output. At this time the voltage on the ramp capacitor
is
and . Thus
(3)
It is noticeable from (3) and (1) that both the SC and the Palmo
Miller integrators have identical transfer functions where the
corresponding gains ( ) are
(4)
Due to this similarity, existing SC synthesis techniques and tools
may be applied to the Palmo realization [12], [13]. In a Palmo
implementation, scaling ( ) is a product of the ratio of two
capacitances and the ratio of two currents, resulting in greater
dynamic range of filter coefficients, compared to conventional
381
(b)
(b) (c)
1T cos(!t). (b) Error signal introduced by comparator delays, 1T f (t).
SC (or switched current) techniques [14]–[16]. Since the ratio
of capacitors in (4) can be modified by switching between the
elements of a capacitor array and the ratio of the currents can
be electrically modified with sufficient accuracy [17]–[20]; the
gain of a Palmo cell is fully digitally programmable and in-
sensitive to absolute values [21]–[23].
III. HARMONIC DISTORTION
The main factors that contribute to the THD in Palmo circuits
are the nonidealities of the comparator and the differences be-
tween the charging and discharging currents in the circuits of
Offsets introduced by the comparator of a typical Palmo cell
can be easily cancelled by post processing. However, propaga-
tion delays result in harmonic distortion when the positive and
negative switching response times of the comparator output are
unequal. Such comparator delays are due to the parasitic capac-
itances which need to be charged (or discharged) when the com-
parator output changes state. The effect of these inevitable de-
lays is to make the output pulsewidths longer than they should
be adding to the PWM output. Therefore, the ideal cosine
output [Fig. 4(a)] with a magnitude will be distorted, be-
cause of the signal [Fig. 4(b)], resulting in the signal
shown in Fig. 4(c), which is given by
(5)
where , when
or otherwise.1 The Fourier transform of the output
signal given by (5) [Fig. 4(c)] is equal to the sum of the Fourier
series of the two signals shown in Fig. 4(a) and (b) namely
1Our systems are sampled-data ones, therefore, the output is discrete, how-
ever, for simplicity, we will consider them continuous during this THD analysis.
382 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 49, NO. 6, JUNE 2002

(a) (b) (c)

Fig. 5. Harmonic distortion due to current differences.

and , because the signal is an even func- Therefore, if

tion of the resultant Fourier series is a Fourier cosine series,
thus
(8)

where , are the currents driven by the transistors ,

. For small values of and the THD of the Palmo
The overall harmonic distortion, due to the propagation delay circuit (THD) can be approximated by adding (6) and (8), thus
of the comparator ( ), for , is given by the
equation [25] (9)

1) Discussion: The comparator delays are independent

(6) (to a first approximation) to the frequency of operation, how-
ever, its size increases proportionally to the output ( ) at high
sampling frequencies. Current matching on the other hand de-
where is the magnitude of the ideal signed PWM cosine pends heavily to the size of the currents. As a result distortion
signal and is the size of the comparator delay. introduced by the comparator ( ) is expected to dominate
As shown in (3) capacitor or current mismatches generate at high frequencies, while the use of small and, therefore, less
gain mismatches or offsets. These mismatches do not generate well-matched integrating currents will introduce most of the dis-
distortion. Differences between the charging and discharging tortion ( ) at low frequencies.
currents ( or ) used in the Palmo cell of Fig. 2(c) will gen- Another source of nonlinearities in pulse-based signal
erate harmonic distortion. A typical charge/discharge circuit is processing circuits is clock jitter; this can be viewed as a
shown in Fig. 5(a), where and represent charging and dis- quantization error signal added to the input of the analog to
charging currents of different magnitudes. Assuming the voltage pulse converter and would directly add to the noise floor of the
to PWM converter of Fig. 5(b) were the ramp voltage is com- Palmo signal. Such a noise effect may be shaped and pushed
pared to the input voltage ; if is generated to higher frequencies by the means of a converter, or can
by two different current sources then were be suppressed to a lower level that the analog information of
is the mismatched positive or negative sampling current interest. Recently, the development of spread spectrum commu-
and is the resultant positive or negative output pulse, respec- nications, which impose strict jitter requirements, encouraged
tively. The discrete output will be treated as a continuous the advancement of low-jitter clock generation [26]–[28] which
function for the purpose of this analysis [Fig. 5(c)] and is has yielded on chip frequency synthesizers with an effective
given by the equation peak to peak jitter of 240 ps at 10 MHz (or SNR of 53 dB if
used in a palmo system) and 81 ps at 100 MHz (or SNR of 42
(7) dB). Other commercially available surface mountable devices
otherwise [29] produce 8.5 ps jitter at 10 MHz (or SNR of 81 dB) and
discrete component-based VCOs for CDMA phones would
where and are unequal peak magnitudes of the output
produce a 5 ps jitter at 10 MHz (or SNR of 85 dB) and 1.68 ps
signal caused by the mismatch in and . This generates
jitter at 100 MHz (or SNR of 75 dB).
a second THD component given by the Fourier transformation
of (7). The Fourier coefficients are
IV. IMPLEMENTATIONS
The principles presented in the previous sections were used
to design several test chips.
and A. Voltage Domain Circuits
A voltage domain Palmo FPAA contained eight Palmo cells
each with a dedicated DAC and programmable capacitor array
PAPATHANASIOU et al.: PALMO: PULSE-BASED SIGNAL PROCESSING FOR ANALOG VLSI
Fig. 6. Voltage domain palmo cell with dedicated DAC and programmable capacitor array.
(Fig. 6) to set the cell gain. The integrating and ramp gener-
ating current sources of Fig. 2(c) are combined into a single cir-
cuit that is multiplexed in time to perform either integration or
ramp generation depending on the state of the digital control
line . The gain is set by the ratio of currents mul-
tiplexed into the current DAC ( and ) and by the setting
of individual elements of a 3 by 3 capacitor array assigned to
or depending upon the state of the digital control word
. The signal defines whether current will be
dumped or removed from the appropriate capacitor. The input
signal Pulse is either the PWM input signal, or the signal that
controls the ramp waveform. The gain of the analog Palmo cell
has 9 b of resolution. Since this 9 b resolution is a product of a
6 b current ratio and a 3 b capacitor ratio, the chip area occu-
pied by the cell is much less than the equivalent resolution in
a SC implementation where 512 elementary capacitors would
be required. Analog to PWM conversion was facilitated by con-
necting the node on one of the Palmo cells to an analog
input pad to the chip. PWM to analog conversion was imple-
mented by buffering the node through an on chip unity
gain buffer so the signal could be read off chip. All interconnec-
tion and digital control was implemented using a separate field
programmable gate array (FPGA).
Characterization of similar fabricated devices (Fig. 6) [12],
[13], [30] highlighted several possible improvements: the use
of wide swing cascoded current mirrors, accurate thermometer
coded dynamic current DACs and faster continuous time voltage
comparator implementations. This experience led to the realiza-
tion that the use of CM techniques would offer significant ad-
vantages in the implementation of Palmo cells.
383
B. CM Palmo Cells
CM circuits offer a large dynamic range that is not limited by
power supply voltage so that it is possible to use a dual-slope
current ramp waveform and the signaling technique PWM(b)
of Fig. 1. Due to the high switching speeds of continuous time
current controlled comparator circuits the sampling frequency
of CM Palmo circuits is more than an order of magnitude greater
than the voltage domain implementations [31].
The schematic diagram of the CM Palmo cell is shown in
Fig. 7. It consists of three parts: a digital logic block, an inte-
grator, and a current comparator. The logic converts the input
pulses and the sign signal into two differential input currents
that form the input to the integrator. The pulsed output is gener-
ated by a current controlled comparator (CCC) which compares
the integrator output current to a current ramp produced by a
second identical integrator.
Here, two different integrator circuits that perform the dif-
ferential integration function shown in Fig. 7 are introduced; a
log-domain integrator and a square-root-domain integrator with
its associated geometric mean circuit. The current controlled
comparator circuit of Fig. 7 is also introduced.
1) Log-Domain Integrator: The principal circuit of the log-
domain integrator used in our Palmo cell is shown in Fig. 8. It
is based on [32]–[35], but has improved linearity over a bigger
current range, due to the use of cascode current mirrors and sta-
bilising transistors, M13 and M14 [30], [31]. The integrator is
fully differential; the input value is the difference of the two
currents and . First the input currents are compressed into
log-domain by Q1 (Q8); Q2 and C1 (Q7, C2) perform integra-
tion in the log-domain. The integrated value is scaled by Q3
384 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 49, NO. 6, JUNE 2002

Fig. 7. CM Palmo cell and typical waveform diagram.

Fig. 8. Log-domain integrator.

(Q6), the scaling factor depends on the current . Finally, Q4 current of , and is the current gain of the bipolar transistors.
(Q5) expands the compressed signal. The output is represented The output currents and are given by the equations
by the difference of the currents and . Additional cur-
rent mirrors are necessary for producing the output current (not i
i
shown).
The following translinear equations [36] for the integrator cir- i
i
i

cuit of Fig. 8 may be derived from the relationship

i
of the bipolar transistor i

i i (12)
i

(10)
where is the thermal voltage (26 mV at 300 K), is the
biasing voltage (Fig. 8). Subtracting the two (10), substituting
where is the collector current of transistor . The currents
from (11) and i from (12), while assuming
(and similarly ) are given by the fol-
and results in the final equation:
lowing equations:

(11)

where is the mirroring ratio of the current mirror M5-8, is the

mirroring ratio of the current mirror M9-12, is the charging
i
(13)
PAPATHANASIOU et al.: PALMO: PULSE-BASED SIGNAL PROCESSING FOR ANALOG VLSI
Fig. 9. Square-root-domain integrator with transistor W/L ratios.
where are due to the early voltage effect,
is the collector-base voltage of transistor and is
the early voltage.
The first term on the right side of (13) shows that the differ-
ence of the output currents ( ) is proportional to the
integral of . The integration constant is . It
can be controlled by changing the current or the capacitor C.
However, it is a function of temperature. The overall gain of the
Palmo cell (4) is [12], [13]
(14)
and, therefore, temperature dependency has been removed from
the gain of the cell.
In practice, the scaling current should be proportional to
temperature. The accuracy of temperature tracking is not critical
to the accuracy of the integrator gain, but it is beneficial for
achieving the maximum dynamic range; because temperature
variations will alter the currents and , thus, changing
the dynamic range, while the current ratio will remain the same
over temperature variations.
The second term occurs because of the base currents of Q3
and Q5 which introduce a leakage current on the integrating
nodes. This is a particular problem for sampled data systems
because the integrated value should remain constant between
samples. Since the collector current of these transistors is always
equal to this term can be easily cancelled by introducing two
additional current sources of . These current sources
are derived from the base current of a single bipolar transistor
with a collector current of .
The reason for the third term is the difference of the mirroring
ratios of the two current mirrors M5-8 and M9-12. The two cur-
rents and which are mirrored are not the same, there-
fore, the mirroring ratio should be constant with respect to the
mirrored current. To maximize the dynamic range of the cir-
cuit at the expense of operating frequency, operating voltage and
power, a cascode current mirror is used.
The last term is due to the early effect. The collector voltages
of Q4 and Q5 vary due to output current changes. Transistors
M13 and M14 stabilize the collector voltages of Q4 and Q5 to
minimize this term.
385
The integrator is reset by connecting nodes 1 and 2 together,
or by increasing the base compensating current, .
2) Differential Square-Root Translinear Circuit: The inte-
grator is shown in Fig. 9. Transistor is a current source
controlled by . This current source generates variable
magnitude current pulses , depending upon the sam-
pling rate (the shorter the sampling time, the larger the current).
This current is integrated on capacitor . The transistor
introduce some common mode feedback [37], which,
along with , defines the circuit operating point. The transis-
tors are used to form wide swing cascoded current sources.
A square-law expanded current is derived from
the integrated voltage on the gate of . This current
is compressed and scaled by the use of complementary
metal–oxide–semiconductor (CMOS) geometric mean circuit
[38] ( ) (Fig. 10), to produce an overall linear V–I
relationship. The transfer function of the differential integrator
of Fig. 9 (assuming well-matched transistors, capacitors, and
currents) is given by
where is the differential output current ( ),
is the differential input current ( ), the scaling cur-
rent, is the transconductance parameter of , is the in-
tegrating capacitance.
The linearity of the circuit depends on the accuracy of the V–I
characteristic of saturated MOS transistors and the quality of
the geometric mean circuit. The frequency of operation depends
on the delays posed by the feedback loop and can be designed
to be arbitrarily small, with a tradeoff in power consumption.
Delays in the geometric mean circuit influence the response of
the circuit, however, since these circuits are not in the feedback
loop, they do not degrade the sampling frequency.
The overall gain of the Palmo cell is [30], [31]
(15)
The gain is dependent on capacitor and current ratios, which can
be accurately realized in silicon. Furthermore, since the gain
386 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 49, NO. 6, JUNE 2002

(a) (b)
Fig. 10. MOS geometric mean circuit.

(a) (b)
Fig. 11. Current comparator.

is dependent on the product of two different values, high
Q factors can be achieved with reduced area requirements (
80 dB for 250 m 250 m on a 0.8- m process) compared to
other conventional sampled-data techniques.
The signal to noise ratio (SNR) of the integrator is over 65 dB
for a wide range of sampling frequencies (10 kHz to 20 MHz)
and a 5 V supply voltage. This is due to the fact that the magni-
tude of the input currents , varies with the frequency of
operation. A power supply voltage of 3 V gives a dynamic range
of 60 dB. The integrator may be reset by connecting integrating
nodes one and two together temporarily, with virtually no clock
feed-through effects observable at the output.
C. CCC
This circuit is mainly responsible for the high sampling fre-
quency capability [31] of the Palmo cell because it is faster than
the voltage mode comparators used in former Palmo implemen-
tations [39].
The CCC used was based upon [40] [Fig. 11(a)]. The input
currents are amplified by transistors and , while positive
feedback from and further increase transition currents.
However, during the transient period when the current changes
sign (deadband) the buffer cannot supply the input current, re-
sulting in a high impedance node and degrading the response
time. The size of the deadband is determined by and is, there-
fore, process dependent.
The comparator used is an improvement of the above circuit
proposed in [41] [Fig. 11(b)]. It was modified in order to accom-
modate the lack of p-wells in the fabrication process used. As the
voltages at nodes (1) and (2) [Fig. 11(b)] are increased toward
, the deadband in the transfer characteristic is reduced by the
voltage drop on , which is controlled by and . This
results in a smaller voltage swing and, thus, a faster response
(17 ns for a 50 nA swing). The smaller and become,
the smaller the deadband of the source follower gets, hence the
current comparator gets faster. On the other hand the power con-
sumption increases (2 mW in our circuit) due to the bigger cur-
rents in the CMOS inverter stages. In that way the operating
frequency and the dynamic range of the Palmo circuit is signif-
icantly improved.
V. RESULTS FROM SILICON
A. Harmonic Distortion
Fig. 12(a) shows an estimation of , , and THD (12)
calculated using (6) and (8) and measured parameters from a
voltage domain test chip. Fig. 12(b) shows the harmonic distor-
tion of the differential circuit measured from silicon. The
PAPATHANASIOU et al.: PALMO: PULSE-BASED SIGNAL PROCESSING FOR ANALOG VLSI
Fig. 12. THD for different sampling frequencies. (a) Voltage domain circuits. (b)
Fig. 13. Programmable voltage domain circuits: first-, second-, and third-
order Butterworth filters at cutoff frequencies of 1 and 2 kHz.
innovations introduced by the design are evident. Harmonic dis-
tortion is reduced because of the improved matching of the dif-
ferential circuit and the advanced comparator design. Those re-
sults compare favorably with a figure of 0.4% [42] quoted for a
mature programmable SC FPAA cell.
Distortion introduced by the comparator (Fig. 12) is dominant
at high frequencies where the comparator delays become com-
parable to the sampling rate. Distortion due to current matching
dominates at low frequencies due to small and less well-matched
integrating currents.
B. Voltage Domain Circuits
Measured results (Fig. 13) from the voltage domain Palmo
FPAA circuits (Fig. 6) demonstrate the programmability of the
Palmo circuits. The order and the cutoff frequency of the re-
sponse [13], [39], may be altered by the digital configuration
of the control signals. Other implementations of mixed-mode
finite-impulse response filters and more complex system real-
izations (such as a modulator) highlighted the advantages
of the Palmo approach to programmable analog hardware [30].
Voltage domain circuits offer limited SNR (40–50 dB) and sam-
pling frequency (500 kHz). This is due to mirroring inaccura-
387
px circuits.
Fig. 14. Third-order Butterworth filter responses in different sampling fre-
quencies (100 kHz, 1 MHz, 8 MHz).
cies, limited supply headroom (12 V) and slow voltage com-
parators.
C. CM Circuits
Both a CM log-domain and a -domain circuit were fabri-
cated. The latter offered higher sampling frequencies and sim-
ilar dynamic range for a larger power supply voltage (5 V).
The -domain test chip was used to generate the results pre-
sented in Fig. 14. A third-order low-pass Butterworth filter was
implemented utilising a single test chip to perform the analog
integrator and a digital FPGA to drive the control lines. The bi-
asing currents were provided externally from tuneable current
sources. The biasing current sizes were a function of the fre-
quency of operation (the faster the sampling frequency the larger
the currents). The resultant output pulse was recorded by a dig-
ital signal analyzer with a sampling frequency of 1.5 GHz. It
is clear (Fig. 14) that the CM circuits outperform voltage do-
main approaches in both SNR and the maximum sampling fre-
quency. The circuit behaves best at a sampling frequency of
about 1 MHz, giving over 60 dB. At 100 kHz the response ap-
proaches 57 dB; because of matching degradation due to the use
of smaller biasing currents which lowers the effective voltage of
388 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 49, NO. 6, JUNE 2002
the current sources and, thus, mismatches become more sig-
nificant. At 8 MHz the attenuation in the stop band increases to
40 dB. This is due to comparator and pin-to-pin FPGA delays
and also due to the fact that the resolution of the recording circuit
( Gs MHz dB) is comparable to the signal
itself (40 dB) and to the proximity of the Nyquist frequency to
the cutoff frequency, which makes the approximation
less accurate.
VI. CONCLUSION
The simple step of using a PWM signal to encode analog
signal information has led to the development of an entirely
new class of programmable analog circuit. We call this Palmo.
The analysis and results from fabricated VLSI devices presented
here demonstrate the validity and performance of the technique.
Palmo is ideally suited to FPAA implementation due to the com-
pactness of the programmable structure and the ease with which
signals may be routed between cells. The Miller integrator pre-
sented here demonstrates an equivalence to the SC counterpart.
The sources of harmonic distortion are understood and may be
constrained by appropriate design. The Palmo technique may
be extended to give programmable mixed signal and continuous
time analog circuit solutions [4].
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PAPATHANASIOU et al.: PALMO: PULSE-BASED SIGNAL PROCESSING FOR ANALOG VLSI 389

Konstantinos Papathanasiou (M’00) received the Alister Hamilton is a Lecturer in the Department of
M.S.degree in electrical engineering from the Univer- Electronics and Electrical Engineering, University
sity of Patras, Patras, Greece, in 1994 and the Ph.D. of Edinburgh, Edinburgh, U.K. His research interests
degree in analog electronics from the University of have spanned neural network implementations
Edinburgh, Edinburgh, U.K., in 1998. in analog VLSI, neuromorphic engineering, pro-
From 1997 to 1998, he was a Research Associate grammable analog VLSI, and on-focal plane analog
at the University of Edinburgh. In 1999, he became processing of image data.
a Research Professor in the Department of Infor-
mation Technology, Danish Technical University,
Lyngby, Denmark. From 2000 to 2001, he worked
for Qualcomm CDMA Technologies, San Diego,
CA. Currently, he is with RF-Magic, San Diego, CA. His research interests
include analog and RF integrated systems, neural network implementations,
implantable low-power devices, field programmable analog and RF arrays,
analog uses of floating gates, device modeling and mismatch.
Dr. Papathanasiou is a Member of the Hellenic Chamber of Engineers.

Thomas Brandtner (S’00) was born in Salzburg,

Austria, in 1974. He received the Dipl.-Ing. degree
from the Graz University of Technology, Graz,
Austria, in 1998, where he is currently and working
toward the Ph.D. degree. He did his Diploma thesis
on log-domain Palmo cells for field programmable
analog arrays at the University of Edinburgh,
Edinburgh, U.K., in 1998.
Currently, he is working in the RF Group, Infineon
Technologies Development Center, Graz, focusing
on modeling and simulation of parasitic effects in
mixed-signal integrated circuits