CD4514BM/CD4514BC, CD4515BM/CD4515BC 4-Bit Latched/4-to-16 Line Decoders

February 1988

CD4514BM/CD4514BC, CD4515BM/CD4515BC
4-Bit Latched/4-to-16 Line Decoders
General Description Features
The CD4514B and CD4515B are 4-to-16 line decoders with Y Wide supply voltage range 3.0V to 15V
latched inputs implemented with complementary MOS Y High noise immunity 0.45 VDD (typ.)
(CMOS) circuits constructed with N- and P-channel en- Y Low power TTL fan out of 2
hancement mode transistors. These circuits are primarily compatibility driving 74L
used in decoding applications where low power dissipation Y Low quiescent power dissipation 0.025 mW/package
and/or high noise immunity is required. @ 5.0 V
DC
The CD4514B (output active high option) presents a logical Y Single supply operation
‘‘1’’ at the selected output, whereas the CD4515B presents Y Input impedance e 1012X typically
a logical ‘‘0’’ at the selected output. The input latches are Y Plug-in replacement for MC14514, MC14515
R –S type flip-flops, which hold the last input data presented
prior to the strobe transition from ‘‘1’’ to ‘‘0’’. This input data
is decoded and the corresponding output is activated. An
output inhibit line is also available.

Logic and Connection Diagrams

TL/F/5994 – 1
Dual-In-Line Package

Order Number CD4514B or CD4515B

TL/F/5994 – 2
Top View
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.

C1995 National Semiconductor Corporation TL/F/5994 RRD-B30M105/Printed in U. S. A.

 Absolute Maximum Ratings (Notes 1 and 2) Recommended Operating
If Military/Aerospace specified devices are required, Conditions (Note 2)
please contact the National Semiconductor Sales
DC Supply Voltage (VDD) 3V to 15V
Office/Distributors for availability and specifications.
Input Voltage (VIN) 0V to VDD
DC Supply Voltage (VDD) b 0.5V to a 18V
Operating Temperature Range (TA)
Input Voltage (VIN) b 0.5V to VDD a 0.5V
CD4514BM, CD4515BM b 55§ C to a 125§ C
Storage Temperature Range (TS) b 65§ C to a 150§ C CD4514BC, CD4515BC b 40§ C to a 85§ C
Power Dissipation (PD)
Dual-In-Line 700 mW
Small Outline 500 mW
Lead Temperature (TL)
(Soldering, 10 seconds) 260§ C

DC Electrical Characteristics CD4514BM, CD4515BM (Note 2)

b 55§ C a 25§ C a 125§ C
Symbol Parameter Conditions Units
Min Max Min Typ Max Min Max
IDD Quiescent Device VDD e 5V, VIN e VDD or VSS 5 0.005 5 150 mA
Current VDD e 10V, VIN e VDD or VSS 10 0.010 10 300 mA
VDD e 15V, VIN e VDD or VSS 20 0.015 20 600 mA
VOL Low Level VIH e VDD, lIOl k 1 mA
Output Voltage VDD e 5V, VIL e 0V 0.05 0 0.05 0.05 V
VDD e 10V 0.05 0 0.05 0.05 V
VDD e 15V 0.05 0 0.05 0.05 V
VOH High Level VIH e VDD, lIOl k 1 mA
Output Voltage VDD e 5V, VIL e 0V 4.95 4.95 5 4.95 V
VDD e 10V 9.95 9.95 10 9.95 V
VDD e 15V 14.95 14.95 15 14.95 V
VIL Low Level VO e 0.5V or 4.5V
Input Voltage VDD e 5V, lIOl k 1 mA 1.5 2.25 1.5 1.5 V
VDD e 10V, VO e 1.0V or 9.0V 3.0 4.50 3.0 3.0 V
VDD e 15V, VO e 1.5V or 13.5V 4.0 6.75 4.0 4.0 V
VIH High Level VO e 0.5V or 4.5V
Input Voltage VDD e 5V, lIOl k 1 mA 3.5 3.5 2.75 3.5 V
VDD e 10V, VO e 1.0V or 9.0V 7.0 7.0 5.50 7.0 V
VDD e 15V, VO e 1.5V or 13.5V 11.0 11.0 8.25 11.0 V
IOL Low Level Output VDD e 5V, VO e 0.4V 0.64 0.51 0.88 0.36 mA
Current (Note 3) VDD e 10V, VO e 0.5V 1.6 1.3 2.25 0.90 mA
VDD e 15V, VO e 1.5V 4.2 3.4 8.80 2.40 mA
IOH High Level Output VDD e 5V, VO e 4.6V b 0.64 b 0.51 b 0.88 b 0.36 mA
Current (Note 3) VDD e 10V, VO e 9.5V b 1.6 b 1.3 b 2.25 b 0.90 mA
VDD e 15V, VO e 13.5V b 4.2 b 3.4 b 8.80 b 2.40 mA
IIN Input Current VDD e 15V, VIN e 0V b 0.1 b 10 b 5 b 0.1 b 1.0 mA
VDD e 15V, VIN e 15V 0.1 10b5 0.1 1.0 mA

DC Electrical Characteristics CD4514BC, CD4515BC (Note 2)

b 40§ C a 25§ C a 85§ C
Symbol Parameter Conditions Units
Min Max Min Typ Max Min Max
IDD Quiescent Device VDD e 5V, VIN e VDD or VSS 20 0.005 20 150 mA
Current VDD e 10V, VIN e VDD or VSS 40 0.010 40 300 mA
VDD e 15V, VIN e VDD or VSS 80 0.015 80 600 mA
VOL Low Level VIL e 0V, VIH e VDD,
Output Voltage lIOl k 1 mA
VDD e 5V 0.05 0 0.05 0.05 V
VDD e 10V 0.05 0 0.05 0.05 V
VDD e 15V 0.05 0 0.05 0.05 V
VOH High Level VIL e 0V, VIH e VDD,
Output Voltage lIOl k 1 mA
VDD e 5V 4.95 4.95 5.0 4.95 V
VDD e 10V 9.95 9.95 10.0 9.95 V
VDD e 15V 14.95 14.95 15.0 14.95 V

2
 DC Electrical Characteristics CD4514BC, CD4515BC (Note 2) (Continued)
b 40§ C a 25§ C a 85§ C
Symbol Parameter Conditions Units
Min Max Min Typ Max Min Max
VIL Low Level lIOl k 1 mA
Input Voltage VDD e 5V, VO e 0.5V or 4.5V 1.5 2.25 1.5 1.5 V
VDD e 10V, VO e 1.0V or 9.0V 3.0 4.50 3.0 3.0 V
VDD e 15V, VO e 1.5V or 13.5V 4.0 6.75 4.0 4.0 V
VIH High Level lIOl k 1 mA
Input Voltage VDD e 5V, VO e 0.5V or 4.5V 3.5 3.5 2.75 3.5 V
VDD e 10V, VO e 1.0V or 9.0V 7.0 7.0 5.50 7.0 V
VDD e 15V, VO e 1.5V or 13.5V 11.0 11.0 8.25 11.0 V
IOL Low Level Output VDD e 5V, VO e 0.4V 0.52 0.44 0.88 0.36 mA
Current (Note 3) VDD e 10V, VO e 0.5V 1.3 1.1 2.25 0.90 mA
VDD e 15V, VO e 1.5V 3.6 3.0 8.8 2.4 mA
IOH High Level Output VDD e 5V, VO e 4.6V b 0.52 b 0.44 b 0.88 b 0.36 mA
Current (Note 3) VDD e 10V, VO e 9.5V b 1.3 b 1.1 b 2.25 b 0.90 mA
VDD e 15V, VO e 13.5V b 3.6 b 3.0 b 8.8 b 2.4 mA
IIN Input Current VDD e 15V, VIN e 0V b 0.3 b 10 b 5 b 0.3 b 1.0 mA
VDD e 15V, VIN e 15V 0.3 10b5 0.3 1.0 mA

AC Electrical Characteristics*
All types CL e 50 pF, TA e 25§ C, tr e tf e 20 ns unless otherwise specified
Symbol Parameter Conditions Min Typ Max Units
tTHL, tTLH Transition Times VDD e 5V 100 200 ns
VDD e 10V 50 100 ns
VDD e 15V 40 80 ns
tPLH, tPHL Propagation Delay Times VDD e 5V 550 1100 ns
VDD e 10V 225 450 ns
VDD e 15V 150 300 ns
tPLH, tPHL Inhibit Propagation VDD e 5V 400 800 ns
Delay Times VDD e 10V 150 300 ns
VDD e 15V 100 200 ns
tSU Setup Time VDD e 5V 125 250 ns
VDD e 10V 50 100 ns
VDD e 15V 38 75 ns
tWH Strobe Pulse Width VDD e 5V 175 350 ns
VDD e 10V 50 100 ns
VDD e 15V 38 75 ns
CPD Power Dissipation Capacitance Per Package (Note 5) 150 pF
CIN Input Capacitance Any Input (Note 4) 5 7.5 pF
*AC Parameters are guaranteed by DC correlated testing.
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits. The tables of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteris-
tics’’ provide conditions for actual device operation.
Note 2: VSS e 0V unless otherwise specified.
Note 3: IOH and IOL are tested one output at a time.
Note 4: Capacitance is guaranteed by periodic testing.
Note 5: CPD determines the no load AC power consumption of any CMOS device. For complete explanation, see 54C and 74C Family Characteristics application
note, AN-90.

3
Truth Table
Decode Truth Table (Strobe e 1)
Data Inputs Selected Output
Inhibit CD4514 e Logic ‘‘1’’
D C B A CD4515 e Logic ‘‘0’’

0 0 0 0 0 S0
0 0 0 0 1 S1
0 0 0 1 0 S2
0 0 0 1 1 S3
0 0 1 0 0 S4
0 0 1 0 1 S5
0 0 1 1 0 S6
0 0 1 1 1 S7
0 1 0 0 0 S8
0 1 0 0 1 S9
0 1 0 1 0 S10
0 1 0 1 1 S11
0 1 1 0 0 S12
0 1 1 0 1 S13
0 1 1 1 0 S14
0 1 1 1 1 S15
1 X X X X All Outputs e 0, CD4514
All Outputs e 1, CD4515
X e Don’t Care

AC Test Circuit and Switching Time Waveforms

TL/F/5994 – 4

TL/F/5994 – 3
FIGURE 1

4
Applications
Two CD4512 8-channel data selectors are used here with
the CD4514B 4-bit latch/decoder to effect a complex data
routing system. A total of 16 inputs from data registers are
selected and transferred via a TRI-STATEÉ data bus to a
data distributor for rearrangement and entry into 16 output
registers. In this way sequential data can be re-routed or
intermixed according to patterns determined by data select
and distribution inputs.
Data is placed into the routing scheme via the 8 inputs on
both CD4512 data selectors. One register is assigned to
each input. The signals on A0, A1 and A2 choose 1-of-8
inputs for transfer out to the TRI-STATE data bus. A fourth
signal, labelled Dis, disables one of the CD4512 selectors,
assuring transfer of data from only one register.
In addition to a choice of input registers, 1–16, the rate of
transfer of the sequential information can also be varied.
That is, if the CD4512 were addressed at a rate that is
5
8 times faster than the shift frequency of the input registers,
the most significant bit (MSB) from each register could be
selected for transfer to the data bus. Therefore, all of the
most significant bits from all of the registers can be trans-
ferred to the data bus before the next most significant bit is
presented for transfer by the input registers.
Information from the TRI-STATE bus is redistributed by the
CD4514B 4-bit latch/decoder. Using the 4-bit address,
INA –IND, the information on the inhibit line can be trans-
ferred to the addressed output line to the desired output
registers, A–P. This distribution of data bits to the output
registers can be made in many complex patterns. For exam-
ple, all of the most significant bits from the input registers
can be routed into output register A, all of the next most
significant bits into register B, etc. In this way horizontal,
vertical, or other methods of data slicing can be implement-
ed.
TL/F/5994 – 5
CD4514BM/CD4514BC, CD4515BM/CD4515BC 4-Bit Latched/4-to-16 Line Decoders
Physical Dimensions inches (millimeters)

Ceramic Dual-In-Line Package (J)

Order Number CD4514BMJ, CD4514BCJ, CD4515BMJ or CD4515BCJ
NS Package Number J24A

Molded Dual-In-Line Package (N)

Order Number CD4514BMN, CD4514BCN, CD4515BMN or CD4515BCN
NS Package Number N24A

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This file is the datasheet for the following electronic components:

CD4514 - http://www.ti.com/product/cd4514?HQS=TI-null-null-dscatalog-df-pf-null-wwe