Documente Academic
Documente Profesional
Documente Cultură
TIMING CHARACTERISTICS1, 2 (V DD = +2.7 V to +5.5 V, VREF = +VDD [EXT] unless otherwise noted)
Parameter Y Version Units Conditions/Comments
tPOWER-UP 1 µs (max) Power-Up Time of AD7811/AD7812 After Rising Edge of CONVST
t1 2.3 µs (max) Conversion Time
t2 20 ns (min) CONVST Pulsewidth
t3 25 ns (min) SCLK High Pulsewidth
t4 25 ns (min) SCLK Low Pulsewidth
t5 3 5 ns (min) RFS Rising Edge to SCLK Rising Edge Setup Time
t6 3 5 ns (min) TFS Falling Edge to SCLK Falling Edge Setup Time
t7 3 10 ns (max) SCLK Rising Edge to Data Out Valid
t8 10 ns (min) DIN Data Valid to SCLK Falling Edge Setup Time
t9 5 ns (min) DIN Data Valid after SCLK Falling Edge Hold Time
t103, 4 20 ns (max) SCLK Rising Edge to DOUT High Impedance
t11 100 ns (min) DOUT High Impedance to CONVST Falling Edge
NOTES
1
Sample tested to ensure compliance.
2
See Figures 16, 17 and 18.
3
These numbers are measured with the load circuit of Figure 1. They are defined as the time required for the o/p to cross 0.8 V or 2.4 V for V DD = 5 V ± 10% and
0.4 V or 2 V for V DD = 3 V ± 10%.
4
Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 11, quoted in the Timing Characteristics is the true bus relinquish
time of the part and as such is independent of external bus loading capacitances.
Specifications subject to change without notice.
200 A IOL
TO
OUTPUT +2.1V
PIN CL
50pF
200 A IOH
REV. A –3–