Int. J. Elect. Enging. Educ., Vol. 28, pp, 350-360. Manchester D.P., 1991.

Printed in Great Britain

GATE DRIVE CIRCUITS FOR POWER MOSFETS

E. D. COYLE*, J. O'DWYERt and F. DUIGNANt

• Department ofControl Systems and Electrical Engineering, College of
Technology, Kevin St., Dublin, Ireland
t Department ofElectronic and Electrical Engineering, University College
Dublin, Ireland

INTRODUCTION
The information presented in this paper was gathered from various postgrad-
uate projects incorporating power mosfets as switching devices. The work
was a joint venture between the Department of Control Systems and Electrical
Engineering, College of Technology, Kevin St., Dublin 8, and the Depart-
ment of Electronic and Electrical Engineering, University College Dublin.
Three separate projects provided the basis for the paper. All three projects
involved design of full-bridge (H) mosfet converters. Two of the converters were
for use in high frequency welding circuits, while the third was used in an
induction motor speed controller.
By adopting three separate projects, various design techniques were investi-
gated leading to an overall body of knowledge in gate drive circuits for both
Nand P-type mosfet devices.

OVERVIEW OF DRIVE REQUIREMENTS FOR POWER MOSFETS

Advances in recent years in the manufacture of Metal Oxide Field Effect
Transistors (Mosfets) have paved the way for new design criteria in solid-
state switching power circuits. Unlike bipolar power transistors, mosfets are
voltage controlled devices and do not require large continuous base drive sig-
nals when switching large currents. Drive circuits for power mosfet devices
are less complicated than those for bipolar transistors or thyristors.
A further advantage of power mosfets over other switching devices is that
they can be switched at speeds far in excess of bipolar transistors or thyris-
tors. Tum-on and tum-off times of 20 ns are achievable.
Whereas bipolar transistors have a limited working cut-off frequency, typi-
cally less than 50 kHz, power mosfets can be switched at frequencies up to
several hundred kHz.
Mosfets also incorporate an intrinsic body diode which can be useful as a
ftyback diode for certain applications.
An approximate equivalent circuit of a power mosfet is shown in Fig. I. As
shown in the diagram, the mosfet has parasitic capacitances and inductances
between its gate, drain and source. These internal inductances, which are

350
 351

FIG.l Approximateequivalent circuit ofa power mosfet device.

generally of the order of 5 to 10 nH, are more pronounced in circuits operated

at very high frequencies. External lead inductances must also be accounted
for and their effect can be much larger than internal parasitics. Careful circuit
design is essential in order to limit these external stray inductances. The
internal parasitic capacitances are voltage dependent and a graph of their mag-
nitude as a function of voltage is normally supplied on manufacturer's data
sheets.
Power mosfets display a very high d.c. input resistance (several megohms).
In parallel with this there is an equivalent input capacitance, Clss, consisting of
gate-to-source capacitance, C gS' and gate-to-drain capacitance, Cgd •
Mosfets are voltage controlled devices. In order to turn on a device, its
gate-source capacitance, C p , must be charged up to a threshold voltage
level, VI' At this point the resistance between drain and source terminals falls
off rapidly with increasing gate voltage. In addition the effectivegate-source
capacitance assumes a much larger value than its static specification during
its switching transition, owing to the phenomenon known as the Miller
effect'. As the threshold voltage level VI is reached, the drain-source voltage
Vds falls sharply and drain current Id starts to flow. As the drain voltage
decays during the switching cycle, the potential Vgd also decays until Vds
reaches Vp' The capacitance C gd is depletion-dependent and as a result its value
rises dramatically as the voltage between gate and drain diminishes. For
analysis purposes this additional capacitance owing to the Miller effect is
taken account of as part of the overall input capacitance.
The speed at which a mosfet can be turned on or off is related to how
quickly the equivalent input capacitance can be charged or discharged.
The circuit designer must have an outline knowledge of the above-
mentioned points when embarking on a mosfet-circuit related project. The
designer is faced with a series of compromises from which he attempts to
352

arrive at an optimum design for a particular application. For example, the

designer is at liberty to decide how quickly he wishes to switch the devices. If
he switches too slowly he may cause excessive power losses within the tran-
sistors. If, on the other hand, the devices are switched very quickly, additional
stresses are imposed on other components in the circuit. Furthermore, to switch
the devices very quickly requires greater current pulses from the signal source
at the switching transitions 1.2.
Another problem facing the designer is in providing electrical isolation for
mosfets whose sources (N-channel devices) or drains (P-channel devices) are
not ground-referenced. This problem exists for half-bridge or full (H) bridge
circuits. Various means of solving these problems were investigated in the three
projects and these will be discussed individually in the following paragraphs.
Fig. 2 shows the three mosfet bridges in block diagram form. Fig. 2(a) com-
prises two P-type and two N-type devices in a complementary H-bridge
circuit supplying an inductive load, Fig. 2(b) comprises four N-type devices in
a H-bridge arrangement again supplying a transformer (inductive) load and
Fig. 2(c)indicates an all N-type bridge, the load being a single-phase induction
motor. Pulse width modulation (PWM) was used to control all three circuits.
The circuits shown in Figs 2(a) and 2(b) were controlled by means of a d.c.
PWM technique. Circuit 2(c) was controlled by sinusoidal PWM. >

Design A: complementary H-bridge converter

An advanced regulating PWM 18 pin chip, SG1526A, designed by Siliconixv",
was used to provide the driving pulses for the gate circuits of each mosfet in
designs A and B. The SG 1526A can operate with an input voltage from 8 to
40 volts, be set to switch at frequencies from I kHz to 400 kHz, and provide
100 rnA of drive current to the converter switches.

FIG. 2 Mosfet bridge arrangements for (a) design A: four N-channel devices
supplying a transformer load. (b) design B: two P-channel and two N-channel
devices supplying a transformer load, and (c) design C: four N-channel devices
feeding a single-phase induction motor.
 353

In order to arrive at a suitable operating frequency for the bridge, the circuit
of Fig. 3 was designed. The combination of the external capacitor C, and 20 K
potentiometer R, enabled frequency variation from 30 kHz to 230 kHz.
The PWM has dual outputs A and B, each of these outputs providing
signals to diagonally opposing mosfets in the bridge circuit of Fig. 2.
While it is possible to turn on a power mosfet directly from TTL logic, it is
not possible to achieve rapid turn-on times without interfacing with some
suitable buffer circuit. The International Rectifier Hexfet Power Mosfet
Designers Manual provides an informative article wherein calculations are
performed to estimate the amplitude of current pulses drawn by the gate
circuit of a mosfet at switching intervals 1.
In order to supply the current pulse, a CMOS quad power driver (0469 by
Siliconix Incorporated) was used as a buffer between the PWM outputs and
the mosfet gate terminals.I Each output of the D469 may be configured as
being logically inverting or non-inverting and can sink or source a peak
current of 0.5 A. Outputs may be paralleled to increase the available drive
current.
The drive circuit for one half of the bridge incorporating the lower N-
channel device and the upper P-channel device is shown in Fig. 4. The lower
devices are directly driven from D469 drivers connected in the non-inverting
mode. Electrical isolation was not used for these ground-connected devices.
In order to protect the silicon oxide layer between gate and source of the
devices a zener diode was placed close to the gate and source terminals. The

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354

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FIG.4 Gate-drive circuit for one halfofdesign A. A duplicate circuit drives

the other halfof the bridge.

upper P-channel devices require electrical isolation for their control circuitry.
This was achieved by using transformer isolation. The isolation (pulse) trans-
formers were designed with three windings, the extra winding ensuring core
desaturisation during the gate pulse off period. A Siemens torroidal ferrite
core ofN27 type materials was used. The three windings, comprising IS turns,
were wound uniformly on the core. The third (tertiary) winding was connec-
ted in the opposite sense to the primary and secondary windings. This winding,
together with diode D I provides transformer demagnetisation when Q I is
switched off by returning the transformer magnetic energy into the input
supply rail. A 10 volt power supply, referenced to the positive rail, is gener-
ated for the D469's ground pin with a zener diode, a capacitor and resistor.

Design B: N-channel mosfet H-bridge converter

Design B, like design A, is based on a full-bridge H-converter. However, the
bridge comprises four N-channel devices. In this instance similar drive circuits
are required for the upper and lower mosfet devices. Again, the SG I526A
PWM and the D469 driver were used as central elements in the drive circuits.
Electrical isolation was incorporated for both upper and lower devices. In
place of the isolation transformers employed in design A, high speed opto-
 355

couplers 7 were used in design B. Fig. 5 shows the drive circuits for half the
bridge of design B.
In order to exercise some control over the rates of turn-on and turn-off
times of the mosfet devices, variable-resistor/diode circuits were added to the
D469 output stages.
To limit parasitic oscillations at switching points, ferrite beads were installed
on the drive leads close to the gate terminals.
Test waveforms are shown in Fig. 6. Fig. 6(a) shows a plot of the gate-source
voltage. The PWM frequency was set at 100 kHz with a pulse on-time of 4 J.1S.

FIG.5 Gate-drive circuit for one halfofdesign B. A duplicate circuit drives

the other halfof the bridge.

FIG.6 Test waoeformsfor design B: (a) gate-source voltage, (b) opto-coupler

output, (c) unloaded gate-drive circuit, (d) loaded gate-drive circuit. (e) gate
current waveform and ( f ) load voltage waveform.
356

Fig. 6(b) shows the 5 V peak opto-coupler output waveform. Figs 6(c)and
6(d) indicate the drive circuit outputs for unloaded and loaded conditions
respectively. Potentiometer adjustment was made prior to recording waveform
6(d). This is indicated by the slower rise and fall times. Fig. 6(e)demonstrates
that a pulse of current is drawn from the drive circuitry at the on and of
switching intervals. As outlined above this current is due to the capacitive
load presented by the mosfet at switching. Fig. 6(f) shows the load voltage
waveform recorded across the transformer primary winding indicating a
peak-to-peak voltage of 200 V. Waveforms 6(a) to 6(f) were made on the
JJ Instruments PL3 distance/time recorder.

Design C: N-channel mosfet H-bridge converter for driveofan induction motor

control
Design C describes an H-bridge N-channel mosfet inverter used for PWM
speed control of a single-phase induction motor. The circuit under consider-
ation consists essentially of three components, these being gate drive circuit,
gate circuit and bridge circuit. A different design criterion was used to that of
designs A and B. Although an all N-channel mosfet bridge was used, different
techniques were used to drive the mosfets. The frequency of operation of the
bridge is much lower than that of designs A and B. Sinusoidal pulse width
modulation was applied as the controlling technique.
The gate drive circuit is shown in Fig. 7. A microprocessor is used to gener-
ate the pulse width modulation signals. Other means of generating the drive
signal may equally be used. In order to control the full bridge, two drive
circuits as shown in Fig. 7 are necessary, the second being supplied with the
inverse of the drive signal.

Analysis ofgate-drivecircuit
The first stage of the circuit, comprising a comparator OAI, diode D3, resistor
R3, capacitor CI and zener diode ZDI, provides a small delay on the positive
switching edge of the push-pull output stage (Q2 and Q3). This enables a
dead-time between one transistor in a branch of the inverter switching off
and the other switching on. This is important as it gives the former transistor
time to recover and switch off completely before the other device turns on.
The next stage in the circuit provides some flexibility in controlling the
turn-on speed of mosfets. The rate of rise of voltage on the collector of Q I is
controlled by adjusting R8, hence controlling the rate of turn-on of the mosfet.
This helps to minimise the possibility of current pulses passing through the
drain source capacitance of the mosfet which is off when the other mosfet in
the arm of the bridge is turned on.
The secondary side of one of the pulse transformers is shown in Fig. 8.
Ferrite beads together with resistor R I serve to damp out oscillations on the
gate of Q3. Two zener diodes provide positive and negative voltage limiting
on the gate. R2 and CI control the rate of discharge of the gate of Q3 when no
signal is applied. In the event of a failure in the control system it is important
 357

FIG. 7 Gate-drive circuit for design C.

FIG.8 Gate-drive circuitfor one mosfetof design C (from secondary sideof

pulse transformer).

that the main mosfet Q3 should turn itself off after a short period. Adjusting
R2 allows almost linear control of this period. CI also reduces the amount of
reflected voltage on the gate from the drain of Q3 by effectively increasing the
gate-source capacitance.
The device firing sequence operates in the following way. When a positive
going pulse appears across the terminals of the pulse transformer, Q 1
turns off and its intrinsic diode conducts. Q2 and Q3 both turn on as their
358

gate-source capacitances as well as CI are charged. The mosfets will stay on

while CI remains charged above their threshold voltages. To turn offQ3 a
negative going pulse is generated on the terminals of the pulse transformer. This
pulse turns on Q I and charges the gate-source capacitances of Q2 and Q3 as
well as CI to a negative voltage. This provides noise immunity and prevents
spurious turn-on of Q3. The complete bridge circuit is shown in Fig. 9.
Zener diodes are placed across the mosfets to provide over-voltage protec-
tion. RC snubber circuits are also included. L3 and L4 together with Ll
prevent current pulses from passing through the mosfets of either branch. A
diode connected across Ll provides flyback currents with a low impedance
path back to the smoothing capacitor C2. A varistor is included to protect
C2. In order to limit radio frequency (RFI) and mains interference snubbers
were placed across all rectifying diodes and between d.c. and mains earth. The
output inductor helps to limit unwanted high frequency output signals.
Resistors R3 and R4 help to further limit RFI by damping oscillations on the
inductors.
Control voltage and current waveforms are shown in Fig. 10 for a PWM
fundamental frequency of 50 Hz. For measurement purposes the d.c. voltage
was taken from a 120 V isolated supply. Fig. lO(a)shows the gate-current
waveform. The current measurement is derived from the voltage across RI (68R)
in the gate circuit. As seen from the diagram the amplitude of the turn-on
pulse is less than that of the tum-off pulse. This reduces the tum-on speed of
the mosfets but maintains the fast tum-off speeds. Shown in Fig. 10(b)is the
voltage across the gate-source terminals of one of the upper mosfets. The
combined effects of pulse-transformer saturation and residual charge build up
in the gate circuit capacitances are evident in the 'envelope' of the waveshape.
The envelope has a period equal to that of the fundamental harmonic.
Fig. 10(c)shows the drain-source voltage of one of the upper mosfets. The

FIG.9 Complete bridge circuitfor design C.

 359

FIG.10 Control voltage and current waveforms: (a) gate current waveform.
(b) gate-source voltage ofan upper mosfet and (c) drain-source voltage ofan
upper mosfet.

damping effect of the snubber is evident on the tum-off (positive going) edge
of the waveshape.

CONCLUSIONS
It is hoped that the information contained in the paper will be of help to final-
year undergraduate electrical engineering students who may be required to
complete a power electronics project. The study should also be of help to
postgraduate Master of Engineering degree students.
The great advantage of mosfet devices over thyristors and power transistors
is their ability to be switched at much higher operating frequencies than the
latter. The designer must take into consideration that the very fast switching
capabilities of the mosfet can impose stress on other circuit components.
Care must be exercised in the choice of items such as rectifying diodes, zener
diodes and capacitors for use in mosfet switching circuits. Fast-acting soft
recovery rectifiers should be used where possible.
360

Careful circuit design is absolutely essential in order to limit stray parasitic

inductances. Where possible it is advised to limit lead lengths, particularly those
connected to gate terminals. It is advisable to intertwine gate drive circuit
leads (i.e. leads to gate and source for an N-channel device). It is also helpful to
make leads to different mosfets equal in length".
When basic but adequate attention is given to the above points the designer
will find that building of mosfet circuits is relatively uncomplicated. The
ability to switch large currents at high frequency has paved the way for many
exciting developments in power electronics. The combination of power mosfets
and ferrite-cored transformers and inductors has presented the possibility of
adopting conventional 50 Hz mains-designed apparatus (such as the high fre-
quency welding machine) to much more light-weight and efficient designs.

REFERENCES
[I] International Rectifier; Hexfet Power Mosfet Designers Manual, 233 Kansas St., EI Segundo,
California.
[2] Severns, Rudy, and Armijos, Jack, Mospower Applications Handbook, Siliconixs
Incorporated, Santa Clara, California.
[3] Siliconixs Incorporated; Integrated Circuits Data Book (1985).
[4] Chryssis, George; High Frequency Switching Power Supplies, Power General Corporation.
[5] Siemens; Ferrites Data Book (1986/87).
[6] Faulkenberry, Luces M., Systems Troubleshooting Handbook. J. Wiley.
[7] Hewlett Packard, Optoelectronics Designers Catalogue (1991-92).

ABSTRACTS - ENGLISH, FRENCH, GERMAN, SPANISH

Gate drive circuits for power mosfets

Advances in recent years in the manufacture of metal oxide Field Effect Transistors (Mosfets)
have paved the way for new design criteria in solid-state switching power circuits. This paper
gives an insight into the knowledge gained in the design of gate drive circuits for power mosfet
switching devices.

Circuits de commaode de gichettes pour des transistors MOSFET de puissance

Les developpements des dernieres annees dans la fabrication des transistors aeffet de champ
a
(MOSFETS) ont ouvert la voie de nouveaux criteres de conception de circuits de commutation
a
de puissance semi-conducteurs. Cet article donne une vue sur la connaissance obtenue dans la
conception de circuits de commande de gachettes pour des systemes de commutation de puissance
MOSFET.

Galetreiberkreise ffir MOS-FETs

In den letzten Jahren erzietle Fortschritte bei der Herstellung von Metalloxid-Feldeffekttransi-
storen (MOS-FETs) haben den Weg zu neuen Entwurfskriterien fUrHalbleiterschaltkreise
gebahnt. Dieser Artikel gibt einen Einblick in die Kenntnisse, die beim Entwurf von Gatetreiber-
kreisen fUr MOS-FET-Stromschalteinrichtungen erworben werden konnten.

Circ:uitosde maoejo de puerta en mosfets de potencia

Los adalantos obtenidos en la fabricacion de transistores Mosfets ha facilitado nuevos criterios
de diseiio en circuitos interruptores de potencia de estado solido. Este articulo presenta una vision
del conocimiento adquirido en el diseiio de circuitos de manejo de puertas en dispositivos mosfets
interruptores de potencia.