Documente Academic
Documente Profesional
Documente Cultură
for
IP Core Based SoC
Time, Power and Area Optimization
Usha S Mehta
MOTIVATION
IP Core Based SoC
TTM COST
Modular Design
IP Core
Based SoC
Test
Cost
Area
To Be
Hidden Focused
Test
Structure of Power
IP
Core
Test Cost
Test Data Compression
Test Cost
Test Application Time
*Test Time will be 209.34 times in
2024 compared to 2009 [ITRS2009]
Test Power
Dynamic Power
No Availability of Netlist
No Possibility of Insertion or
Modification in Internal Structure
No Possibility of Application of Test
Development Tools like ATPG or
Scan Chain Insertion
To play with Ready Made Test Data
Test Vectors Made up of “1s, 0s and Xs”
The Goal
Ready Made
Test Data
Switching
Test Data Reduction
Compression During
Scan
Test Data Compression
Reduction in Test
Algorithm Compress the Data Transfer Time Addition of
Data /per chip Decoding Time
(one time process)
/per chip
Compressed On Chip
Data Decoder
Addition
Automatic of
Test On Chip
Equipment IPCh
Core
Decoder
to be
Area
Comparator tested
Chip
Switching
Activity??
Objective
To design a test data processing (to prepare for
better compression) and test data compression
method specially for IP core based SoC which
1. does not require any insertion or modification
in internal structure of IP core
2. does not require any test development tools
like ATPG or fault simulation
3. increases the compression
4. reduces the overall test application time (TAT)
5. reduces the switching activity during scan
operation
6. does not increase the on-chip area overhead
Low Power
ATPG Input Reordering Don’t Care
Algorithm Controls Techniques Bit Filling
Switching
Compression
Activity
Don’t Care
Reordering
Bit Filing
Compression
Switching
Compression
&
Activity
Switching Activity
Summary
of
Research Work
Run Length
Based
Test Data Compression
Analysis
Analysis of Existing run length based test data compression
codes like Golomb coding, Frequency Directed Run length
coding (FDR), extended FDR (EFDR), modified FDR (MFDR),
alternating FDR (AFDR), shifted alternating FDR (SAFDR)
for
• Compression results through implementation and
simulation of these codes using MATLAB and C
language.
• Peak power and average power (in terms of switching
activities) through implementation and simulation of
these codes using MATLAB and C language.
• On-chip decoder area overhead through implementation
in VHDL, simulation using Modelsim and synthesis
using Leonardo Spectrum.
HDR-CBF- 1 3 1 1
DV
2-D 3 1 2 3
WTR-CBF- 2 2 1 2
DV
Statistical Code
Based
Test Data Compression
Analysis
Analysis of Existing Statistical compression codes like
selective Huffman code, optimal selective Huffman code,
Variable Length Input Huffman code (VIHC) and Split-
VIHC for
• Compression results through implementation and
simulation of these codes using MATLAB and C
language.
• Peak power and average power (in terms of switching
activities) through implementation and simulation of
these codes using MATLAB and C language.
• On-chip decoder area overhead through implementation
in VHDL, simulation using Modelsim and synthesis
using Leonardo Spectrum.
Publication Ref. J-4 IJCA,
C-7 NUiCONE
Modified Selective Huffman Code
700000
600000
500000
400000
300000
200000
100000
0
s5378 s9234 s13207 s15850 s38417 s38584
Average Power
(average # of transitions)
600000 WTR-CBF-DV + FDR Coding FDBAF + MS-Huffman Coding
500000
400000
300000
200000
100000
0
s5378 s9234 s13207 s15850 s38417 s38584
On-Chip Area Overhead
FDBAF WTR-CBF-DV
• Compression: less • Compression : more
• Area Overhead: less • Area Overhead:
• Power: comparable more
• Power: comparable
THANK YOU